163 lines
5.1 KiB
C
163 lines
5.1 KiB
C
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/*
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* STM32 RCC (only reset and enable registers are implemented)
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*
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* Copyright (c) 2024 Román Cárdenas <rcardenas.rod@gmail.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "trace.h"
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#include "hw/irq.h"
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#include "migration/vmstate.h"
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#include "hw/misc/stm32_rcc.h"
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static void stm32_rcc_reset(DeviceState *dev)
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{
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STM32RccState *s = STM32_RCC(dev);
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for (int i = 0; i < STM32_RCC_NREGS; i++) {
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s->regs[i] = 0;
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}
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}
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static uint64_t stm32_rcc_read(void *opaque, hwaddr addr, unsigned int size)
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{
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STM32RccState *s = STM32_RCC(opaque);
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uint32_t value = 0;
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if (addr > STM32_RCC_DCKCFGR2) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"HWADDR_PRIx"\n",
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__func__, addr);
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} else {
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value = s->regs[addr >> 2];
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}
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trace_stm32_rcc_read(addr, value);
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return value;
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}
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static void stm32_rcc_write(void *opaque, hwaddr addr,
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uint64_t val64, unsigned int size)
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{
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STM32RccState *s = STM32_RCC(opaque);
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uint32_t value = val64;
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uint32_t prev_value, new_value, irq_offset;
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trace_stm32_rcc_write(value, addr);
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if (addr > STM32_RCC_DCKCFGR2) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"HWADDR_PRIx"\n",
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__func__, addr);
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return;
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}
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switch (addr) {
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case STM32_RCC_AHB1_RSTR...STM32_RCC_APB2_RSTR:
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prev_value = s->regs[addr / 4];
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s->regs[addr / 4] = value;
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irq_offset = ((addr - STM32_RCC_AHB1_RSTR) / 4) * 32;
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for (int i = 0; i < 32; i++) {
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new_value = extract32(value, i, 1);
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if (extract32(prev_value, i, 1) && !new_value) {
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trace_stm32_rcc_pulse_reset(irq_offset + i, new_value);
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qemu_set_irq(s->reset_irq[irq_offset + i], new_value);
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}
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}
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return;
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case STM32_RCC_AHB1_ENR...STM32_RCC_APB2_ENR:
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prev_value = s->regs[addr / 4];
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s->regs[addr / 4] = value;
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irq_offset = ((addr - STM32_RCC_AHB1_ENR) / 4) * 32;
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for (int i = 0; i < 32; i++) {
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new_value = extract32(value, i, 1);
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if (!extract32(prev_value, i, 1) && new_value) {
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trace_stm32_rcc_pulse_enable(irq_offset + i, new_value);
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qemu_set_irq(s->enable_irq[irq_offset + i], new_value);
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}
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}
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return;
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default:
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qemu_log_mask(
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LOG_UNIMP,
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"%s: The RCC peripheral only supports enable and reset in QEMU\n",
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__func__
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);
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s->regs[addr >> 2] = value;
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}
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}
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static const MemoryRegionOps stm32_rcc_ops = {
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.read = stm32_rcc_read,
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.write = stm32_rcc_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void stm32_rcc_init(Object *obj)
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{
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STM32RccState *s = STM32_RCC(obj);
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memory_region_init_io(&s->mmio, obj, &stm32_rcc_ops, s,
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TYPE_STM32_RCC, STM32_RCC_PERIPHERAL_SIZE);
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sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
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qdev_init_gpio_out(DEVICE(obj), s->reset_irq, STM32_RCC_NIRQS);
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qdev_init_gpio_out(DEVICE(obj), s->enable_irq, STM32_RCC_NIRQS);
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for (int i = 0; i < STM32_RCC_NIRQS; i++) {
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sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->reset_irq[i]);
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sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->enable_irq[i]);
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}
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}
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static const VMStateDescription vmstate_stm32_rcc = {
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.name = TYPE_STM32_RCC,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (const VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, STM32RccState, STM32_RCC_NREGS),
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VMSTATE_END_OF_LIST()
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}
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};
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static void stm32_rcc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->vmsd = &vmstate_stm32_rcc;
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device_class_set_legacy_reset(dc, stm32_rcc_reset);
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}
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static const TypeInfo stm32_rcc_info = {
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.name = TYPE_STM32_RCC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(STM32RccState),
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.instance_init = stm32_rcc_init,
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.class_init = stm32_rcc_class_init,
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};
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static void stm32_rcc_register_types(void)
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{
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type_register_static(&stm32_rcc_info);
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}
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type_init(stm32_rcc_register_types)
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