2021-07-27 20:48:55 +03:00
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/*
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* Routines common to user and system emulation of load/store.
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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2023-09-12 18:34:28 +03:00
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/*
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* Load helpers for tcg-ldst.h
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*/
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tcg_target_ulong helper_ldub_mmu(CPUArchState *env, uint64_t addr,
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MemOpIdx oi, uintptr_t retaddr)
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{
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tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_8);
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return do_ld1_mmu(env_cpu(env), addr, oi, retaddr, MMU_DATA_LOAD);
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}
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tcg_target_ulong helper_lduw_mmu(CPUArchState *env, uint64_t addr,
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MemOpIdx oi, uintptr_t retaddr)
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{
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tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_16);
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return do_ld2_mmu(env_cpu(env), addr, oi, retaddr, MMU_DATA_LOAD);
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}
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tcg_target_ulong helper_ldul_mmu(CPUArchState *env, uint64_t addr,
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MemOpIdx oi, uintptr_t retaddr)
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{
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tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_32);
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return do_ld4_mmu(env_cpu(env), addr, oi, retaddr, MMU_DATA_LOAD);
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}
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uint64_t helper_ldq_mmu(CPUArchState *env, uint64_t addr,
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MemOpIdx oi, uintptr_t retaddr)
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{
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tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_64);
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return do_ld8_mmu(env_cpu(env), addr, oi, retaddr, MMU_DATA_LOAD);
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}
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/*
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* Provide signed versions of the load routines as well. We can of course
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* avoid this for 64-bit data, or for 32-bit data on 32-bit host.
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*/
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tcg_target_ulong helper_ldsb_mmu(CPUArchState *env, uint64_t addr,
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MemOpIdx oi, uintptr_t retaddr)
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{
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return (int8_t)helper_ldub_mmu(env, addr, oi, retaddr);
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}
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tcg_target_ulong helper_ldsw_mmu(CPUArchState *env, uint64_t addr,
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MemOpIdx oi, uintptr_t retaddr)
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{
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return (int16_t)helper_lduw_mmu(env, addr, oi, retaddr);
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}
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tcg_target_ulong helper_ldsl_mmu(CPUArchState *env, uint64_t addr,
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MemOpIdx oi, uintptr_t retaddr)
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{
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return (int32_t)helper_ldul_mmu(env, addr, oi, retaddr);
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}
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Int128 helper_ld16_mmu(CPUArchState *env, uint64_t addr,
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MemOpIdx oi, uintptr_t retaddr)
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{
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tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_128);
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return do_ld16_mmu(env_cpu(env), addr, oi, retaddr);
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}
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Int128 helper_ld_i128(CPUArchState *env, uint64_t addr, uint32_t oi)
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{
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return helper_ld16_mmu(env, addr, oi, GETPC());
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}
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/*
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* Store helpers for tcg-ldst.h
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*/
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void helper_stb_mmu(CPUArchState *env, uint64_t addr, uint32_t val,
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MemOpIdx oi, uintptr_t ra)
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{
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tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_8);
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do_st1_mmu(env_cpu(env), addr, val, oi, ra);
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}
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void helper_stw_mmu(CPUArchState *env, uint64_t addr, uint32_t val,
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MemOpIdx oi, uintptr_t retaddr)
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{
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tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_16);
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do_st2_mmu(env_cpu(env), addr, val, oi, retaddr);
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}
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void helper_stl_mmu(CPUArchState *env, uint64_t addr, uint32_t val,
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MemOpIdx oi, uintptr_t retaddr)
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{
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tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_32);
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do_st4_mmu(env_cpu(env), addr, val, oi, retaddr);
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}
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void helper_stq_mmu(CPUArchState *env, uint64_t addr, uint64_t val,
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MemOpIdx oi, uintptr_t retaddr)
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{
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tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_64);
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do_st8_mmu(env_cpu(env), addr, val, oi, retaddr);
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}
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void helper_st16_mmu(CPUArchState *env, uint64_t addr, Int128 val,
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MemOpIdx oi, uintptr_t retaddr)
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{
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tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_128);
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do_st16_mmu(env_cpu(env), addr, val, oi, retaddr);
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}
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void helper_st_i128(CPUArchState *env, uint64_t addr, Int128 val, MemOpIdx oi)
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{
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helper_st16_mmu(env, addr, val, oi, GETPC());
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}
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/*
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* Load helpers for cpu_ldst.h
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*/
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static void plugin_load_cb(CPUArchState *env, abi_ptr addr, MemOpIdx oi)
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{
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qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R);
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}
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uint8_t cpu_ldb_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t ra)
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{
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uint8_t ret;
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tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_UB);
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ret = do_ld1_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD);
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plugin_load_cb(env, addr, oi);
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return ret;
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}
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uint16_t cpu_ldw_mmu(CPUArchState *env, abi_ptr addr,
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MemOpIdx oi, uintptr_t ra)
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{
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uint16_t ret;
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tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_16);
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ret = do_ld2_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD);
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plugin_load_cb(env, addr, oi);
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return ret;
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}
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uint32_t cpu_ldl_mmu(CPUArchState *env, abi_ptr addr,
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MemOpIdx oi, uintptr_t ra)
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{
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uint32_t ret;
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tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_32);
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ret = do_ld4_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD);
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plugin_load_cb(env, addr, oi);
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return ret;
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}
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uint64_t cpu_ldq_mmu(CPUArchState *env, abi_ptr addr,
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MemOpIdx oi, uintptr_t ra)
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{
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uint64_t ret;
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tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_64);
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ret = do_ld8_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD);
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plugin_load_cb(env, addr, oi);
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return ret;
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}
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Int128 cpu_ld16_mmu(CPUArchState *env, abi_ptr addr,
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MemOpIdx oi, uintptr_t ra)
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{
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Int128 ret;
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tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_128);
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ret = do_ld16_mmu(env_cpu(env), addr, oi, ra);
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plugin_load_cb(env, addr, oi);
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return ret;
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}
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/*
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* Store helpers for cpu_ldst.h
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*/
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static void plugin_store_cb(CPUArchState *env, abi_ptr addr, MemOpIdx oi)
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{
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qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W);
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}
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void cpu_stb_mmu(CPUArchState *env, abi_ptr addr, uint8_t val,
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MemOpIdx oi, uintptr_t retaddr)
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{
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helper_stb_mmu(env, addr, val, oi, retaddr);
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plugin_store_cb(env, addr, oi);
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}
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void cpu_stw_mmu(CPUArchState *env, abi_ptr addr, uint16_t val,
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MemOpIdx oi, uintptr_t retaddr)
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{
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tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_16);
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do_st2_mmu(env_cpu(env), addr, val, oi, retaddr);
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plugin_store_cb(env, addr, oi);
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}
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void cpu_stl_mmu(CPUArchState *env, abi_ptr addr, uint32_t val,
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MemOpIdx oi, uintptr_t retaddr)
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{
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tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_32);
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do_st4_mmu(env_cpu(env), addr, val, oi, retaddr);
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plugin_store_cb(env, addr, oi);
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}
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void cpu_stq_mmu(CPUArchState *env, abi_ptr addr, uint64_t val,
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MemOpIdx oi, uintptr_t retaddr)
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{
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tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_64);
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do_st8_mmu(env_cpu(env), addr, val, oi, retaddr);
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plugin_store_cb(env, addr, oi);
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}
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void cpu_st16_mmu(CPUArchState *env, abi_ptr addr, Int128 val,
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MemOpIdx oi, uintptr_t retaddr)
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{
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tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_128);
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do_st16_mmu(env_cpu(env), addr, val, oi, retaddr);
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plugin_store_cb(env, addr, oi);
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}
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/*
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* Wrappers of the above
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*/
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2021-07-27 20:48:55 +03:00
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uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra)
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{
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MemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
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return cpu_ldb_mmu(env, addr, oi, ra);
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}
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int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra)
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{
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return (int8_t)cpu_ldub_mmuidx_ra(env, addr, mmu_idx, ra);
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}
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uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra)
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{
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MemOpIdx oi = make_memop_idx(MO_BEUW | MO_UNALN, mmu_idx);
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2023-05-20 03:29:27 +03:00
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return cpu_ldw_mmu(env, addr, oi, ra);
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2021-07-27 20:48:55 +03:00
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}
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int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra)
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{
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return (int16_t)cpu_lduw_be_mmuidx_ra(env, addr, mmu_idx, ra);
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}
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uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra)
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{
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MemOpIdx oi = make_memop_idx(MO_BEUL | MO_UNALN, mmu_idx);
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2023-05-20 03:29:27 +03:00
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return cpu_ldl_mmu(env, addr, oi, ra);
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2021-07-27 20:48:55 +03:00
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}
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uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra)
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{
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2022-01-07 00:00:51 +03:00
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MemOpIdx oi = make_memop_idx(MO_BEUQ | MO_UNALN, mmu_idx);
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2023-05-20 03:29:27 +03:00
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return cpu_ldq_mmu(env, addr, oi, ra);
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2021-07-27 20:48:55 +03:00
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}
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uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra)
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{
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MemOpIdx oi = make_memop_idx(MO_LEUW | MO_UNALN, mmu_idx);
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2023-05-20 03:29:27 +03:00
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return cpu_ldw_mmu(env, addr, oi, ra);
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2021-07-27 20:48:55 +03:00
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}
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int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra)
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{
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return (int16_t)cpu_lduw_le_mmuidx_ra(env, addr, mmu_idx, ra);
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}
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uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra)
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{
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MemOpIdx oi = make_memop_idx(MO_LEUL | MO_UNALN, mmu_idx);
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2023-05-20 03:29:27 +03:00
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return cpu_ldl_mmu(env, addr, oi, ra);
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2021-07-27 20:48:55 +03:00
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}
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uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra)
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{
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2022-01-07 00:00:51 +03:00
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MemOpIdx oi = make_memop_idx(MO_LEUQ | MO_UNALN, mmu_idx);
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2023-05-20 03:29:27 +03:00
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return cpu_ldq_mmu(env, addr, oi, ra);
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2021-07-27 20:48:55 +03:00
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}
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void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
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int mmu_idx, uintptr_t ra)
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{
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MemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
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cpu_stb_mmu(env, addr, val, oi, ra);
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}
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void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
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int mmu_idx, uintptr_t ra)
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{
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MemOpIdx oi = make_memop_idx(MO_BEUW | MO_UNALN, mmu_idx);
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2023-05-20 03:29:27 +03:00
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cpu_stw_mmu(env, addr, val, oi, ra);
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2021-07-27 20:48:55 +03:00
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}
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|
|
|
|
|
|
|
void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
|
|
|
|
int mmu_idx, uintptr_t ra)
|
|
|
|
{
|
|
|
|
MemOpIdx oi = make_memop_idx(MO_BEUL | MO_UNALN, mmu_idx);
|
2023-05-20 03:29:27 +03:00
|
|
|
cpu_stl_mmu(env, addr, val, oi, ra);
|
2021-07-27 20:48:55 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
|
|
|
|
int mmu_idx, uintptr_t ra)
|
|
|
|
{
|
2022-01-07 00:00:51 +03:00
|
|
|
MemOpIdx oi = make_memop_idx(MO_BEUQ | MO_UNALN, mmu_idx);
|
2023-05-20 03:29:27 +03:00
|
|
|
cpu_stq_mmu(env, addr, val, oi, ra);
|
2021-07-27 20:48:55 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
|
|
|
|
int mmu_idx, uintptr_t ra)
|
|
|
|
{
|
|
|
|
MemOpIdx oi = make_memop_idx(MO_LEUW | MO_UNALN, mmu_idx);
|
2023-05-20 03:29:27 +03:00
|
|
|
cpu_stw_mmu(env, addr, val, oi, ra);
|
2021-07-27 20:48:55 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
|
|
|
|
int mmu_idx, uintptr_t ra)
|
|
|
|
{
|
|
|
|
MemOpIdx oi = make_memop_idx(MO_LEUL | MO_UNALN, mmu_idx);
|
2023-05-20 03:29:27 +03:00
|
|
|
cpu_stl_mmu(env, addr, val, oi, ra);
|
2021-07-27 20:48:55 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
|
|
|
|
int mmu_idx, uintptr_t ra)
|
|
|
|
{
|
2022-01-07 00:00:51 +03:00
|
|
|
MemOpIdx oi = make_memop_idx(MO_LEUQ | MO_UNALN, mmu_idx);
|
2023-05-20 03:29:27 +03:00
|
|
|
cpu_stq_mmu(env, addr, val, oi, ra);
|
2021-07-27 20:48:55 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
/*--------------------------*/
|
|
|
|
|
|
|
|
uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
|
|
|
|
{
|
2024-01-29 13:35:06 +03:00
|
|
|
int mmu_index = cpu_mmu_index(env_cpu(env), false);
|
|
|
|
return cpu_ldub_mmuidx_ra(env, addr, mmu_index, ra);
|
2021-07-27 20:48:55 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
|
|
|
|
{
|
|
|
|
return (int8_t)cpu_ldub_data_ra(env, addr, ra);
|
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
|
|
|
|
{
|
2024-01-29 13:35:06 +03:00
|
|
|
int mmu_index = cpu_mmu_index(env_cpu(env), false);
|
|
|
|
return cpu_lduw_be_mmuidx_ra(env, addr, mmu_index, ra);
|
2021-07-27 20:48:55 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
|
|
|
|
{
|
|
|
|
return (int16_t)cpu_lduw_be_data_ra(env, addr, ra);
|
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
|
|
|
|
{
|
2024-01-29 13:35:06 +03:00
|
|
|
int mmu_index = cpu_mmu_index(env_cpu(env), false);
|
|
|
|
return cpu_ldl_be_mmuidx_ra(env, addr, mmu_index, ra);
|
2021-07-27 20:48:55 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
|
|
|
|
{
|
2024-01-29 13:35:06 +03:00
|
|
|
int mmu_index = cpu_mmu_index(env_cpu(env), false);
|
|
|
|
return cpu_ldq_be_mmuidx_ra(env, addr, mmu_index, ra);
|
2021-07-27 20:48:55 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
|
|
|
|
{
|
2024-01-29 13:35:06 +03:00
|
|
|
int mmu_index = cpu_mmu_index(env_cpu(env), false);
|
|
|
|
return cpu_lduw_le_mmuidx_ra(env, addr, mmu_index, ra);
|
2021-07-27 20:48:55 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
|
|
|
|
{
|
|
|
|
return (int16_t)cpu_lduw_le_data_ra(env, addr, ra);
|
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
|
|
|
|
{
|
2024-01-29 13:35:06 +03:00
|
|
|
int mmu_index = cpu_mmu_index(env_cpu(env), false);
|
|
|
|
return cpu_ldl_le_mmuidx_ra(env, addr, mmu_index, ra);
|
2021-07-27 20:48:55 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
|
|
|
|
{
|
2024-01-29 13:35:06 +03:00
|
|
|
int mmu_index = cpu_mmu_index(env_cpu(env), false);
|
|
|
|
return cpu_ldq_le_mmuidx_ra(env, addr, mmu_index, ra);
|
2021-07-27 20:48:55 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
void cpu_stb_data_ra(CPUArchState *env, abi_ptr addr,
|
|
|
|
uint32_t val, uintptr_t ra)
|
|
|
|
{
|
2024-01-29 13:35:06 +03:00
|
|
|
int mmu_index = cpu_mmu_index(env_cpu(env), false);
|
|
|
|
cpu_stb_mmuidx_ra(env, addr, val, mmu_index, ra);
|
2021-07-27 20:48:55 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr addr,
|
|
|
|
uint32_t val, uintptr_t ra)
|
|
|
|
{
|
2024-01-29 13:35:06 +03:00
|
|
|
int mmu_index = cpu_mmu_index(env_cpu(env), false);
|
|
|
|
cpu_stw_be_mmuidx_ra(env, addr, val, mmu_index, ra);
|
2021-07-27 20:48:55 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr addr,
|
|
|
|
uint32_t val, uintptr_t ra)
|
|
|
|
{
|
2024-01-29 13:35:06 +03:00
|
|
|
int mmu_index = cpu_mmu_index(env_cpu(env), false);
|
|
|
|
cpu_stl_be_mmuidx_ra(env, addr, val, mmu_index, ra);
|
2021-07-27 20:48:55 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr addr,
|
|
|
|
uint64_t val, uintptr_t ra)
|
|
|
|
{
|
2024-01-29 13:35:06 +03:00
|
|
|
int mmu_index = cpu_mmu_index(env_cpu(env), false);
|
|
|
|
cpu_stq_be_mmuidx_ra(env, addr, val, mmu_index, ra);
|
2021-07-27 20:48:55 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr addr,
|
|
|
|
uint32_t val, uintptr_t ra)
|
|
|
|
{
|
2024-01-29 13:35:06 +03:00
|
|
|
int mmu_index = cpu_mmu_index(env_cpu(env), false);
|
|
|
|
cpu_stw_le_mmuidx_ra(env, addr, val, mmu_index, ra);
|
2021-07-27 20:48:55 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr addr,
|
|
|
|
uint32_t val, uintptr_t ra)
|
|
|
|
{
|
2024-01-29 13:35:06 +03:00
|
|
|
int mmu_index = cpu_mmu_index(env_cpu(env), false);
|
|
|
|
cpu_stl_le_mmuidx_ra(env, addr, val, mmu_index, ra);
|
2021-07-27 20:48:55 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr addr,
|
|
|
|
uint64_t val, uintptr_t ra)
|
|
|
|
{
|
2024-01-29 13:35:06 +03:00
|
|
|
int mmu_index = cpu_mmu_index(env_cpu(env), false);
|
|
|
|
cpu_stq_le_mmuidx_ra(env, addr, val, mmu_index, ra);
|
2021-07-27 20:48:55 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
/*--------------------------*/
|
|
|
|
|
|
|
|
uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr addr)
|
|
|
|
{
|
|
|
|
return cpu_ldub_data_ra(env, addr, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
int cpu_ldsb_data(CPUArchState *env, abi_ptr addr)
|
|
|
|
{
|
|
|
|
return (int8_t)cpu_ldub_data(env, addr);
|
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr addr)
|
|
|
|
{
|
|
|
|
return cpu_lduw_be_data_ra(env, addr, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
int cpu_ldsw_be_data(CPUArchState *env, abi_ptr addr)
|
|
|
|
{
|
|
|
|
return (int16_t)cpu_lduw_be_data(env, addr);
|
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr addr)
|
|
|
|
{
|
|
|
|
return cpu_ldl_be_data_ra(env, addr, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr addr)
|
|
|
|
{
|
|
|
|
return cpu_ldq_be_data_ra(env, addr, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr addr)
|
|
|
|
{
|
|
|
|
return cpu_lduw_le_data_ra(env, addr, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
int cpu_ldsw_le_data(CPUArchState *env, abi_ptr addr)
|
|
|
|
{
|
|
|
|
return (int16_t)cpu_lduw_le_data(env, addr);
|
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr addr)
|
|
|
|
{
|
|
|
|
return cpu_ldl_le_data_ra(env, addr, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr addr)
|
|
|
|
{
|
|
|
|
return cpu_ldq_le_data_ra(env, addr, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
void cpu_stb_data(CPUArchState *env, abi_ptr addr, uint32_t val)
|
|
|
|
{
|
|
|
|
cpu_stb_data_ra(env, addr, val, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
void cpu_stw_be_data(CPUArchState *env, abi_ptr addr, uint32_t val)
|
|
|
|
{
|
|
|
|
cpu_stw_be_data_ra(env, addr, val, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
void cpu_stl_be_data(CPUArchState *env, abi_ptr addr, uint32_t val)
|
|
|
|
{
|
|
|
|
cpu_stl_be_data_ra(env, addr, val, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
void cpu_stq_be_data(CPUArchState *env, abi_ptr addr, uint64_t val)
|
|
|
|
{
|
|
|
|
cpu_stq_be_data_ra(env, addr, val, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
void cpu_stw_le_data(CPUArchState *env, abi_ptr addr, uint32_t val)
|
|
|
|
{
|
|
|
|
cpu_stw_le_data_ra(env, addr, val, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
void cpu_stl_le_data(CPUArchState *env, abi_ptr addr, uint32_t val)
|
|
|
|
{
|
|
|
|
cpu_stl_le_data_ra(env, addr, val, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
void cpu_stq_le_data(CPUArchState *env, abi_ptr addr, uint64_t val)
|
|
|
|
{
|
|
|
|
cpu_stq_le_data_ra(env, addr, val, 0);
|
|
|
|
}
|