2012-03-02 23:28:46 +04:00
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/*
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* QEMU 8253/8254 - internal interfaces
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*
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* Copyright (c) 2011 Jan Kiszka, Siemens AG
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef QEMU_I8254_INTERNAL_H
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#define QEMU_I8254_INTERNAL_H
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2013-02-05 20:06:20 +04:00
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#include "hw/isa/isa.h"
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2019-08-12 08:23:31 +03:00
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#include "hw/timer/i8254.h"
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2017-10-17 19:44:15 +03:00
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#include "qemu/timer.h"
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2012-03-02 23:28:46 +04:00
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typedef struct PITChannelState {
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int count; /* can be 65536 */
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uint16_t latched_count;
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uint8_t count_latched;
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uint8_t status_latched;
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uint8_t status;
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uint8_t read_state;
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uint8_t write_state;
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uint8_t write_latch;
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uint8_t rw_mode;
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uint8_t mode;
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uint8_t bcd; /* not supported */
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uint8_t gate; /* timer start */
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int64_t count_load_time;
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/* irq handling */
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int64_t next_transition_time;
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QEMUTimer *irq_timer;
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qemu_irq irq;
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uint32_t irq_disabled;
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} PITChannelState;
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2020-08-25 22:20:14 +03:00
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struct PITCommonState {
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2012-03-02 23:28:46 +04:00
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ISADevice dev;
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MemoryRegion ioports;
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uint32_t iobase;
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PITChannelState channels[3];
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2020-08-25 22:20:14 +03:00
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};
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2012-03-02 23:28:46 +04:00
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2020-08-25 22:20:14 +03:00
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struct PITCommonClass {
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2023-02-14 14:48:15 +03:00
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DeviceClass parent_class;
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2012-03-02 23:28:46 +04:00
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void (*set_channel_gate)(PITCommonState *s, PITChannelState *sc, int val);
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void (*get_channel_info)(PITCommonState *s, PITChannelState *sc,
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PITChannelInfo *info);
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void (*pre_save)(PITCommonState *s);
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void (*post_load)(PITCommonState *s);
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2020-08-25 22:20:14 +03:00
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};
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2012-03-02 23:28:46 +04:00
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int pit_get_out(PITChannelState *s, int64_t current_time);
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int64_t pit_get_next_transition_time(PITChannelState *s, int64_t current_time);
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void pit_get_channel_info_common(PITCommonState *s, PITChannelState *sc,
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PITChannelInfo *info);
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void pit_reset_common(PITCommonState *s);
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2016-06-29 16:29:06 +03:00
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#endif /* QEMU_I8254_INTERNAL_H */
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