2013-04-16 18:45:16 +04:00
|
|
|
/*
|
|
|
|
* libqos PCI bindings
|
|
|
|
*
|
|
|
|
* Copyright IBM, Corp. 2012-2013
|
|
|
|
*
|
|
|
|
* Authors:
|
|
|
|
* Anthony Liguori <aliguori@us.ibm.com>
|
|
|
|
*
|
|
|
|
* This work is licensed under the terms of the GNU GPL, version 2 or later.
|
|
|
|
* See the COPYING file in the top-level directory.
|
|
|
|
*/
|
|
|
|
|
2016-02-08 21:08:51 +03:00
|
|
|
#include "qemu/osdep.h"
|
2020-08-04 21:00:40 +03:00
|
|
|
#include "pci.h"
|
2013-04-16 18:45:16 +04:00
|
|
|
|
2021-12-08 16:03:47 +03:00
|
|
|
#include "hw/pci/pci.h"
|
|
|
|
#include "hw/pci/pci_bridge.h"
|
2013-04-16 18:45:16 +04:00
|
|
|
#include "hw/pci/pci_regs.h"
|
2016-10-19 06:06:51 +03:00
|
|
|
#include "qemu/host-utils.h"
|
2020-08-04 21:00:40 +03:00
|
|
|
#include "qgraph.h"
|
2013-04-16 18:45:16 +04:00
|
|
|
|
|
|
|
void qpci_device_foreach(QPCIBus *bus, int vendor_id, int device_id,
|
|
|
|
void (*func)(QPCIDevice *dev, int devfn, void *data),
|
|
|
|
void *data)
|
|
|
|
{
|
|
|
|
int slot;
|
|
|
|
|
|
|
|
for (slot = 0; slot < 32; slot++) {
|
|
|
|
int fn;
|
|
|
|
|
|
|
|
for (fn = 0; fn < 8; fn++) {
|
|
|
|
QPCIDevice *dev;
|
|
|
|
|
|
|
|
dev = qpci_device_find(bus, QPCI_DEVFN(slot, fn));
|
|
|
|
if (!dev) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (vendor_id != -1 &&
|
|
|
|
qpci_config_readw(dev, PCI_VENDOR_ID) != vendor_id) {
|
2015-12-18 17:13:32 +03:00
|
|
|
g_free(dev);
|
2013-04-16 18:45:16 +04:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (device_id != -1 &&
|
|
|
|
qpci_config_readw(dev, PCI_DEVICE_ID) != device_id) {
|
2015-12-18 17:13:32 +03:00
|
|
|
g_free(dev);
|
2013-04-16 18:45:16 +04:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
func(dev, QPCI_DEVFN(slot, fn), data);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-08-09 13:44:56 +03:00
|
|
|
bool qpci_has_buggy_msi(QPCIDevice *dev)
|
|
|
|
{
|
|
|
|
return dev->bus->has_buggy_msi;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool qpci_check_buggy_msi(QPCIDevice *dev)
|
|
|
|
{
|
|
|
|
if (qpci_has_buggy_msi(dev)) {
|
|
|
|
g_test_skip("Skipping due to incomplete support for MSI");
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2018-07-03 17:53:10 +03:00
|
|
|
static void qpci_device_set(QPCIDevice *dev, QPCIBus *bus, int devfn)
|
|
|
|
{
|
|
|
|
g_assert(dev);
|
|
|
|
|
|
|
|
dev->bus = bus;
|
|
|
|
dev->devfn = devfn;
|
|
|
|
}
|
|
|
|
|
2013-04-16 18:45:16 +04:00
|
|
|
QPCIDevice *qpci_device_find(QPCIBus *bus, int devfn)
|
|
|
|
{
|
|
|
|
QPCIDevice *dev;
|
|
|
|
|
|
|
|
dev = g_malloc0(sizeof(*dev));
|
2018-07-03 17:53:10 +03:00
|
|
|
qpci_device_set(dev, bus, devfn);
|
2013-04-16 18:45:16 +04:00
|
|
|
|
|
|
|
if (qpci_config_readw(dev, PCI_VENDOR_ID) == 0xFFFF) {
|
|
|
|
g_free(dev);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return dev;
|
|
|
|
}
|
|
|
|
|
2018-07-03 17:53:10 +03:00
|
|
|
void qpci_device_init(QPCIDevice *dev, QPCIBus *bus, QPCIAddress *addr)
|
|
|
|
{
|
|
|
|
uint16_t vendor_id, device_id;
|
|
|
|
|
|
|
|
qpci_device_set(dev, bus, addr->devfn);
|
|
|
|
vendor_id = qpci_config_readw(dev, PCI_VENDOR_ID);
|
|
|
|
device_id = qpci_config_readw(dev, PCI_DEVICE_ID);
|
|
|
|
g_assert(!addr->vendor_id || vendor_id == addr->vendor_id);
|
|
|
|
g_assert(!addr->device_id || device_id == addr->device_id);
|
|
|
|
}
|
|
|
|
|
2021-12-08 16:03:47 +03:00
|
|
|
static uint8_t qpci_find_resource_reserve_capability(QPCIDevice *dev)
|
|
|
|
{
|
|
|
|
uint16_t device_id;
|
|
|
|
uint8_t cap = 0;
|
|
|
|
|
|
|
|
if (qpci_config_readw(dev, PCI_VENDOR_ID) != PCI_VENDOR_ID_REDHAT) {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
device_id = qpci_config_readw(dev, PCI_DEVICE_ID);
|
|
|
|
|
|
|
|
if (device_id != PCI_DEVICE_ID_REDHAT_PCIE_RP &&
|
|
|
|
device_id != PCI_DEVICE_ID_REDHAT_BRIDGE) {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
do {
|
|
|
|
cap = qpci_find_capability(dev, PCI_CAP_ID_VNDR, cap);
|
|
|
|
} while (cap &&
|
|
|
|
qpci_config_readb(dev, cap + REDHAT_PCI_CAP_TYPE_OFFSET) !=
|
|
|
|
REDHAT_PCI_CAP_RESOURCE_RESERVE);
|
|
|
|
if (cap) {
|
|
|
|
uint8_t cap_len = qpci_config_readb(dev, cap + PCI_CAP_FLAGS);
|
|
|
|
if (cap_len < REDHAT_PCI_CAP_RES_RESERVE_CAP_SIZE) {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return cap;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void qpci_secondary_buses_rec(QPCIBus *qbus, int bus, int *pci_bus)
|
|
|
|
{
|
|
|
|
QPCIDevice *dev;
|
|
|
|
uint16_t class;
|
|
|
|
uint8_t pribus, secbus, subbus;
|
|
|
|
int index;
|
|
|
|
|
|
|
|
for (index = 0; index < 32; index++) {
|
|
|
|
dev = qpci_device_find(qbus, QPCI_DEVFN(bus + index, 0));
|
|
|
|
if (dev == NULL) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
class = qpci_config_readw(dev, PCI_CLASS_DEVICE);
|
|
|
|
if (class == PCI_CLASS_BRIDGE_PCI) {
|
|
|
|
qpci_config_writeb(dev, PCI_SECONDARY_BUS, 255);
|
|
|
|
qpci_config_writeb(dev, PCI_SUBORDINATE_BUS, 0);
|
|
|
|
}
|
|
|
|
g_free(dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
for (index = 0; index < 32; index++) {
|
|
|
|
dev = qpci_device_find(qbus, QPCI_DEVFN(bus + index, 0));
|
|
|
|
if (dev == NULL) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
class = qpci_config_readw(dev, PCI_CLASS_DEVICE);
|
|
|
|
if (class != PCI_CLASS_BRIDGE_PCI) {
|
|
|
|
g_free(dev);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
pribus = qpci_config_readb(dev, PCI_PRIMARY_BUS);
|
|
|
|
if (pribus != bus) {
|
|
|
|
qpci_config_writeb(dev, PCI_PRIMARY_BUS, bus);
|
|
|
|
}
|
|
|
|
|
|
|
|
secbus = qpci_config_readb(dev, PCI_SECONDARY_BUS);
|
|
|
|
(*pci_bus)++;
|
|
|
|
if (*pci_bus != secbus) {
|
|
|
|
secbus = *pci_bus;
|
|
|
|
qpci_config_writeb(dev, PCI_SECONDARY_BUS, secbus);
|
|
|
|
}
|
|
|
|
|
|
|
|
subbus = qpci_config_readb(dev, PCI_SUBORDINATE_BUS);
|
|
|
|
qpci_config_writeb(dev, PCI_SUBORDINATE_BUS, 255);
|
|
|
|
|
|
|
|
qpci_secondary_buses_rec(qbus, secbus << 5, pci_bus);
|
|
|
|
|
|
|
|
if (subbus != *pci_bus) {
|
|
|
|
uint8_t res_bus = *pci_bus;
|
|
|
|
uint8_t cap = qpci_find_resource_reserve_capability(dev);
|
|
|
|
|
|
|
|
if (cap) {
|
|
|
|
uint32_t tmp_res_bus;
|
|
|
|
|
|
|
|
tmp_res_bus = qpci_config_readl(dev, cap +
|
|
|
|
REDHAT_PCI_CAP_RES_RESERVE_BUS_RES);
|
|
|
|
if (tmp_res_bus != (uint32_t)-1) {
|
|
|
|
res_bus = tmp_res_bus & 0xFF;
|
|
|
|
if ((uint8_t)(res_bus + secbus) < secbus ||
|
|
|
|
(uint8_t)(res_bus + secbus) < res_bus) {
|
|
|
|
res_bus = 0;
|
|
|
|
}
|
|
|
|
if (secbus + res_bus > *pci_bus) {
|
|
|
|
res_bus = secbus + res_bus;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
subbus = res_bus;
|
|
|
|
*pci_bus = res_bus;
|
|
|
|
}
|
|
|
|
|
|
|
|
qpci_config_writeb(dev, PCI_SUBORDINATE_BUS, subbus);
|
|
|
|
g_free(dev);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
int qpci_secondary_buses_init(QPCIBus *bus)
|
|
|
|
{
|
|
|
|
int last_bus = 0;
|
|
|
|
|
|
|
|
qpci_secondary_buses_rec(bus, 0, &last_bus);
|
|
|
|
|
|
|
|
return last_bus;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2013-04-16 18:45:16 +04:00
|
|
|
void qpci_device_enable(QPCIDevice *dev)
|
|
|
|
{
|
|
|
|
uint16_t cmd;
|
|
|
|
|
|
|
|
/* FIXME -- does this need to be a bus callout? */
|
|
|
|
cmd = qpci_config_readw(dev, PCI_COMMAND);
|
2013-03-13 20:00:40 +04:00
|
|
|
cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
|
2013-04-16 18:45:16 +04:00
|
|
|
qpci_config_writew(dev, PCI_COMMAND, cmd);
|
2014-08-21 21:44:35 +04:00
|
|
|
|
|
|
|
/* Verify the bits are now set. */
|
|
|
|
cmd = qpci_config_readw(dev, PCI_COMMAND);
|
|
|
|
g_assert_cmphex(cmd & PCI_COMMAND_IO, ==, PCI_COMMAND_IO);
|
|
|
|
g_assert_cmphex(cmd & PCI_COMMAND_MEMORY, ==, PCI_COMMAND_MEMORY);
|
|
|
|
g_assert_cmphex(cmd & PCI_COMMAND_MASTER, ==, PCI_COMMAND_MASTER);
|
2013-04-16 18:45:16 +04:00
|
|
|
}
|
|
|
|
|
2019-10-23 13:04:19 +03:00
|
|
|
/**
|
|
|
|
* qpci_find_capability:
|
|
|
|
* @dev: the PCI device
|
|
|
|
* @id: the PCI Capability ID (PCI_CAP_ID_*)
|
|
|
|
* @start_addr: 0 to begin iteration or the last return value to continue
|
|
|
|
* iteration
|
|
|
|
*
|
|
|
|
* Iterate over the PCI Capabilities List.
|
|
|
|
*
|
|
|
|
* Returns: PCI Configuration Space offset of the capabililty structure or
|
|
|
|
* 0 if no further matching capability is found
|
|
|
|
*/
|
|
|
|
uint8_t qpci_find_capability(QPCIDevice *dev, uint8_t id, uint8_t start_addr)
|
2014-09-01 14:07:59 +04:00
|
|
|
{
|
|
|
|
uint8_t cap;
|
2019-10-23 13:04:19 +03:00
|
|
|
uint8_t addr;
|
|
|
|
|
|
|
|
if (start_addr) {
|
|
|
|
addr = qpci_config_readb(dev, start_addr + PCI_CAP_LIST_NEXT);
|
|
|
|
} else {
|
|
|
|
addr = qpci_config_readb(dev, PCI_CAPABILITY_LIST);
|
|
|
|
}
|
2014-09-01 14:07:59 +04:00
|
|
|
|
|
|
|
do {
|
|
|
|
cap = qpci_config_readb(dev, addr);
|
|
|
|
if (cap != id) {
|
|
|
|
addr = qpci_config_readb(dev, addr + PCI_CAP_LIST_NEXT);
|
|
|
|
}
|
|
|
|
} while (cap != id && addr != 0);
|
|
|
|
|
|
|
|
return addr;
|
|
|
|
}
|
|
|
|
|
|
|
|
void qpci_msix_enable(QPCIDevice *dev)
|
|
|
|
{
|
|
|
|
uint8_t addr;
|
|
|
|
uint16_t val;
|
|
|
|
uint32_t table;
|
|
|
|
uint8_t bir_table;
|
|
|
|
uint8_t bir_pba;
|
|
|
|
|
2019-10-23 13:04:19 +03:00
|
|
|
addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX, 0);
|
2014-09-01 14:07:59 +04:00
|
|
|
g_assert_cmphex(addr, !=, 0);
|
|
|
|
|
|
|
|
val = qpci_config_readw(dev, addr + PCI_MSIX_FLAGS);
|
|
|
|
qpci_config_writew(dev, addr + PCI_MSIX_FLAGS, val | PCI_MSIX_FLAGS_ENABLE);
|
|
|
|
|
|
|
|
table = qpci_config_readl(dev, addr + PCI_MSIX_TABLE);
|
|
|
|
bir_table = table & PCI_MSIX_FLAGS_BIRMASK;
|
2016-10-24 07:52:06 +03:00
|
|
|
dev->msix_table_bar = qpci_iomap(dev, bir_table, NULL);
|
|
|
|
dev->msix_table_off = table & ~PCI_MSIX_FLAGS_BIRMASK;
|
2014-09-01 14:07:59 +04:00
|
|
|
|
|
|
|
table = qpci_config_readl(dev, addr + PCI_MSIX_PBA);
|
|
|
|
bir_pba = table & PCI_MSIX_FLAGS_BIRMASK;
|
|
|
|
if (bir_pba != bir_table) {
|
2016-10-24 07:52:06 +03:00
|
|
|
dev->msix_pba_bar = qpci_iomap(dev, bir_pba, NULL);
|
2017-08-29 20:03:51 +03:00
|
|
|
} else {
|
|
|
|
dev->msix_pba_bar = dev->msix_table_bar;
|
2014-09-01 14:07:59 +04:00
|
|
|
}
|
2016-10-24 07:52:06 +03:00
|
|
|
dev->msix_pba_off = table & ~PCI_MSIX_FLAGS_BIRMASK;
|
2014-09-01 14:07:59 +04:00
|
|
|
|
|
|
|
dev->msix_enabled = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
void qpci_msix_disable(QPCIDevice *dev)
|
|
|
|
{
|
|
|
|
uint8_t addr;
|
|
|
|
uint16_t val;
|
|
|
|
|
|
|
|
g_assert(dev->msix_enabled);
|
2019-10-23 13:04:19 +03:00
|
|
|
addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX, 0);
|
2014-09-01 14:07:59 +04:00
|
|
|
g_assert_cmphex(addr, !=, 0);
|
|
|
|
val = qpci_config_readw(dev, addr + PCI_MSIX_FLAGS);
|
|
|
|
qpci_config_writew(dev, addr + PCI_MSIX_FLAGS,
|
|
|
|
val & ~PCI_MSIX_FLAGS_ENABLE);
|
|
|
|
|
2017-08-29 20:03:51 +03:00
|
|
|
if (dev->msix_pba_bar.addr != dev->msix_table_bar.addr) {
|
|
|
|
qpci_iounmap(dev, dev->msix_pba_bar);
|
|
|
|
}
|
2016-10-24 07:52:06 +03:00
|
|
|
qpci_iounmap(dev, dev->msix_table_bar);
|
2017-08-29 20:03:51 +03:00
|
|
|
|
2014-09-01 14:07:59 +04:00
|
|
|
dev->msix_enabled = 0;
|
2016-10-24 07:52:06 +03:00
|
|
|
dev->msix_table_off = 0;
|
|
|
|
dev->msix_pba_off = 0;
|
2014-09-01 14:07:59 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
bool qpci_msix_pending(QPCIDevice *dev, uint16_t entry)
|
|
|
|
{
|
|
|
|
uint32_t pba_entry;
|
|
|
|
uint8_t bit_n = entry % 32;
|
2016-10-24 07:52:06 +03:00
|
|
|
uint64_t off = (entry / 32) * PCI_MSIX_ENTRY_SIZE / 4;
|
2014-09-01 14:07:59 +04:00
|
|
|
|
|
|
|
g_assert(dev->msix_enabled);
|
2016-10-24 07:52:06 +03:00
|
|
|
pba_entry = qpci_io_readl(dev, dev->msix_pba_bar, dev->msix_pba_off + off);
|
|
|
|
qpci_io_writel(dev, dev->msix_pba_bar, dev->msix_pba_off + off,
|
|
|
|
pba_entry & ~(1 << bit_n));
|
2014-09-01 14:07:59 +04:00
|
|
|
return (pba_entry & (1 << bit_n)) != 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool qpci_msix_masked(QPCIDevice *dev, uint16_t entry)
|
|
|
|
{
|
|
|
|
uint8_t addr;
|
|
|
|
uint16_t val;
|
2016-10-24 07:52:06 +03:00
|
|
|
uint64_t vector_off = dev->msix_table_off + entry * PCI_MSIX_ENTRY_SIZE;
|
2014-09-01 14:07:59 +04:00
|
|
|
|
|
|
|
g_assert(dev->msix_enabled);
|
2019-10-23 13:04:19 +03:00
|
|
|
addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX, 0);
|
2014-09-01 14:07:59 +04:00
|
|
|
g_assert_cmphex(addr, !=, 0);
|
|
|
|
val = qpci_config_readw(dev, addr + PCI_MSIX_FLAGS);
|
|
|
|
|
|
|
|
if (val & PCI_MSIX_FLAGS_MASKALL) {
|
|
|
|
return true;
|
|
|
|
} else {
|
2016-10-24 07:52:06 +03:00
|
|
|
return (qpci_io_readl(dev, dev->msix_table_bar,
|
|
|
|
vector_off + PCI_MSIX_ENTRY_VECTOR_CTRL)
|
|
|
|
& PCI_MSIX_ENTRY_CTRL_MASKBIT) != 0;
|
2014-09-01 14:07:59 +04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
uint16_t qpci_msix_table_size(QPCIDevice *dev)
|
|
|
|
{
|
|
|
|
uint8_t addr;
|
|
|
|
uint16_t control;
|
|
|
|
|
2019-10-23 13:04:19 +03:00
|
|
|
addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX, 0);
|
2014-09-01 14:07:59 +04:00
|
|
|
g_assert_cmphex(addr, !=, 0);
|
|
|
|
|
|
|
|
control = qpci_config_readw(dev, addr + PCI_MSIX_FLAGS);
|
|
|
|
return (control & PCI_MSIX_FLAGS_QSIZE) + 1;
|
|
|
|
}
|
|
|
|
|
2013-04-16 18:45:16 +04:00
|
|
|
uint8_t qpci_config_readb(QPCIDevice *dev, uint8_t offset)
|
|
|
|
{
|
|
|
|
return dev->bus->config_readb(dev->bus, dev->devfn, offset);
|
|
|
|
}
|
|
|
|
|
|
|
|
uint16_t qpci_config_readw(QPCIDevice *dev, uint8_t offset)
|
|
|
|
{
|
|
|
|
return dev->bus->config_readw(dev->bus, dev->devfn, offset);
|
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t qpci_config_readl(QPCIDevice *dev, uint8_t offset)
|
|
|
|
{
|
|
|
|
return dev->bus->config_readl(dev->bus, dev->devfn, offset);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void qpci_config_writeb(QPCIDevice *dev, uint8_t offset, uint8_t value)
|
|
|
|
{
|
|
|
|
dev->bus->config_writeb(dev->bus, dev->devfn, offset, value);
|
|
|
|
}
|
|
|
|
|
|
|
|
void qpci_config_writew(QPCIDevice *dev, uint8_t offset, uint16_t value)
|
|
|
|
{
|
|
|
|
dev->bus->config_writew(dev->bus, dev->devfn, offset, value);
|
|
|
|
}
|
|
|
|
|
|
|
|
void qpci_config_writel(QPCIDevice *dev, uint8_t offset, uint32_t value)
|
|
|
|
{
|
2014-05-08 12:54:33 +04:00
|
|
|
dev->bus->config_writel(dev->bus, dev->devfn, offset, value);
|
2013-04-16 18:45:16 +04:00
|
|
|
}
|
|
|
|
|
2016-10-24 07:52:06 +03:00
|
|
|
uint8_t qpci_io_readb(QPCIDevice *dev, QPCIBar token, uint64_t off)
|
2013-04-16 18:45:16 +04:00
|
|
|
{
|
2016-10-24 07:52:06 +03:00
|
|
|
if (token.addr < QPCI_PIO_LIMIT) {
|
|
|
|
return dev->bus->pio_readb(dev->bus, token.addr + off);
|
2016-10-18 09:02:49 +03:00
|
|
|
} else {
|
2016-10-19 06:20:44 +03:00
|
|
|
uint8_t val;
|
2016-10-24 07:52:06 +03:00
|
|
|
dev->bus->memread(dev->bus, token.addr + off, &val, sizeof(val));
|
2016-10-19 06:20:44 +03:00
|
|
|
return val;
|
2016-10-18 09:02:49 +03:00
|
|
|
}
|
2013-04-16 18:45:16 +04:00
|
|
|
}
|
|
|
|
|
2016-10-24 07:52:06 +03:00
|
|
|
uint16_t qpci_io_readw(QPCIDevice *dev, QPCIBar token, uint64_t off)
|
2013-04-16 18:45:16 +04:00
|
|
|
{
|
2016-10-24 07:52:06 +03:00
|
|
|
if (token.addr < QPCI_PIO_LIMIT) {
|
|
|
|
return dev->bus->pio_readw(dev->bus, token.addr + off);
|
2016-10-18 09:02:49 +03:00
|
|
|
} else {
|
2016-10-19 06:20:44 +03:00
|
|
|
uint16_t val;
|
2016-10-24 07:52:06 +03:00
|
|
|
dev->bus->memread(dev->bus, token.addr + off, &val, sizeof(val));
|
2016-10-19 06:20:44 +03:00
|
|
|
return le16_to_cpu(val);
|
2016-10-18 09:02:49 +03:00
|
|
|
}
|
2013-04-16 18:45:16 +04:00
|
|
|
}
|
|
|
|
|
2016-10-24 07:52:06 +03:00
|
|
|
uint32_t qpci_io_readl(QPCIDevice *dev, QPCIBar token, uint64_t off)
|
2013-04-16 18:45:16 +04:00
|
|
|
{
|
2016-10-24 07:52:06 +03:00
|
|
|
if (token.addr < QPCI_PIO_LIMIT) {
|
|
|
|
return dev->bus->pio_readl(dev->bus, token.addr + off);
|
2016-10-18 09:02:49 +03:00
|
|
|
} else {
|
2016-10-19 06:20:44 +03:00
|
|
|
uint32_t val;
|
2016-10-24 07:52:06 +03:00
|
|
|
dev->bus->memread(dev->bus, token.addr + off, &val, sizeof(val));
|
2016-10-19 06:20:44 +03:00
|
|
|
return le32_to_cpu(val);
|
2016-10-18 09:02:49 +03:00
|
|
|
}
|
|
|
|
}
|
2013-04-16 18:45:16 +04:00
|
|
|
|
2016-10-24 07:52:06 +03:00
|
|
|
uint64_t qpci_io_readq(QPCIDevice *dev, QPCIBar token, uint64_t off)
|
2016-10-19 07:00:21 +03:00
|
|
|
{
|
2016-10-24 07:52:06 +03:00
|
|
|
if (token.addr < QPCI_PIO_LIMIT) {
|
|
|
|
return dev->bus->pio_readq(dev->bus, token.addr + off);
|
2016-10-19 07:00:21 +03:00
|
|
|
} else {
|
|
|
|
uint64_t val;
|
2016-10-24 07:52:06 +03:00
|
|
|
dev->bus->memread(dev->bus, token.addr + off, &val, sizeof(val));
|
2016-10-19 07:00:21 +03:00
|
|
|
return le64_to_cpu(val);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-10-24 07:52:06 +03:00
|
|
|
void qpci_io_writeb(QPCIDevice *dev, QPCIBar token, uint64_t off,
|
|
|
|
uint8_t value)
|
2013-04-16 18:45:16 +04:00
|
|
|
{
|
2016-10-24 07:52:06 +03:00
|
|
|
if (token.addr < QPCI_PIO_LIMIT) {
|
|
|
|
dev->bus->pio_writeb(dev->bus, token.addr + off, value);
|
2016-10-18 09:02:49 +03:00
|
|
|
} else {
|
2016-10-24 07:52:06 +03:00
|
|
|
dev->bus->memwrite(dev->bus, token.addr + off, &value, sizeof(value));
|
2016-10-18 09:02:49 +03:00
|
|
|
}
|
2013-04-16 18:45:16 +04:00
|
|
|
}
|
|
|
|
|
2016-10-24 07:52:06 +03:00
|
|
|
void qpci_io_writew(QPCIDevice *dev, QPCIBar token, uint64_t off,
|
|
|
|
uint16_t value)
|
2013-04-16 18:45:16 +04:00
|
|
|
{
|
2016-10-24 07:52:06 +03:00
|
|
|
if (token.addr < QPCI_PIO_LIMIT) {
|
|
|
|
dev->bus->pio_writew(dev->bus, token.addr + off, value);
|
2016-10-18 09:02:49 +03:00
|
|
|
} else {
|
2016-10-19 06:20:44 +03:00
|
|
|
value = cpu_to_le16(value);
|
2016-10-24 07:52:06 +03:00
|
|
|
dev->bus->memwrite(dev->bus, token.addr + off, &value, sizeof(value));
|
2016-10-18 09:02:49 +03:00
|
|
|
}
|
2013-04-16 18:45:16 +04:00
|
|
|
}
|
|
|
|
|
2016-10-24 07:52:06 +03:00
|
|
|
void qpci_io_writel(QPCIDevice *dev, QPCIBar token, uint64_t off,
|
|
|
|
uint32_t value)
|
2013-04-16 18:45:16 +04:00
|
|
|
{
|
2016-10-24 07:52:06 +03:00
|
|
|
if (token.addr < QPCI_PIO_LIMIT) {
|
|
|
|
dev->bus->pio_writel(dev->bus, token.addr + off, value);
|
2016-10-18 09:02:49 +03:00
|
|
|
} else {
|
2016-10-19 06:20:44 +03:00
|
|
|
value = cpu_to_le32(value);
|
2016-10-24 07:52:06 +03:00
|
|
|
dev->bus->memwrite(dev->bus, token.addr + off, &value, sizeof(value));
|
2016-10-18 09:02:49 +03:00
|
|
|
}
|
2013-04-16 18:45:16 +04:00
|
|
|
}
|
|
|
|
|
2016-10-24 07:52:06 +03:00
|
|
|
void qpci_io_writeq(QPCIDevice *dev, QPCIBar token, uint64_t off,
|
|
|
|
uint64_t value)
|
2016-10-19 07:00:21 +03:00
|
|
|
{
|
2016-10-24 07:52:06 +03:00
|
|
|
if (token.addr < QPCI_PIO_LIMIT) {
|
|
|
|
dev->bus->pio_writeq(dev->bus, token.addr + off, value);
|
2016-10-19 07:00:21 +03:00
|
|
|
} else {
|
|
|
|
value = cpu_to_le64(value);
|
2016-10-24 07:52:06 +03:00
|
|
|
dev->bus->memwrite(dev->bus, token.addr + off, &value, sizeof(value));
|
2016-10-19 07:00:21 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-10-24 07:52:06 +03:00
|
|
|
void qpci_memread(QPCIDevice *dev, QPCIBar token, uint64_t off,
|
|
|
|
void *buf, size_t len)
|
2016-10-19 06:19:47 +03:00
|
|
|
{
|
2016-10-24 07:52:06 +03:00
|
|
|
g_assert(token.addr >= QPCI_PIO_LIMIT);
|
|
|
|
dev->bus->memread(dev->bus, token.addr + off, buf, len);
|
2016-10-19 06:19:47 +03:00
|
|
|
}
|
|
|
|
|
2016-10-24 07:52:06 +03:00
|
|
|
void qpci_memwrite(QPCIDevice *dev, QPCIBar token, uint64_t off,
|
|
|
|
const void *buf, size_t len)
|
2016-10-19 06:19:47 +03:00
|
|
|
{
|
2016-10-24 07:52:06 +03:00
|
|
|
g_assert(token.addr >= QPCI_PIO_LIMIT);
|
|
|
|
dev->bus->memwrite(dev->bus, token.addr + off, buf, len);
|
2016-10-19 06:19:47 +03:00
|
|
|
}
|
|
|
|
|
2016-10-24 07:52:06 +03:00
|
|
|
QPCIBar qpci_iomap(QPCIDevice *dev, int barno, uint64_t *sizeptr)
|
2013-04-16 18:45:16 +04:00
|
|
|
{
|
2016-10-19 06:06:51 +03:00
|
|
|
QPCIBus *bus = dev->bus;
|
|
|
|
static const int bar_reg_map[] = {
|
|
|
|
PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_2,
|
|
|
|
PCI_BASE_ADDRESS_3, PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_5,
|
|
|
|
};
|
2016-10-24 07:52:06 +03:00
|
|
|
QPCIBar bar;
|
2016-10-19 06:06:51 +03:00
|
|
|
int bar_reg;
|
|
|
|
uint32_t addr, size;
|
|
|
|
uint32_t io_type;
|
|
|
|
uint64_t loc;
|
|
|
|
|
|
|
|
g_assert(barno >= 0 && barno <= 5);
|
|
|
|
bar_reg = bar_reg_map[barno];
|
|
|
|
|
|
|
|
qpci_config_writel(dev, bar_reg, 0xFFFFFFFF);
|
|
|
|
addr = qpci_config_readl(dev, bar_reg);
|
|
|
|
|
|
|
|
io_type = addr & PCI_BASE_ADDRESS_SPACE;
|
|
|
|
if (io_type == PCI_BASE_ADDRESS_SPACE_IO) {
|
|
|
|
addr &= PCI_BASE_ADDRESS_IO_MASK;
|
|
|
|
} else {
|
|
|
|
addr &= PCI_BASE_ADDRESS_MEM_MASK;
|
|
|
|
}
|
|
|
|
|
|
|
|
g_assert(addr); /* Must have *some* size bits */
|
|
|
|
|
|
|
|
size = 1U << ctz32(addr);
|
|
|
|
if (sizeptr) {
|
|
|
|
*sizeptr = size;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (io_type == PCI_BASE_ADDRESS_SPACE_IO) {
|
|
|
|
loc = QEMU_ALIGN_UP(bus->pio_alloc_ptr, size);
|
|
|
|
|
|
|
|
g_assert(loc >= bus->pio_alloc_ptr);
|
|
|
|
g_assert(loc + size <= QPCI_PIO_LIMIT); /* Keep PIO below 64kiB */
|
|
|
|
|
|
|
|
bus->pio_alloc_ptr = loc + size;
|
|
|
|
|
|
|
|
qpci_config_writel(dev, bar_reg, loc | PCI_BASE_ADDRESS_SPACE_IO);
|
|
|
|
} else {
|
|
|
|
loc = QEMU_ALIGN_UP(bus->mmio_alloc_ptr, size);
|
|
|
|
|
|
|
|
/* Check for space */
|
|
|
|
g_assert(loc >= bus->mmio_alloc_ptr);
|
|
|
|
g_assert(loc + size <= bus->mmio_limit);
|
|
|
|
|
|
|
|
bus->mmio_alloc_ptr = loc + size;
|
|
|
|
|
|
|
|
qpci_config_writel(dev, bar_reg, loc);
|
|
|
|
}
|
|
|
|
|
2016-10-24 07:52:06 +03:00
|
|
|
bar.addr = loc;
|
|
|
|
return bar;
|
2013-04-16 18:45:16 +04:00
|
|
|
}
|
|
|
|
|
2016-10-24 07:52:06 +03:00
|
|
|
void qpci_iounmap(QPCIDevice *dev, QPCIBar bar)
|
2013-04-16 18:45:16 +04:00
|
|
|
{
|
2016-10-19 06:06:51 +03:00
|
|
|
/* FIXME */
|
2013-04-16 18:45:16 +04:00
|
|
|
}
|
|
|
|
|
2016-10-24 07:52:06 +03:00
|
|
|
QPCIBar qpci_legacy_iomap(QPCIDevice *dev, uint16_t addr)
|
libqos: Better handling of PCI legacy IO
The usual model for PCI IO with libqos is to use qpci_iomap() to map a
specific BAR for a PCI device, then perform IOs within that BAR using
qpci_io_{read,write}*().
However, certain devices also have legacy PCI IO. In this case, instead of
(or as well as) being accessed via PCI BARs, the device can be accessed
via certain well-known, fixed addresses in PCI IO space.
Two existing tests use legacy PCI IO, and take different flawed approaches
to it:
* tco-test manually constructs a tco_io_base value instead of calling
qpci_iomap(), which assumes internal knowledge of the structure of
the value it shouldn't have
* ide-test uses direct in*() and out*() calls instead of using
qpci_io_*() accessors, meaning it's not portable to non-x86 machine
types.
This patch implements a new qpci_iomap_legacy() interface which gets a
handle in the same format as qpci_iomap() but refers to a region in
the legacy PIO space. For a device which has the same registers
available both in a BAR and in legacy space (quite common), this
allows the same test code to test both options with just a different
iomap() at the beginning.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Laurent Vivier <lvivier@redhat.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
2016-10-19 09:43:42 +03:00
|
|
|
{
|
2016-10-24 07:52:06 +03:00
|
|
|
QPCIBar bar = { .addr = addr };
|
|
|
|
return bar;
|
libqos: Better handling of PCI legacy IO
The usual model for PCI IO with libqos is to use qpci_iomap() to map a
specific BAR for a PCI device, then perform IOs within that BAR using
qpci_io_{read,write}*().
However, certain devices also have legacy PCI IO. In this case, instead of
(or as well as) being accessed via PCI BARs, the device can be accessed
via certain well-known, fixed addresses in PCI IO space.
Two existing tests use legacy PCI IO, and take different flawed approaches
to it:
* tco-test manually constructs a tco_io_base value instead of calling
qpci_iomap(), which assumes internal knowledge of the structure of
the value it shouldn't have
* ide-test uses direct in*() and out*() calls instead of using
qpci_io_*() accessors, meaning it's not portable to non-x86 machine
types.
This patch implements a new qpci_iomap_legacy() interface which gets a
handle in the same format as qpci_iomap() but refers to a region in
the legacy PIO space. For a device which has the same registers
available both in a BAR and in legacy space (quite common), this
allows the same test code to test both options with just a different
iomap() at the beginning.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Laurent Vivier <lvivier@redhat.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
2016-10-19 09:43:42 +03:00
|
|
|
}
|
2018-07-03 17:53:10 +03:00
|
|
|
|
|
|
|
void add_qpci_address(QOSGraphEdgeOptions *opts, QPCIAddress *addr)
|
|
|
|
{
|
|
|
|
g_assert(addr);
|
|
|
|
g_assert(opts);
|
|
|
|
|
|
|
|
opts->arg = addr;
|
|
|
|
opts->size_arg = sizeof(QPCIAddress);
|
|
|
|
}
|