2003-11-23 17:55:54 +03:00
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/*
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* PPC emulation cpu definitions for qemu.
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*
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* Copyright (c) 2003 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#if !defined (__CPU_PPC_H__)
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#define __CPU_PPC_H__
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#include <endian.h>
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#include <asm/byteorder.h>
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#include "cpu-defs.h"
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/*** Sign extend constants ***/
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/* 8 to 32 bits */
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static inline int32_t s_ext8 (uint8_t value)
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{
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int8_t *tmp = &value;
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return *tmp;
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}
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/* 16 to 32 bits */
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static inline int32_t s_ext16 (uint16_t value)
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{
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int16_t *tmp = &value;
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return *tmp;
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}
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/* 24 to 32 bits */
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static inline int32_t s_ext24 (uint32_t value)
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{
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uint16_t utmp = (value >> 8) & 0xFFFF;
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int16_t *tmp = &utmp;
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return (*tmp << 8) | (value & 0xFF);
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}
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#include "config.h"
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#include <setjmp.h>
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/* Floting point status and control register */
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#define FPSCR_FX 31
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#define FPSCR_FEX 30
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#define FPSCR_VX 29
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#define FPSCR_OX 28
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#define FPSCR_UX 27
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#define FPSCR_ZX 26
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#define FPSCR_XX 25
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#define FPSCR_VXSNAN 24
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#define FPSCR_VXISI 26
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#define FPSCR_VXIDI 25
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#define FPSCR_VXZDZ 21
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#define FPSCR_VXIMZ 20
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#define FPSCR_VXVC 18
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#define FPSCR_FR 17
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#define FPSCR_FI 16
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#define FPSCR_FPRF 11
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#define FPSCR_VXSOFT 9
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#define FPSCR_VXSQRT 8
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#define FPSCR_VXCVI 7
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#define FPSCR_OE 6
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#define FPSCR_UE 5
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#define FPSCR_ZE 4
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#define FPSCR_XE 3
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#define FPSCR_NI 2
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#define FPSCR_RN 0
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#define fpscr_fx env->fpscr[FPSCR_FX]
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#define fpscr_fex env->fpscr[FPSCR_FEX]
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#define fpscr_vx env->fpscr[FPSCR_VX]
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#define fpscr_ox env->fpscr[FPSCR_OX]
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#define fpscr_ux env->fpscr[FPSCR_UX]
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#define fpscr_zx env->fpscr[FPSCR_ZX]
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#define fpscr_xx env->fpscr[FPSCR_XX]
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#define fpscr_vsxnan env->fpscr[FPSCR_VXSNAN]
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#define fpscr_vxisi env->fpscr[FPSCR_VXISI]
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#define fpscr_vxidi env->fpscr[FPSCR_VXIDI]
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#define fpscr_vxzdz env->fpscr[FPSCR_VXZDZ]
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#define fpscr_vximz env->fpscr[FPSCR_VXIMZ]
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#define fpscr_fr env->fpscr[FPSCR_FR]
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#define fpscr_fi env->fpscr[FPSCR_FI]
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#define fpscr_fprf env->fpscr[FPSCR_FPRF]
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#define fpscr_vxsoft env->fpscr[FPSCR_VXSOFT]
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#define fpscr_vxsqrt env->fpscr[FPSCR_VXSQRT]
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#define fpscr_oe env->fpscr[FPSCR_OE]
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#define fpscr_ue env->fpscr[FPSCR_UE]
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#define fpscr_ze env->fpscr[FPSCR_ZE]
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#define fpscr_xe env->fpscr[FPSCR_XE]
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#define fpscr_ni env->fpscr[FPSCR_NI]
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#define fpscr_rn env->fpscr[FPSCR_RN]
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/* Supervisor mode registers */
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/* Machine state register */
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#define MSR_POW 18
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#define MSR_ILE 16
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#define MSR_EE 15
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#define MSR_PR 14
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#define MSR_FP 13
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#define MSR_ME 12
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#define MSR_FE0 11
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#define MSR_SE 10
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#define MSR_BE 9
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#define MSR_FE1 8
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#define MSR_IP 6
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#define MSR_IR 5
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#define MSR_DR 4
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#define MSR_RI 1
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#define MSR_LE 0
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#define msr_pow env->msr[MSR_POW]
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#define msr_ile env->msr[MSR_ILE]
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#define msr_ee env->msr[MSR_EE]
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#define msr_pr env->msr[MSR_PR]
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#define msr_fp env->msr[MSR_FP]
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#define msr_me env->msr[MSR_ME]
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#define msr_fe0 env->msr[MSR_FE0]
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#define msr_se env->msr[MSR_SE]
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#define msr_be env->msr[MSR_BE]
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#define msr_fe1 env->msr[MSR_FE1]
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#define msr_ip env->msr[MSR_IP]
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#define msr_ir env->msr[MSR_IR]
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#define msr_dr env->msr[MSR_DR]
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#define msr_ri env->msr[MSR_RI]
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#define msr_le env->msr[MSR_LE]
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/* Segment registers */
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typedef struct ppc_sr_t {
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uint32_t t:1;
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uint32_t ks:1;
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uint32_t kp:1;
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uint32_t n:1;
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uint32_t res:4;
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uint32_t vsid:24;
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} ppc_sr_t;
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typedef struct CPUPPCState {
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/* general purpose registers */
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uint32_t gpr[32];
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/* floating point registers */
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2004-01-04 17:57:11 +03:00
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double fpr[32];
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2003-11-23 17:55:54 +03:00
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/* segment registers */
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ppc_sr_t sr[16];
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/* special purpose registers */
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uint32_t spr[1024];
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/* XER */
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uint8_t xer[32];
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/* Reservation address */
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uint32_t reserve;
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/* machine state register */
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uint8_t msr[32];
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/* condition register */
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uint8_t crf[8];
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/* floating point status and control register */
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uint8_t fpscr[32];
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uint32_t nip;
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/* CPU exception code */
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uint32_t exception;
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/* qemu dedicated */
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2004-01-04 17:57:11 +03:00
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/* temporary float registers */
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double ft0;
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double ft1;
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double ft2;
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2003-11-23 17:55:54 +03:00
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int interrupt_request;
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jmp_buf jmp_env;
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int exception_index;
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int error_code;
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int user_mode_only; /* user mode only simulation */
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struct TranslationBlock *current_tb; /* currently executing TB */
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/* user data */
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void *opaque;
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} CPUPPCState;
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CPUPPCState *cpu_ppc_init(void);
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int cpu_ppc_exec(CPUPPCState *s);
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void cpu_ppc_close(CPUPPCState *s);
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/* you can call this signal handler from your SIGBUS and SIGSEGV
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signal handlers to inform the virtual CPU of exceptions. non zero
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is returned if the signal was handled by the virtual CPU. */
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struct siginfo;
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int cpu_ppc_signal_handler(int host_signum, struct siginfo *info,
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void *puc);
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void cpu_ppc_dump_state(CPUPPCState *env, FILE *f, int flags);
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#define TARGET_PAGE_BITS 12
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#include "cpu-all.h"
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#define ugpr(n) (env->gpr[n])
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#define fpr(n) (env->fpr[n])
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#define SPR_ENCODE(sprn) \
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(((sprn) >> 5) | (((sprn) & 0x1F) << 5))
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/* User mode SPR */
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#define spr(n) env->spr[n]
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//#define XER spr[1]
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#define XER env->xer
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#define XER_SO 31
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#define XER_OV 30
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#define XER_CA 29
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#define XER_BC 0
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#define xer_so env->xer[XER_SO]
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#define xer_ov env->xer[XER_OV]
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#define xer_ca env->xer[XER_CA]
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#define xer_bc env->xer[XER_BC]
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#define LR spr[SPR_ENCODE(8)]
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#define CTR spr[SPR_ENCODE(9)]
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/* VEA mode SPR */
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#define V_TBL spr[SPR_ENCODE(268)]
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#define V_TBU spr[SPR_ENCODE(269)]
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/* supervisor mode SPR */
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#define DSISR spr[SPR_ENCODE(18)]
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#define DAR spr[SPR_ENCODE(19)]
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#define DEC spr[SPR_ENCODE(22)]
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#define SDR1 spr[SPR_ENCODE(25)]
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typedef struct ppc_sdr1_t {
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uint32_t htaborg:16;
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uint32_t res:7;
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uint32_t htabmask:9;
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} ppc_sdr1_t;
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#define SRR0 spr[SPR_ENCODE(26)]
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#define SRR0_MASK 0xFFFFFFFC
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#define SRR1 spr[SPR_ENCODE(27)]
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#define SPRG0 spr[SPR_ENCODE(272)]
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#define SPRG1 spr[SPR_ENCODE(273)]
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#define SPRG2 spr[SPR_ENCODE(274)]
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#define SPRG3 spr[SPR_ENCODE(275)]
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#define EAR spr[SPR_ENCODE(282)]
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typedef struct ppc_ear_t {
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uint32_t e:1;
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uint32_t res:25;
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uint32_t rid:6;
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} ppc_ear_t;
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#define TBL spr[SPR_ENCODE(284)]
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#define TBU spr[SPR_ENCODE(285)]
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#define PVR spr[SPR_ENCODE(287)]
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typedef struct ppc_pvr_t {
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uint32_t version:16;
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uint32_t revision:16;
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} ppc_pvr_t;
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#define IBAT0U spr[SPR_ENCODE(528)]
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#define IBAT0L spr[SPR_ENCODE(529)]
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#define IBAT1U spr[SPR_ENCODE(530)]
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#define IBAT1L spr[SPR_ENCODE(531)]
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#define IBAT2U spr[SPR_ENCODE(532)]
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#define IBAT2L spr[SPR_ENCODE(533)]
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#define IBAT3U spr[SPR_ENCODE(534)]
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#define IBAT3L spr[SPR_ENCODE(535)]
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#define DBAT0U spr[SPR_ENCODE(536)]
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#define DBAT0L spr[SPR_ENCODE(537)]
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#define DBAT1U spr[SPR_ENCODE(538)]
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#define DBAT1L spr[SPR_ENCODE(539)]
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#define DBAT2U spr[SPR_ENCODE(540)]
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#define DBAT2L spr[SPR_ENCODE(541)]
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#define DBAT3U spr[SPR_ENCODE(542)]
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#define DBAT3L spr[SPR_ENCODE(543)]
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typedef struct ppc_ubat_t {
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uint32_t bepi:15;
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uint32_t res:4;
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uint32_t bl:11;
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uint32_t vs:1;
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uint32_t vp:1;
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} ppc_ubat_t;
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typedef struct ppc_lbat_t {
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uint32_t brpn:15;
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uint32_t res0:10;
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uint32_t w:1;
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uint32_t i:1;
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uint32_t m:1;
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uint32_t g:1;
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uint32_t res1:1;
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uint32_t pp:2;
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} ppc_lbat_t;
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#define DABR spr[SPR_ENCODE(1013)]
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#define DABR_MASK 0xFFFFFFF8
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typedef struct ppc_dabr_t {
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uint32_t dab:29;
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uint32_t bt:1;
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uint32_t dw:1;
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uint32_t dr:1;
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} ppc_dabr_t;
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#define FPECR spr[SPR_ENCODE(1022)]
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#define PIR spr[SPR_ENCODE(1023)]
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#define TARGET_PAGE_BITS 12
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#include "cpu-all.h"
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CPUPPCState *cpu_ppc_init(void);
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int cpu_ppc_exec(CPUPPCState *s);
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void cpu_ppc_close(CPUPPCState *s);
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void cpu_ppc_dump_state(CPUPPCState *env, FILE *f, int flags);
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/* Exeptions */
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enum {
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EXCP_NONE = 0x00,
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/* PPC hardware exceptions : exception vector / 0x100 */
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EXCP_RESET = 0x01, /* System reset */
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EXCP_MACHINE_CHECK = 0x02, /* Machine check exception */
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EXCP_DSI = 0x03, /* Impossible memory access */
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EXCP_ISI = 0x04, /* Impossible instruction fetch */
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EXCP_EXTERNAL = 0x05, /* External interruption */
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EXCP_ALIGN = 0x06, /* Alignment exception */
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EXCP_PROGRAM = 0x07, /* Program exception */
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EXCP_NO_FP = 0x08, /* No floating point */
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EXCP_DECR = 0x09, /* Decrementer exception */
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EXCP_RESA = 0x0A, /* Implementation specific */
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EXCP_RESB = 0x0B, /* Implementation specific */
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EXCP_SYSCALL = 0x0C, /* System call */
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EXCP_TRACE = 0x0D, /* Trace exception (optional) */
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EXCP_FP_ASSIST = 0x0E, /* Floating-point assist (optional) */
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#if 0
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/* Exeption subtypes for EXCP_DSI */
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EXCP_DSI_TRANSLATE = 0x10301, /* Data address can't be translated */
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EXCP_DSI_NOTSUP = 0x10302, /* Access type not supported */
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EXCP_DSI_PROT = 0x10303, /* Memory protection violation */
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EXCP_DSI_EXTERNAL = 0x10304, /* External access disabled */
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EXCP_DSI_DABR = 0x10305, /* Data address breakpoint */
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/* Exeption subtypes for EXCP_ISI */
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EXCP_ISI_TRANSLATE = 0x10401, /* Code address can't be translated */
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EXCP_ISI_NOTSUP = 0x10402, /* Access type not supported */
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EXCP_ISI_PROT = 0x10403, /* Memory protection violation */
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EXCP_ISI_GUARD = 0x10404, /* Fetch into guarded memory */
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/* Exeption subtypes for EXCP_ALIGN */
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EXCP_ALIGN_FP = 0x10601, /* FP alignment exception */
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EXCP_ALIGN_LST = 0x10602, /* Unaligned memory load/store */
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EXCP_ALIGN_LE = 0x10603, /* Unaligned little-endian access */
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EXCP_ALIGN_PROT = 0x10604, /* Access cross protection boundary */
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EXCP_ALIGN_BAT = 0x10605, /* Access cross a BAT/seg boundary */
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EXCP_ALIGN_CACHE = 0x10606, /* Impossible dcbz access */
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/* Exeption subtypes for EXCP_PROGRAM */
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/* FP exceptions */
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EXCP_FP_OX = 0x10701, /* FP overflow */
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EXCP_FP_UX = 0x10702, /* FP underflow */
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EXCP_FP_ZX = 0x10703, /* FP divide by zero */
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EXCP_FP_XX = 0x10704, /* FP inexact */
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EXCP_FP_VXNAN = 0x10705, /* FP invalid SNaN op */
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EXCP_FP_VXISI = 0x10706, /* FP invalid infinite substraction */
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EXCP_FP_VXIDI = 0x10707, /* FP invalid infinite divide */
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EXCP_FP_VXZDZ = 0x10708, /* FP invalid zero divide */
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EXCP_FP_VXIMZ = 0x10709, /* FP invalid infinite * zero */
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EXCP_FP_VXVC = 0x1070A, /* FP invalid compare */
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EXCP_FP_VXSOFT = 0x1070B, /* FP invalid operation */
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EXCP_FP_VXSQRT = 0x1070C, /* FP invalid square root */
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EXCP_FP_VXCVI = 0x1070D, /* FP invalid integer conversion */
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/* Invalid instruction */
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EXCP_INVAL_INVAL = 0x10711, /* Invalid instruction */
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EXCP_INVAL_LSWX = 0x10712, /* Invalid lswx instruction */
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EXCP_INVAL_SPR = 0x10713, /* Invalid SPR access */
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EXCP_INVAL_FP = 0x10714, /* Unimplemented mandatory fp instr */
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#endif
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EXCP_INVAL = 0x70, /* Invalid instruction */
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/* Privileged instruction */
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EXCP_PRIV = 0x71, /* Privileged instruction */
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/* Trap */
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EXCP_TRAP = 0x72, /* Trap */
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/* Special cases where we want to stop translation */
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EXCP_MTMSR = 0x103, /* mtmsr instruction: */
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/* may change privilege level */
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EXCP_BRANCH = 0x104, /* branch instruction */
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};
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#endif /* !defined (__CPU_PPC_H__) */
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