2012-10-17 11:54:20 +04:00
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/*
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* QEMU 16550A UART emulation
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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* Copyright (c) 2008 Citrix Systems, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2012-10-17 11:54:23 +04:00
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/* see docs/specs/pci-serial.txt */
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2013-02-05 20:06:20 +04:00
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#include "hw/char/serial.h"
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2013-02-04 18:40:22 +04:00
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#include "hw/pci/pci.h"
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2012-11-25 05:37:14 +04:00
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#include "qapi/qmp/qerror.h"
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2012-10-17 11:54:20 +04:00
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2012-10-17 11:54:22 +04:00
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#define PCI_SERIAL_MAX_PORTS 4
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2012-10-17 11:54:20 +04:00
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typedef struct PCISerialState {
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PCIDevice dev;
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SerialState state;
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} PCISerialState;
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2012-10-17 11:54:22 +04:00
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typedef struct PCIMultiSerialState {
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PCIDevice dev;
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MemoryRegion iobar;
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uint32_t ports;
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char *name[PCI_SERIAL_MAX_PORTS];
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SerialState state[PCI_SERIAL_MAX_PORTS];
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uint32_t level[PCI_SERIAL_MAX_PORTS];
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qemu_irq *irqs;
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} PCIMultiSerialState;
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2012-10-17 11:54:20 +04:00
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static int serial_pci_init(PCIDevice *dev)
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{
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PCISerialState *pci = DO_UPCAST(PCISerialState, dev, dev);
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SerialState *s = &pci->state;
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2012-11-25 05:37:14 +04:00
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Error *err = NULL;
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2012-10-17 11:54:20 +04:00
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s->baudbase = 115200;
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2012-11-25 05:37:14 +04:00
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serial_realize_core(s, &err);
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if (err != NULL) {
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qerror_report_err(err);
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error_free(err);
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return -1;
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}
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2012-10-17 11:54:20 +04:00
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pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
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s->irq = pci->dev.irq[0];
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2013-06-07 05:25:08 +04:00
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memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s, "serial", 8);
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2012-10-17 11:54:20 +04:00
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pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
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return 0;
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}
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2012-10-17 11:54:22 +04:00
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static void multi_serial_irq_mux(void *opaque, int n, int level)
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{
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PCIMultiSerialState *pci = opaque;
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int i, pending = 0;
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pci->level[n] = level;
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for (i = 0; i < pci->ports; i++) {
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if (pci->level[i]) {
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pending = 1;
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}
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}
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qemu_set_irq(pci->dev.irq[0], pending);
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}
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static int multi_serial_pci_init(PCIDevice *dev)
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{
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PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
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PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev);
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SerialState *s;
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2012-11-25 05:37:14 +04:00
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Error *err = NULL;
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2012-10-17 11:54:22 +04:00
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int i;
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switch (pc->device_id) {
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case 0x0003:
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pci->ports = 2;
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break;
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case 0x0004:
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pci->ports = 4;
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break;
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}
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assert(pci->ports > 0);
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assert(pci->ports <= PCI_SERIAL_MAX_PORTS);
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pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
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2013-06-07 05:25:08 +04:00
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memory_region_init(&pci->iobar, OBJECT(pci), "multiserial", 8 * pci->ports);
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2012-10-17 11:54:22 +04:00
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pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->iobar);
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pci->irqs = qemu_allocate_irqs(multi_serial_irq_mux, pci,
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pci->ports);
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for (i = 0; i < pci->ports; i++) {
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s = pci->state + i;
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s->baudbase = 115200;
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2012-11-25 05:37:14 +04:00
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serial_realize_core(s, &err);
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if (err != NULL) {
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qerror_report_err(err);
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error_free(err);
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return -1;
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}
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2012-10-17 11:54:22 +04:00
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s->irq = pci->irqs[i];
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pci->name[i] = g_strdup_printf("uart #%d", i+1);
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2013-06-07 05:25:08 +04:00
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memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s,
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pci->name[i], 8);
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2012-10-17 11:54:22 +04:00
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memory_region_add_subregion(&pci->iobar, 8 * i, &s->io);
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}
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return 0;
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}
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2012-10-17 11:54:20 +04:00
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static void serial_pci_exit(PCIDevice *dev)
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{
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PCISerialState *pci = DO_UPCAST(PCISerialState, dev, dev);
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SerialState *s = &pci->state;
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serial_exit_core(s);
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memory_region_destroy(&s->io);
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}
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2012-10-17 11:54:22 +04:00
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static void multi_serial_pci_exit(PCIDevice *dev)
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{
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PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev);
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SerialState *s;
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int i;
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for (i = 0; i < pci->ports; i++) {
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s = pci->state + i;
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serial_exit_core(s);
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memory_region_destroy(&s->io);
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g_free(pci->name[i]);
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}
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memory_region_destroy(&pci->iobar);
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qemu_free_irqs(pci->irqs);
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}
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2012-10-17 11:54:20 +04:00
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static const VMStateDescription vmstate_pci_serial = {
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.name = "pci-serial",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(dev, PCISerialState),
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VMSTATE_STRUCT(state, PCISerialState, 0, vmstate_serial, SerialState),
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VMSTATE_END_OF_LIST()
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}
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};
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2012-10-17 11:54:22 +04:00
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static const VMStateDescription vmstate_pci_multi_serial = {
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.name = "pci-serial-multi",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(dev, PCIMultiSerialState),
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VMSTATE_STRUCT_ARRAY(state, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS,
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0, vmstate_serial, SerialState),
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VMSTATE_UINT32_ARRAY(level, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS),
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VMSTATE_END_OF_LIST()
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}
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};
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2012-10-17 11:54:20 +04:00
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static Property serial_pci_properties[] = {
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DEFINE_PROP_CHR("chardev", PCISerialState, state.chr),
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DEFINE_PROP_END_OF_LIST(),
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};
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2012-10-17 11:54:22 +04:00
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static Property multi_2x_serial_pci_properties[] = {
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DEFINE_PROP_CHR("chardev1", PCIMultiSerialState, state[0].chr),
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DEFINE_PROP_CHR("chardev2", PCIMultiSerialState, state[1].chr),
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DEFINE_PROP_END_OF_LIST(),
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};
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static Property multi_4x_serial_pci_properties[] = {
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DEFINE_PROP_CHR("chardev1", PCIMultiSerialState, state[0].chr),
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DEFINE_PROP_CHR("chardev2", PCIMultiSerialState, state[1].chr),
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DEFINE_PROP_CHR("chardev3", PCIMultiSerialState, state[2].chr),
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DEFINE_PROP_CHR("chardev4", PCIMultiSerialState, state[3].chr),
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DEFINE_PROP_END_OF_LIST(),
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};
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2012-10-17 11:54:20 +04:00
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static void serial_pci_class_initfn(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
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pc->init = serial_pci_init;
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pc->exit = serial_pci_exit;
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2012-12-13 13:19:38 +04:00
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pc->vendor_id = PCI_VENDOR_ID_REDHAT;
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pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL;
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2012-10-17 11:54:20 +04:00
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pc->revision = 1;
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pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
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dc->vmsd = &vmstate_pci_serial;
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dc->props = serial_pci_properties;
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}
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2012-10-17 11:54:22 +04:00
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static void multi_2x_serial_pci_class_initfn(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
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pc->init = multi_serial_pci_init;
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pc->exit = multi_serial_pci_exit;
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2012-12-13 13:19:38 +04:00
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pc->vendor_id = PCI_VENDOR_ID_REDHAT;
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pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL2;
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2012-10-17 11:54:22 +04:00
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pc->revision = 1;
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pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
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dc->vmsd = &vmstate_pci_multi_serial;
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dc->props = multi_2x_serial_pci_properties;
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}
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static void multi_4x_serial_pci_class_initfn(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
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pc->init = multi_serial_pci_init;
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pc->exit = multi_serial_pci_exit;
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2012-12-13 13:19:38 +04:00
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pc->vendor_id = PCI_VENDOR_ID_REDHAT;
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pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL4;
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2012-10-17 11:54:22 +04:00
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pc->revision = 1;
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pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
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dc->vmsd = &vmstate_pci_multi_serial;
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dc->props = multi_4x_serial_pci_properties;
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}
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2013-01-10 19:19:07 +04:00
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static const TypeInfo serial_pci_info = {
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2012-10-17 11:54:20 +04:00
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.name = "pci-serial",
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PCISerialState),
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.class_init = serial_pci_class_initfn,
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};
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2013-01-10 19:19:07 +04:00
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static const TypeInfo multi_2x_serial_pci_info = {
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2012-10-17 11:54:22 +04:00
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.name = "pci-serial-2x",
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PCIMultiSerialState),
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.class_init = multi_2x_serial_pci_class_initfn,
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};
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2013-01-10 19:19:07 +04:00
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static const TypeInfo multi_4x_serial_pci_info = {
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2012-10-17 11:54:22 +04:00
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.name = "pci-serial-4x",
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PCIMultiSerialState),
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.class_init = multi_4x_serial_pci_class_initfn,
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};
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2012-10-17 11:54:20 +04:00
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static void serial_pci_register_types(void)
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{
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type_register_static(&serial_pci_info);
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2012-10-17 11:54:22 +04:00
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type_register_static(&multi_2x_serial_pci_info);
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type_register_static(&multi_4x_serial_pci_info);
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2012-10-17 11:54:20 +04:00
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}
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type_init(serial_pci_register_types)
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