2020-09-01 04:38:59 +03:00
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/*
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* QEMU RISC-V Board Compatible with Microchip PolarFire SoC Icicle Kit
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*
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* Copyright (c) 2020 Wind River Systems, Inc.
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*
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* Author:
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* Bin Meng <bin.meng@windriver.com>
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*
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* Provides a board compatible with the Microchip PolarFire SoC Icicle Kit
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*
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* 0) CLINT (Core Level Interruptor)
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* 1) PLIC (Platform Level Interrupt Controller)
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* 2) eNVM (Embedded Non-Volatile Memory)
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2020-09-01 04:39:01 +03:00
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* 3) MMUARTs (Multi-Mode UART)
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2020-09-01 04:39:03 +03:00
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* 4) Cadence eMMC/SDHC controller and an SD card connected to it
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2020-09-01 04:39:05 +03:00
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* 5) SiFive Platform DMA (Direct Memory Access Controller)
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2020-09-01 04:39:08 +03:00
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* 6) GEM (Gigabit Ethernet MAC Controller)
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2020-09-01 04:38:59 +03:00
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*
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* This board currently generates devicetree dynamically that indicates at least
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* two harts and up to five harts.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/error-report.h"
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#include "qemu/log.h"
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#include "qemu/units.h"
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#include "qemu/cutils.h"
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#include "qapi/error.h"
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#include "hw/boards.h"
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#include "hw/irq.h"
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#include "hw/loader.h"
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#include "hw/sysbus.h"
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2020-09-01 04:39:01 +03:00
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#include "chardev/char.h"
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2020-09-01 04:38:59 +03:00
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#include "hw/cpu/cluster.h"
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#include "target/riscv/cpu.h"
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#include "hw/misc/unimp.h"
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#include "hw/riscv/boot.h"
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#include "hw/riscv/riscv_hart.h"
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#include "hw/riscv/microchip_pfsoc.h"
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2020-09-03 13:40:16 +03:00
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#include "hw/intc/sifive_clint.h"
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2020-09-03 13:40:17 +03:00
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#include "hw/intc/sifive_plic.h"
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2020-09-01 04:39:01 +03:00
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#include "sysemu/sysemu.h"
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2020-09-01 04:38:59 +03:00
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/*
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* The BIOS image used by this machine is called Hart Software Services (HSS).
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* See https://github.com/polarfire-soc/hart-software-services
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*/
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#define BIOS_FILENAME "hss.bin"
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#define RESET_VECTOR 0x20220000
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2020-09-01 04:39:10 +03:00
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/* CLINT timebase frequency */
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#define CLINT_TIMEBASE_FREQ 1000000
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2020-09-01 04:39:08 +03:00
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/* GEM version */
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#define GEM_REVISION 0x0107010c
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2020-09-01 04:38:59 +03:00
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static const struct MemmapEntry {
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hwaddr base;
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hwaddr size;
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} microchip_pfsoc_memmap[] = {
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[MICROCHIP_PFSOC_DEBUG] = { 0x0, 0x1000 },
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[MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 },
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[MICROCHIP_PFSOC_BUSERR_UNIT0] = { 0x1700000, 0x1000 },
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[MICROCHIP_PFSOC_BUSERR_UNIT1] = { 0x1701000, 0x1000 },
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[MICROCHIP_PFSOC_BUSERR_UNIT2] = { 0x1702000, 0x1000 },
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[MICROCHIP_PFSOC_BUSERR_UNIT3] = { 0x1703000, 0x1000 },
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[MICROCHIP_PFSOC_BUSERR_UNIT4] = { 0x1704000, 0x1000 },
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[MICROCHIP_PFSOC_CLINT] = { 0x2000000, 0x10000 },
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[MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 },
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2020-09-01 04:39:05 +03:00
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[MICROCHIP_PFSOC_DMA] = { 0x3000000, 0x100000 },
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2020-09-01 04:38:59 +03:00
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[MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 },
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[MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 },
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2020-09-01 04:39:01 +03:00
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[MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 },
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2020-09-01 04:38:59 +03:00
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[MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 },
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[MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 },
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2020-09-01 04:39:03 +03:00
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[MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 },
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2020-09-01 04:39:01 +03:00
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[MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 },
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[MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 },
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[MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 },
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[MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 },
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2020-09-01 04:39:08 +03:00
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[MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 },
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[MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 },
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2020-09-01 04:39:09 +03:00
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[MICROCHIP_PFSOC_GPIO0] = { 0x20120000, 0x1000 },
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[MICROCHIP_PFSOC_GPIO1] = { 0x20121000, 0x1000 },
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[MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 },
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2020-09-01 04:38:59 +03:00
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[MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
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[MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
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[MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 },
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[MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 },
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};
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static void microchip_pfsoc_soc_instance_init(Object *obj)
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{
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MachineState *ms = MACHINE(qdev_get_machine());
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MicrochipPFSoCState *s = MICROCHIP_PFSOC(obj);
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object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER);
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qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0);
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object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus,
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TYPE_RISCV_HART_ARRAY);
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qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
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qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
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qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type",
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TYPE_RISCV_CPU_SIFIVE_E51);
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qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", RESET_VECTOR);
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object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
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qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
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object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus,
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TYPE_RISCV_HART_ARRAY);
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qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
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qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
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qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type",
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TYPE_RISCV_CPU_SIFIVE_U54);
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qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR);
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2020-09-01 04:39:03 +03:00
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2020-09-01 04:39:05 +03:00
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object_initialize_child(obj, "dma-controller", &s->dma,
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TYPE_SIFIVE_PDMA);
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2020-09-01 04:39:08 +03:00
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object_initialize_child(obj, "gem0", &s->gem0, TYPE_CADENCE_GEM);
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object_initialize_child(obj, "gem1", &s->gem1, TYPE_CADENCE_GEM);
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2020-09-01 04:39:03 +03:00
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object_initialize_child(obj, "sd-controller", &s->sdhci,
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TYPE_CADENCE_SDHCI);
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2020-09-01 04:38:59 +03:00
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}
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static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
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{
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MachineState *ms = MACHINE(qdev_get_machine());
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MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev);
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const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
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MemoryRegion *system_memory = get_system_memory();
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MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1);
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MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
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MemoryRegion *envm_data = g_new(MemoryRegion, 1);
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char *plic_hart_config;
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size_t plic_hart_config_len;
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2020-09-01 04:39:08 +03:00
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NICInfo *nd;
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2020-09-01 04:38:59 +03:00
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int i;
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sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
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sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort);
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/*
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* The cluster must be realized after the RISC-V hart array container,
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* as the container's CPU object is only created on realize, and the
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* CPU must exist and have been parented into the cluster before the
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* cluster is realized.
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*/
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qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort);
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qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort);
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/* E51 DTIM */
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memory_region_init_ram(e51_dtim_mem, NULL, "microchip.pfsoc.e51_dtim_mem",
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memmap[MICROCHIP_PFSOC_E51_DTIM].size, &error_fatal);
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memory_region_add_subregion(system_memory,
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memmap[MICROCHIP_PFSOC_E51_DTIM].base,
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e51_dtim_mem);
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/* Bus Error Units */
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create_unimplemented_device("microchip.pfsoc.buserr_unit0_mem",
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memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].base,
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memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].size);
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create_unimplemented_device("microchip.pfsoc.buserr_unit1_mem",
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memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].base,
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memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].size);
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create_unimplemented_device("microchip.pfsoc.buserr_unit2_mem",
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memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].base,
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memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].size);
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create_unimplemented_device("microchip.pfsoc.buserr_unit3_mem",
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memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].base,
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memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].size);
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create_unimplemented_device("microchip.pfsoc.buserr_unit4_mem",
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memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].base,
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memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].size);
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/* CLINT */
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sifive_clint_create(memmap[MICROCHIP_PFSOC_CLINT].base,
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memmap[MICROCHIP_PFSOC_CLINT].size, 0, ms->smp.cpus,
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2020-09-01 04:39:10 +03:00
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SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
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CLINT_TIMEBASE_FREQ, false);
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2020-09-01 04:38:59 +03:00
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/* L2 cache controller */
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create_unimplemented_device("microchip.pfsoc.l2cc",
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memmap[MICROCHIP_PFSOC_L2CC].base, memmap[MICROCHIP_PFSOC_L2CC].size);
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/*
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* Add L2-LIM at reset size.
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* This should be reduced in size as the L2 Cache Controller WayEnable
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* register is incremented. Unfortunately I don't see a nice (or any) way
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* to handle reducing or blocking out the L2 LIM while still allowing it
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* be re returned to all enabled after a reset. For the time being, just
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* leave it enabled all the time. This won't break anything, but will be
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* too generous to misbehaving guests.
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*/
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memory_region_init_ram(l2lim_mem, NULL, "microchip.pfsoc.l2lim",
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memmap[MICROCHIP_PFSOC_L2LIM].size, &error_fatal);
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memory_region_add_subregion(system_memory,
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memmap[MICROCHIP_PFSOC_L2LIM].base,
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l2lim_mem);
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/* create PLIC hart topology configuration string */
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plic_hart_config_len = (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1) *
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ms->smp.cpus;
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plic_hart_config = g_malloc0(plic_hart_config_len);
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for (i = 0; i < ms->smp.cpus; i++) {
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if (i != 0) {
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strncat(plic_hart_config, "," MICROCHIP_PFSOC_PLIC_HART_CONFIG,
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plic_hart_config_len);
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} else {
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strncat(plic_hart_config, "M", plic_hart_config_len);
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}
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plic_hart_config_len -= (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1);
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}
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/* PLIC */
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s->plic = sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base,
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plic_hart_config, 0,
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MICROCHIP_PFSOC_PLIC_NUM_SOURCES,
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MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES,
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MICROCHIP_PFSOC_PLIC_PRIORITY_BASE,
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MICROCHIP_PFSOC_PLIC_PENDING_BASE,
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MICROCHIP_PFSOC_PLIC_ENABLE_BASE,
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MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE,
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MICROCHIP_PFSOC_PLIC_CONTEXT_BASE,
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MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE,
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memmap[MICROCHIP_PFSOC_PLIC].size);
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g_free(plic_hart_config);
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2020-09-01 04:39:05 +03:00
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/* DMA */
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sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0,
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memmap[MICROCHIP_PFSOC_DMA].base);
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for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
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qdev_get_gpio_in(DEVICE(s->plic),
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MICROCHIP_PFSOC_DMA_IRQ0 + i));
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}
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2020-09-01 04:38:59 +03:00
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/* SYSREG */
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create_unimplemented_device("microchip.pfsoc.sysreg",
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memmap[MICROCHIP_PFSOC_SYSREG].base,
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memmap[MICROCHIP_PFSOC_SYSREG].size);
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/* MPUCFG */
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create_unimplemented_device("microchip.pfsoc.mpucfg",
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memmap[MICROCHIP_PFSOC_MPUCFG].base,
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memmap[MICROCHIP_PFSOC_MPUCFG].size);
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2020-09-01 04:39:03 +03:00
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/* SDHCI */
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sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
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memmap[MICROCHIP_PFSOC_EMMC_SD].base);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
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qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_EMMC_SD_IRQ));
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2020-09-01 04:39:01 +03:00
|
|
|
/* MMUARTs */
|
|
|
|
s->serial0 = mchp_pfsoc_mmuart_create(system_memory,
|
|
|
|
memmap[MICROCHIP_PFSOC_MMUART0].base,
|
|
|
|
qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART0_IRQ),
|
|
|
|
serial_hd(0));
|
|
|
|
s->serial1 = mchp_pfsoc_mmuart_create(system_memory,
|
|
|
|
memmap[MICROCHIP_PFSOC_MMUART1].base,
|
|
|
|
qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART1_IRQ),
|
|
|
|
serial_hd(1));
|
|
|
|
s->serial2 = mchp_pfsoc_mmuart_create(system_memory,
|
|
|
|
memmap[MICROCHIP_PFSOC_MMUART2].base,
|
|
|
|
qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART2_IRQ),
|
|
|
|
serial_hd(2));
|
|
|
|
s->serial3 = mchp_pfsoc_mmuart_create(system_memory,
|
|
|
|
memmap[MICROCHIP_PFSOC_MMUART3].base,
|
|
|
|
qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART3_IRQ),
|
|
|
|
serial_hd(3));
|
|
|
|
s->serial4 = mchp_pfsoc_mmuart_create(system_memory,
|
|
|
|
memmap[MICROCHIP_PFSOC_MMUART4].base,
|
|
|
|
qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ),
|
|
|
|
serial_hd(4));
|
|
|
|
|
2020-09-01 04:39:08 +03:00
|
|
|
/* GEMs */
|
|
|
|
|
|
|
|
nd = &nd_table[0];
|
|
|
|
if (nd->used) {
|
|
|
|
qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
|
|
|
|
qdev_set_nic_properties(DEVICE(&s->gem0), nd);
|
|
|
|
}
|
|
|
|
nd = &nd_table[1];
|
|
|
|
if (nd->used) {
|
|
|
|
qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
|
|
|
|
qdev_set_nic_properties(DEVICE(&s->gem1), nd);
|
|
|
|
}
|
|
|
|
|
|
|
|
object_property_set_int(OBJECT(&s->gem0), "revision", GEM_REVISION, errp);
|
|
|
|
object_property_set_int(OBJECT(&s->gem0), "phy-addr", 8, errp);
|
|
|
|
sysbus_realize(SYS_BUS_DEVICE(&s->gem0), errp);
|
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem0), 0,
|
|
|
|
memmap[MICROCHIP_PFSOC_GEM0].base);
|
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem0), 0,
|
|
|
|
qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM0_IRQ));
|
|
|
|
|
|
|
|
object_property_set_int(OBJECT(&s->gem1), "revision", GEM_REVISION, errp);
|
|
|
|
object_property_set_int(OBJECT(&s->gem1), "phy-addr", 9, errp);
|
|
|
|
sysbus_realize(SYS_BUS_DEVICE(&s->gem1), errp);
|
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem1), 0,
|
|
|
|
memmap[MICROCHIP_PFSOC_GEM1].base);
|
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem1), 0,
|
|
|
|
qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM1_IRQ));
|
|
|
|
|
2020-09-01 04:39:09 +03:00
|
|
|
/* GPIOs */
|
|
|
|
create_unimplemented_device("microchip.pfsoc.gpio0",
|
|
|
|
memmap[MICROCHIP_PFSOC_GPIO0].base,
|
|
|
|
memmap[MICROCHIP_PFSOC_GPIO0].size);
|
|
|
|
create_unimplemented_device("microchip.pfsoc.gpio1",
|
|
|
|
memmap[MICROCHIP_PFSOC_GPIO1].base,
|
|
|
|
memmap[MICROCHIP_PFSOC_GPIO1].size);
|
|
|
|
create_unimplemented_device("microchip.pfsoc.gpio2",
|
|
|
|
memmap[MICROCHIP_PFSOC_GPIO2].base,
|
|
|
|
memmap[MICROCHIP_PFSOC_GPIO2].size);
|
|
|
|
|
2020-09-01 04:38:59 +03:00
|
|
|
/* eNVM */
|
|
|
|
memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data",
|
|
|
|
memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
|
|
|
|
&error_fatal);
|
|
|
|
memory_region_add_subregion(system_memory,
|
|
|
|
memmap[MICROCHIP_PFSOC_ENVM_DATA].base,
|
|
|
|
envm_data);
|
|
|
|
|
|
|
|
/* IOSCBCFG */
|
|
|
|
create_unimplemented_device("microchip.pfsoc.ioscb.cfg",
|
|
|
|
memmap[MICROCHIP_PFSOC_IOSCB_CFG].base,
|
|
|
|
memmap[MICROCHIP_PFSOC_IOSCB_CFG].size);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
|
|
|
|
dc->realize = microchip_pfsoc_soc_realize;
|
|
|
|
/* Reason: Uses serial_hds in realize function, thus can't be used twice */
|
|
|
|
dc->user_creatable = false;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo microchip_pfsoc_soc_type_info = {
|
|
|
|
.name = TYPE_MICROCHIP_PFSOC,
|
|
|
|
.parent = TYPE_DEVICE,
|
|
|
|
.instance_size = sizeof(MicrochipPFSoCState),
|
|
|
|
.instance_init = microchip_pfsoc_soc_instance_init,
|
|
|
|
.class_init = microchip_pfsoc_soc_class_init,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void microchip_pfsoc_soc_register_types(void)
|
|
|
|
{
|
|
|
|
type_register_static(µchip_pfsoc_soc_type_info);
|
|
|
|
}
|
|
|
|
|
|
|
|
type_init(microchip_pfsoc_soc_register_types)
|
|
|
|
|
|
|
|
static void microchip_icicle_kit_machine_init(MachineState *machine)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_GET_CLASS(machine);
|
|
|
|
const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
|
|
|
|
MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine);
|
|
|
|
MemoryRegion *system_memory = get_system_memory();
|
|
|
|
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
|
2020-09-01 04:39:03 +03:00
|
|
|
DriveInfo *dinfo = drive_get_next(IF_SD);
|
2020-09-01 04:38:59 +03:00
|
|
|
|
|
|
|
/* Sanity check on RAM size */
|
|
|
|
if (machine->ram_size < mc->default_ram_size) {
|
|
|
|
char *sz = size_to_str(mc->default_ram_size);
|
|
|
|
error_report("Invalid RAM size, should be bigger than %s", sz);
|
|
|
|
g_free(sz);
|
|
|
|
exit(EXIT_FAILURE);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Initialize SoC */
|
|
|
|
object_initialize_child(OBJECT(machine), "soc", &s->soc,
|
|
|
|
TYPE_MICROCHIP_PFSOC);
|
|
|
|
qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
|
|
|
|
|
|
|
|
/* Register RAM */
|
|
|
|
memory_region_init_ram(main_mem, NULL, "microchip.icicle.kit.ram",
|
|
|
|
machine->ram_size, &error_fatal);
|
|
|
|
memory_region_add_subregion(system_memory,
|
|
|
|
memmap[MICROCHIP_PFSOC_DRAM].base, main_mem);
|
|
|
|
|
|
|
|
/* Load the firmware */
|
|
|
|
riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NULL);
|
2020-09-01 04:39:03 +03:00
|
|
|
|
|
|
|
/* Attach an SD card */
|
|
|
|
if (dinfo) {
|
|
|
|
CadenceSDHCIState *sdhci = &(s->soc.sdhci);
|
|
|
|
DeviceState *card = qdev_new(TYPE_SD_CARD);
|
|
|
|
|
|
|
|
qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
|
|
|
|
&error_fatal);
|
|
|
|
qdev_realize_and_unref(card, sdhci->bus, &error_fatal);
|
|
|
|
}
|
2020-09-01 04:38:59 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
|
|
|
|
mc->desc = "Microchip PolarFire SoC Icicle Kit";
|
|
|
|
mc->init = microchip_icicle_kit_machine_init;
|
|
|
|
mc->max_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT +
|
|
|
|
MICROCHIP_PFSOC_COMPUTE_CPU_COUNT;
|
|
|
|
mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1;
|
|
|
|
mc->default_cpus = mc->min_cpus;
|
|
|
|
mc->default_ram_size = 1 * GiB;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo microchip_icicle_kit_machine_typeinfo = {
|
|
|
|
.name = MACHINE_TYPE_NAME("microchip-icicle-kit"),
|
|
|
|
.parent = TYPE_MACHINE,
|
|
|
|
.class_init = microchip_icicle_kit_machine_class_init,
|
|
|
|
.instance_size = sizeof(MicrochipIcicleKitState),
|
|
|
|
};
|
|
|
|
|
|
|
|
static void microchip_icicle_kit_machine_init_register_types(void)
|
|
|
|
{
|
|
|
|
type_register_static(µchip_icicle_kit_machine_typeinfo);
|
|
|
|
}
|
|
|
|
|
|
|
|
type_init(microchip_icicle_kit_machine_init_register_types)
|