420 lines
12 KiB
C
420 lines
12 KiB
C
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/*
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* TI OMAP general purpose memory controller emulation.
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*
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* Copyright (C) 2007-2009 Nokia Corporation
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* Original code written by Andrzej Zaborowski <andrew@openedhand.com>
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* Enhancements for OMAP3 and NAND support written by Juha Riihimäki
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) any later version of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw.h"
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#include "flash.h"
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#include "omap.h"
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/* General-Purpose Memory Controller */
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struct omap_gpmc_s {
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qemu_irq irq;
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uint8_t sysconfig;
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uint16_t irqst;
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uint16_t irqen;
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uint16_t timeout;
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uint16_t config;
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uint32_t prefconfig[2];
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int prefcontrol;
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int preffifo;
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int prefcount;
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struct omap_gpmc_cs_file_s {
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uint32_t config[7];
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target_phys_addr_t base;
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size_t size;
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int iomemtype;
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void (*base_update)(void *opaque, target_phys_addr_t new);
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void (*unmap)(void *opaque);
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void *opaque;
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} cs_file[8];
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int ecc_cs;
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int ecc_ptr;
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uint32_t ecc_cfg;
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ECCState ecc[9];
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};
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static void omap_gpmc_int_update(struct omap_gpmc_s *s)
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{
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qemu_set_irq(s->irq, s->irqen & s->irqst);
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}
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static void omap_gpmc_cs_map(struct omap_gpmc_cs_file_s *f, int base, int mask)
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{
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/* TODO: check for overlapping regions and report access errors */
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if ((mask != 0x8 && mask != 0xc && mask != 0xe && mask != 0xf) ||
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(base < 0 || base >= 0x40) ||
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(base & 0x0f & ~mask)) {
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fprintf(stderr, "%s: wrong cs address mapping/decoding!\n",
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__FUNCTION__);
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return;
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}
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if (!f->opaque)
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return;
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f->base = base << 24;
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f->size = (0x0fffffff & ~(mask << 24)) + 1;
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/* TODO: rather than setting the size of the mapping (which should be
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* constant), the mask should cause wrapping of the address space, so
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* that the same memory becomes accessible at every <i>size</i> bytes
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* starting from <i>base</i>. */
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if (f->iomemtype)
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cpu_register_physical_memory(f->base, f->size, f->iomemtype);
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if (f->base_update)
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f->base_update(f->opaque, f->base);
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}
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static void omap_gpmc_cs_unmap(struct omap_gpmc_cs_file_s *f)
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{
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if (f->size) {
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if (f->unmap)
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f->unmap(f->opaque);
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if (f->iomemtype)
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cpu_register_physical_memory(f->base, f->size, IO_MEM_UNASSIGNED);
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f->base = 0;
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f->size = 0;
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}
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}
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void omap_gpmc_reset(struct omap_gpmc_s *s)
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{
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int i;
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s->sysconfig = 0;
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s->irqst = 0;
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s->irqen = 0;
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omap_gpmc_int_update(s);
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s->timeout = 0;
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s->config = 0xa00;
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s->prefconfig[0] = 0x00004000;
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s->prefconfig[1] = 0x00000000;
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s->prefcontrol = 0;
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s->preffifo = 0;
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s->prefcount = 0;
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for (i = 0; i < 8; i ++) {
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if (s->cs_file[i].config[6] & (1 << 6)) /* CSVALID */
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omap_gpmc_cs_unmap(s->cs_file + i);
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s->cs_file[i].config[0] = i ? 1 << 12 : 0;
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s->cs_file[i].config[1] = 0x101001;
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s->cs_file[i].config[2] = 0x020201;
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s->cs_file[i].config[3] = 0x10031003;
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s->cs_file[i].config[4] = 0x10f1111;
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s->cs_file[i].config[5] = 0;
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s->cs_file[i].config[6] = 0xf00 | (i ? 0 : 1 << 6);
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if (s->cs_file[i].config[6] & (1 << 6)) /* CSVALID */
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omap_gpmc_cs_map(&s->cs_file[i],
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s->cs_file[i].config[6] & 0x1f, /* MASKADDR */
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(s->cs_file[i].config[6] >> 8 & 0xf)); /* BASEADDR */
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}
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omap_gpmc_cs_map(s->cs_file, 0, 0xf);
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s->ecc_cs = 0;
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s->ecc_ptr = 0;
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s->ecc_cfg = 0x3fcff000;
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for (i = 0; i < 9; i ++)
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ecc_reset(&s->ecc[i]);
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}
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static uint32_t omap_gpmc_read(void *opaque, target_phys_addr_t addr)
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{
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struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
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int cs;
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struct omap_gpmc_cs_file_s *f;
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switch (addr) {
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case 0x000: /* GPMC_REVISION */
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return 0x20;
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case 0x010: /* GPMC_SYSCONFIG */
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return s->sysconfig;
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case 0x014: /* GPMC_SYSSTATUS */
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return 1; /* RESETDONE */
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case 0x018: /* GPMC_IRQSTATUS */
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return s->irqst;
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case 0x01c: /* GPMC_IRQENABLE */
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return s->irqen;
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case 0x040: /* GPMC_TIMEOUT_CONTROL */
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return s->timeout;
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case 0x044: /* GPMC_ERR_ADDRESS */
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case 0x048: /* GPMC_ERR_TYPE */
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return 0;
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case 0x050: /* GPMC_CONFIG */
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return s->config;
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case 0x054: /* GPMC_STATUS */
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return 0x001;
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case 0x060 ... 0x1d4:
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cs = (addr - 0x060) / 0x30;
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addr -= cs * 0x30;
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f = s->cs_file + cs;
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switch (addr) {
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case 0x60: /* GPMC_CONFIG1 */
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return f->config[0];
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case 0x64: /* GPMC_CONFIG2 */
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return f->config[1];
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case 0x68: /* GPMC_CONFIG3 */
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return f->config[2];
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case 0x6c: /* GPMC_CONFIG4 */
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return f->config[3];
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case 0x70: /* GPMC_CONFIG5 */
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return f->config[4];
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case 0x74: /* GPMC_CONFIG6 */
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return f->config[5];
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case 0x78: /* GPMC_CONFIG7 */
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return f->config[6];
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case 0x84: /* GPMC_NAND_DATA */
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return 0;
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}
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break;
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case 0x1e0: /* GPMC_PREFETCH_CONFIG1 */
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return s->prefconfig[0];
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case 0x1e4: /* GPMC_PREFETCH_CONFIG2 */
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return s->prefconfig[1];
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case 0x1ec: /* GPMC_PREFETCH_CONTROL */
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return s->prefcontrol;
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case 0x1f0: /* GPMC_PREFETCH_STATUS */
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return (s->preffifo << 24) |
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((s->preffifo >
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((s->prefconfig[0] >> 8) & 0x7f) ? 1 : 0) << 16) |
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s->prefcount;
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case 0x1f4: /* GPMC_ECC_CONFIG */
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return s->ecc_cs;
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case 0x1f8: /* GPMC_ECC_CONTROL */
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return s->ecc_ptr;
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case 0x1fc: /* GPMC_ECC_SIZE_CONFIG */
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return s->ecc_cfg;
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case 0x200 ... 0x220: /* GPMC_ECC_RESULT */
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cs = (addr & 0x1f) >> 2;
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/* TODO: check correctness */
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return
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((s->ecc[cs].cp & 0x07) << 0) |
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((s->ecc[cs].cp & 0x38) << 13) |
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((s->ecc[cs].lp[0] & 0x1ff) << 3) |
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((s->ecc[cs].lp[1] & 0x1ff) << 19);
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case 0x230: /* GPMC_TESTMODE_CTRL */
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return 0;
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case 0x234: /* GPMC_PSA_LSB */
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case 0x238: /* GPMC_PSA_MSB */
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return 0x00000000;
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}
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OMAP_BAD_REG(addr);
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return 0;
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}
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static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
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int cs;
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struct omap_gpmc_cs_file_s *f;
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switch (addr) {
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case 0x000: /* GPMC_REVISION */
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case 0x014: /* GPMC_SYSSTATUS */
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case 0x054: /* GPMC_STATUS */
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case 0x1f0: /* GPMC_PREFETCH_STATUS */
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case 0x200 ... 0x220: /* GPMC_ECC_RESULT */
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case 0x234: /* GPMC_PSA_LSB */
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case 0x238: /* GPMC_PSA_MSB */
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OMAP_RO_REG(addr);
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break;
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case 0x010: /* GPMC_SYSCONFIG */
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if ((value >> 3) == 0x3)
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fprintf(stderr, "%s: bad SDRAM idle mode %i\n",
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__FUNCTION__, value >> 3);
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if (value & 2)
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omap_gpmc_reset(s);
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s->sysconfig = value & 0x19;
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break;
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case 0x018: /* GPMC_IRQSTATUS */
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s->irqen = ~value;
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omap_gpmc_int_update(s);
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break;
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case 0x01c: /* GPMC_IRQENABLE */
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s->irqen = value & 0xf03;
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omap_gpmc_int_update(s);
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break;
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case 0x040: /* GPMC_TIMEOUT_CONTROL */
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s->timeout = value & 0x1ff1;
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break;
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case 0x044: /* GPMC_ERR_ADDRESS */
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case 0x048: /* GPMC_ERR_TYPE */
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break;
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case 0x050: /* GPMC_CONFIG */
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s->config = value & 0xf13;
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break;
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case 0x060 ... 0x1d4:
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cs = (addr - 0x060) / 0x30;
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addr -= cs * 0x30;
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f = s->cs_file + cs;
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switch (addr) {
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case 0x60: /* GPMC_CONFIG1 */
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f->config[0] = value & 0xffef3e13;
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break;
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case 0x64: /* GPMC_CONFIG2 */
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f->config[1] = value & 0x001f1f8f;
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break;
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case 0x68: /* GPMC_CONFIG3 */
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f->config[2] = value & 0x001f1f8f;
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break;
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case 0x6c: /* GPMC_CONFIG4 */
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f->config[3] = value & 0x1f8f1f8f;
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break;
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case 0x70: /* GPMC_CONFIG5 */
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f->config[4] = value & 0x0f1f1f1f;
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break;
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case 0x74: /* GPMC_CONFIG6 */
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f->config[5] = value & 0x00000fcf;
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break;
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case 0x78: /* GPMC_CONFIG7 */
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if ((f->config[6] ^ value) & 0xf7f) {
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if (f->config[6] & (1 << 6)) /* CSVALID */
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omap_gpmc_cs_unmap(f);
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if (value & (1 << 6)) /* CSVALID */
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omap_gpmc_cs_map(f, value & 0x1f, /* MASKADDR */
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(value >> 8 & 0xf)); /* BASEADDR */
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}
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f->config[6] = value & 0x00000f7f;
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break;
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case 0x7c: /* GPMC_NAND_COMMAND */
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case 0x80: /* GPMC_NAND_ADDRESS */
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case 0x84: /* GPMC_NAND_DATA */
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break;
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default:
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goto bad_reg;
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}
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break;
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case 0x1e0: /* GPMC_PREFETCH_CONFIG1 */
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s->prefconfig[0] = value & 0x7f8f7fbf;
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/* TODO: update interrupts, fifos, dmas */
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break;
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case 0x1e4: /* GPMC_PREFETCH_CONFIG2 */
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s->prefconfig[1] = value & 0x3fff;
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break;
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case 0x1ec: /* GPMC_PREFETCH_CONTROL */
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s->prefcontrol = value & 1;
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if (s->prefcontrol) {
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if (s->prefconfig[0] & 1)
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s->preffifo = 0x40;
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else
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s->preffifo = 0x00;
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}
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/* TODO: start */
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break;
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case 0x1f4: /* GPMC_ECC_CONFIG */
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s->ecc_cs = 0x8f;
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break;
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case 0x1f8: /* GPMC_ECC_CONTROL */
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if (value & (1 << 8))
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for (cs = 0; cs < 9; cs ++)
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ecc_reset(&s->ecc[cs]);
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s->ecc_ptr = value & 0xf;
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if (s->ecc_ptr == 0 || s->ecc_ptr > 9) {
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s->ecc_ptr = 0;
|
||
|
|
s->ecc_cs &= ~1;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case 0x1fc: /* GPMC_ECC_SIZE_CONFIG */
|
||
|
|
s->ecc_cfg = value & 0x3fcff1ff;
|
||
|
|
break;
|
||
|
|
case 0x230: /* GPMC_TESTMODE_CTRL */
|
||
|
|
if (value & 7)
|
||
|
|
fprintf(stderr, "%s: test mode enable attempt\n", __FUNCTION__);
|
||
|
|
break;
|
||
|
|
|
||
|
|
default:
|
||
|
|
bad_reg:
|
||
|
|
OMAP_BAD_REG(addr);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static CPUReadMemoryFunc * const omap_gpmc_readfn[] = {
|
||
|
|
omap_badwidth_read32, /* TODO */
|
||
|
|
omap_badwidth_read32, /* TODO */
|
||
|
|
omap_gpmc_read,
|
||
|
|
};
|
||
|
|
|
||
|
|
static CPUWriteMemoryFunc * const omap_gpmc_writefn[] = {
|
||
|
|
omap_badwidth_write32, /* TODO */
|
||
|
|
omap_badwidth_write32, /* TODO */
|
||
|
|
omap_gpmc_write,
|
||
|
|
};
|
||
|
|
|
||
|
|
struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq)
|
||
|
|
{
|
||
|
|
int iomemtype;
|
||
|
|
struct omap_gpmc_s *s = (struct omap_gpmc_s *)
|
||
|
|
qemu_mallocz(sizeof(struct omap_gpmc_s));
|
||
|
|
|
||
|
|
omap_gpmc_reset(s);
|
||
|
|
|
||
|
|
iomemtype = cpu_register_io_memory(omap_gpmc_readfn,
|
||
|
|
omap_gpmc_writefn, s);
|
||
|
|
cpu_register_physical_memory(base, 0x1000, iomemtype);
|
||
|
|
|
||
|
|
return s;
|
||
|
|
}
|
||
|
|
|
||
|
|
void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
|
||
|
|
void (*base_upd)(void *opaque, target_phys_addr_t new),
|
||
|
|
void (*unmap)(void *opaque), void *opaque)
|
||
|
|
{
|
||
|
|
struct omap_gpmc_cs_file_s *f;
|
||
|
|
|
||
|
|
if (cs < 0 || cs >= 8) {
|
||
|
|
fprintf(stderr, "%s: bad chip-select %i\n", __FUNCTION__, cs);
|
||
|
|
exit(-1);
|
||
|
|
}
|
||
|
|
f = &s->cs_file[cs];
|
||
|
|
|
||
|
|
f->iomemtype = iomemtype;
|
||
|
|
f->base_update = base_upd;
|
||
|
|
f->unmap = unmap;
|
||
|
|
f->opaque = opaque;
|
||
|
|
|
||
|
|
if (f->config[6] & (1 << 6)) /* CSVALID */
|
||
|
|
omap_gpmc_cs_map(f, f->config[6] & 0x1f, /* MASKADDR */
|
||
|
|
(f->config[6] >> 8 & 0xf)); /* BASEADDR */
|
||
|
|
}
|