2023-05-12 17:40:48 +03:00
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# AArch64 A64 allowed instruction decoding
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#
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# Copyright (c) 2023 Linaro, Ltd
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#
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# This library is free software; you can redistribute it and/or
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# modify it under the terms of the GNU Lesser General Public
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# License as published by the Free Software Foundation; either
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# version 2.1 of the License, or (at your option) any later version.
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#
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# This library is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# Lesser General Public License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public
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# License along with this library; if not, see <http://www.gnu.org/licenses/>.
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#
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# This file is processed by scripts/decodetree.py
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#
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2023-05-12 17:40:50 +03:00
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2024-05-25 02:20:23 +03:00
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%rd 0:5
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2024-05-25 02:20:32 +03:00
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%esz_sd 22:1 !function=plus_2
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2024-05-25 02:20:33 +03:00
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%esz_hsd 22:2 !function=xor_2
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2024-05-25 02:20:32 +03:00
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%hl 11:1 21:1
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%hlm 11:1 20:2
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2023-05-12 17:40:50 +03:00
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2024-05-25 02:20:23 +03:00
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&r rn
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&ri rd imm
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&rri_sf rd rn imm sf
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&i imm
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2024-05-25 02:20:42 +03:00
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&rr_e rd rn esz
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2024-05-25 02:20:32 +03:00
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&rrr_e rd rn rm esz
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&rrx_e rd rn rm idx esz
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2024-05-25 02:20:23 +03:00
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&qrr_e q rd rn esz
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&qrrr_e q rd rn rm esz
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2024-05-25 02:20:32 +03:00
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&qrrx_e q rd rn rm idx esz
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2024-05-25 02:20:28 +03:00
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&qrrrr_e q rd rn rm ra esz
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2024-05-25 02:20:23 +03:00
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2024-05-25 02:20:42 +03:00
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@rr_h ........ ... ..... ...... rn:5 rd:5 &rr_e esz=1
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2024-05-25 02:20:45 +03:00
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@rr_d ........ ... ..... ...... rn:5 rd:5 &rr_e esz=3
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2024-05-25 02:20:42 +03:00
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@rr_sd ........ ... ..... ...... rn:5 rd:5 &rr_e esz=%esz_sd
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2024-05-25 02:20:32 +03:00
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@rrr_h ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=1
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2024-05-28 23:30:20 +03:00
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@rrr_d ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=3
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2024-05-25 02:20:32 +03:00
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@rrr_sd ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=%esz_sd
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2024-05-25 02:20:33 +03:00
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@rrr_hsd ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=%esz_hsd
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2024-05-28 23:30:18 +03:00
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@rrr_e ........ esz:2 . rm:5 ...... rn:5 rd:5 &rrr_e
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2024-05-28 23:30:19 +03:00
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@r2r_e ........ esz:2 . ..... ...... rm:5 rd:5 &rrr_e rn=%rd
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2024-05-25 02:20:32 +03:00
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@rrx_h ........ .. .. rm:4 .... . . rn:5 rd:5 &rrx_e esz=1 idx=%hlm
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@rrx_s ........ .. . rm:5 .... . . rn:5 rd:5 &rrx_e esz=2 idx=%hl
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@rrx_d ........ .. . rm:5 .... idx:1 . rn:5 rd:5 &rrx_e esz=3
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2024-05-25 02:20:23 +03:00
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@rr_q1e0 ........ ........ ...... rn:5 rd:5 &qrr_e q=1 esz=0
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@r2r_q1e0 ........ ........ ...... rm:5 rd:5 &qrrr_e rn=%rd q=1 esz=0
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2024-05-25 02:20:24 +03:00
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@rrr_q1e0 ........ ... rm:5 ...... rn:5 rd:5 &qrrr_e q=1 esz=0
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2024-05-25 02:20:26 +03:00
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@rrr_q1e3 ........ ... rm:5 ...... rn:5 rd:5 &qrrr_e q=1 esz=3
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2024-05-25 02:20:28 +03:00
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@rrrr_q1e3 ........ ... rm:5 . ra:5 rn:5 rd:5 &qrrrr_e q=1 esz=3
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2023-05-12 17:40:50 +03:00
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2024-05-25 02:20:50 +03:00
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@qrrr_b . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=0
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2024-05-25 02:20:32 +03:00
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@qrrr_h . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=1
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@qrrr_sd . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=%esz_sd
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2024-05-25 02:20:45 +03:00
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@qrrr_e . q:1 ...... esz:2 . rm:5 ...... rn:5 rd:5 &qrrr_e
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2024-05-28 23:30:19 +03:00
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@qr2r_e . q:1 ...... esz:2 . ..... ...... rm:5 rd:5 &qrrr_e rn=%rd
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2024-05-25 02:20:32 +03:00
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@qrrx_h . q:1 .. .... .. .. rm:4 .... . . rn:5 rd:5 \
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&qrrx_e esz=1 idx=%hlm
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@qrrx_s . q:1 .. .... .. . rm:5 .... . . rn:5 rd:5 \
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&qrrx_e esz=2 idx=%hl
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@qrrx_d . q:1 .. .... .. . rm:5 .... idx:1 . rn:5 rd:5 \
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&qrrx_e esz=3
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2023-05-12 17:40:50 +03:00
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### Data Processing - Immediate
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# PC-rel addressing
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%imm_pcrel 5:s19 29:2
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@pcrel . .. ..... ................... rd:5 &ri imm=%imm_pcrel
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ADR 0 .. 10000 ................... ..... @pcrel
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ADRP 1 .. 10000 ................... ..... @pcrel
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2023-05-12 17:40:52 +03:00
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# Add/subtract (immediate)
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%imm12_sh12 10:12 !function=shl_12
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@addsub_imm sf:1 .. ...... . imm:12 rn:5 rd:5
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@addsub_imm12 sf:1 .. ...... . ............ rn:5 rd:5 imm=%imm12_sh12
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ADD_i . 00 100010 0 ............ ..... ..... @addsub_imm
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ADD_i . 00 100010 1 ............ ..... ..... @addsub_imm12
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ADDS_i . 01 100010 0 ............ ..... ..... @addsub_imm
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ADDS_i . 01 100010 1 ............ ..... ..... @addsub_imm12
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SUB_i . 10 100010 0 ............ ..... ..... @addsub_imm
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SUB_i . 10 100010 1 ............ ..... ..... @addsub_imm12
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SUBS_i . 11 100010 0 ............ ..... ..... @addsub_imm
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SUBS_i . 11 100010 1 ............ ..... ..... @addsub_imm12
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2023-05-12 17:40:53 +03:00
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# Add/subtract (immediate with tags)
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&rri_tag rd rn uimm6 uimm4
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@addsub_imm_tag . .. ...... . uimm6:6 .. uimm4:4 rn:5 rd:5 &rri_tag
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ADDG_i 1 00 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag
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SUBG_i 1 10 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag
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2023-05-12 17:40:55 +03:00
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# Logical (immediate)
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&rri_log rd rn sf dbm
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@logic_imm_64 1 .. ...... dbm:13 rn:5 rd:5 &rri_log sf=1
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@logic_imm_32 0 .. ...... 0 dbm:12 rn:5 rd:5 &rri_log sf=0
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AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_64
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AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_32
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ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_64
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ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_32
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EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_64
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EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_32
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ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_64
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ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_32
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2023-05-12 17:40:56 +03:00
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# Move wide (immediate)
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&movw rd sf imm hw
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@movw_64 1 .. ...... hw:2 imm:16 rd:5 &movw sf=1
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@movw_32 0 .. ...... 0 hw:1 imm:16 rd:5 &movw sf=0
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MOVN . 00 100101 .. ................ ..... @movw_64
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MOVN . 00 100101 .. ................ ..... @movw_32
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MOVZ . 10 100101 .. ................ ..... @movw_64
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MOVZ . 10 100101 .. ................ ..... @movw_32
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MOVK . 11 100101 .. ................ ..... @movw_64
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MOVK . 11 100101 .. ................ ..... @movw_32
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2023-05-12 17:40:57 +03:00
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# Bitfield
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&bitfield rd rn sf immr imms
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@bitfield_64 1 .. ...... 1 immr:6 imms:6 rn:5 rd:5 &bitfield sf=1
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@bitfield_32 0 .. ...... 0 0 immr:5 0 imms:5 rn:5 rd:5 &bitfield sf=0
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SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_64
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SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_32
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BFM . 01 100110 . ...... ...... ..... ..... @bitfield_64
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BFM . 01 100110 . ...... ...... ..... ..... @bitfield_32
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UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_64
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UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_32
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2023-05-12 17:40:58 +03:00
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# Extract
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&extract rd rn rm imm sf
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EXTR 1 00 100111 1 0 rm:5 imm:6 rn:5 rd:5 &extract sf=1
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EXTR 0 00 100111 0 0 rm:5 0 imm:5 rn:5 rd:5 &extract sf=0
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2023-05-12 17:40:59 +03:00
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# Branches
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%imm26 0:s26 !function=times_4
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@branch . ..... .......................... &i imm=%imm26
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B 0 00101 .......................... @branch
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BL 1 00101 .......................... @branch
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2023-05-12 17:41:00 +03:00
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%imm19 5:s19 !function=times_4
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&cbz rt imm sf nz
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CBZ sf:1 011010 nz:1 ................... rt:5 &cbz imm=%imm19
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2023-05-12 17:41:01 +03:00
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%imm14 5:s14 !function=times_4
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%imm31_19 31:1 19:5
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&tbz rt imm nz bitpos
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TBZ . 011011 nz:1 ..... .............. rt:5 &tbz imm=%imm14 bitpos=%imm31_19
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2023-05-12 17:41:02 +03:00
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2023-09-15 17:37:00 +03:00
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# B.cond and BC.cond
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B_cond 0101010 0 ................... c:1 cond:4 imm=%imm19
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2023-05-12 17:41:03 +03:00
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BR 1101011 0000 11111 000000 rn:5 00000 &r
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BLR 1101011 0001 11111 000000 rn:5 00000 &r
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RET 1101011 0010 11111 000000 rn:5 00000 &r
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2023-05-12 17:41:04 +03:00
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&braz rn m
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BRAZ 1101011 0000 11111 00001 m:1 rn:5 11111 &braz # BRAAZ, BRABZ
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BLRAZ 1101011 0001 11111 00001 m:1 rn:5 11111 &braz # BLRAAZ, BLRABZ
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&reta m
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RETA 1101011 0010 11111 00001 m:1 11111 11111 &reta # RETAA, RETAB
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2023-05-12 17:41:05 +03:00
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&bra rn rm m
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BRA 1101011 1000 11111 00001 m:1 rn:5 rm:5 &bra # BRAA, BRAB
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BLRA 1101011 1001 11111 00001 m:1 rn:5 rm:5 &bra # BLRAA, BLRAB
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2023-05-12 17:41:06 +03:00
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ERET 1101011 0100 11111 000000 11111 00000
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ERETA 1101011 0100 11111 00001 m:1 11111 11111 &reta # ERETAA, ERETAB
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# We don't need to decode DRPS because it always UNDEFs except when
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# the processor is in halting debug state (which we don't implement).
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# The pattern is listed here as documentation.
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# DRPS 1101011 0101 11111 000000 11111 00000
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2023-06-19 13:20:19 +03:00
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# Hint instruction group
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{
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[
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YIELD 1101 0101 0000 0011 0010 0000 001 11111
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WFE 1101 0101 0000 0011 0010 0000 010 11111
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WFI 1101 0101 0000 0011 0010 0000 011 11111
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# We implement WFE to never block, so our SEV/SEVL are NOPs
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# SEV 1101 0101 0000 0011 0010 0000 100 11111
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# SEVL 1101 0101 0000 0011 0010 0000 101 11111
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# Our DGL is a NOP because we don't merge memory accesses anyway.
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# DGL 1101 0101 0000 0011 0010 0000 110 11111
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XPACLRI 1101 0101 0000 0011 0010 0000 111 11111
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PACIA1716 1101 0101 0000 0011 0010 0001 000 11111
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PACIB1716 1101 0101 0000 0011 0010 0001 010 11111
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AUTIA1716 1101 0101 0000 0011 0010 0001 100 11111
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AUTIB1716 1101 0101 0000 0011 0010 0001 110 11111
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ESB 1101 0101 0000 0011 0010 0010 000 11111
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PACIAZ 1101 0101 0000 0011 0010 0011 000 11111
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PACIASP 1101 0101 0000 0011 0010 0011 001 11111
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PACIBZ 1101 0101 0000 0011 0010 0011 010 11111
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PACIBSP 1101 0101 0000 0011 0010 0011 011 11111
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AUTIAZ 1101 0101 0000 0011 0010 0011 100 11111
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AUTIASP 1101 0101 0000 0011 0010 0011 101 11111
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AUTIBZ 1101 0101 0000 0011 0010 0011 110 11111
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AUTIBSP 1101 0101 0000 0011 0010 0011 111 11111
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]
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# The canonical NOP has CRm == op2 == 0, but all of the space
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# that isn't specifically allocated to an instruction must NOP
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NOP 1101 0101 0000 0011 0010 ---- --- 11111
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}
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2023-06-19 13:20:20 +03:00
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# Barriers
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CLREX 1101 0101 0000 0011 0011 ---- 010 11111
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DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111
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ISB 1101 0101 0000 0011 0011 ---- 110 11111
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SB 1101 0101 0000 0011 0011 0000 111 11111
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2023-06-19 13:20:20 +03:00
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# PSTATE
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CFINV 1101 0101 0000 0 000 0100 0000 000 11111
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XAFLAG 1101 0101 0000 0 000 0100 0000 001 11111
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AXFLAG 1101 0101 0000 0 000 0100 0000 010 11111
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2023-06-19 13:20:20 +03:00
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|
|
|
|
# These are architecturally all "MSR (immediate)"; we decode the destination
|
|
|
|
|
# register too because there is no commonality in our implementation.
|
|
|
|
|
@msr_i .... .... .... . ... .... imm:4 ... .....
|
|
|
|
|
MSR_i_UAO 1101 0101 0000 0 000 0100 .... 011 11111 @msr_i
|
|
|
|
|
MSR_i_PAN 1101 0101 0000 0 000 0100 .... 100 11111 @msr_i
|
|
|
|
|
MSR_i_SPSEL 1101 0101 0000 0 000 0100 .... 101 11111 @msr_i
|
|
|
|
|
MSR_i_SBSS 1101 0101 0000 0 011 0100 .... 001 11111 @msr_i
|
|
|
|
|
MSR_i_DIT 1101 0101 0000 0 011 0100 .... 010 11111 @msr_i
|
|
|
|
|
MSR_i_TCO 1101 0101 0000 0 011 0100 .... 100 11111 @msr_i
|
|
|
|
|
MSR_i_DAIFSET 1101 0101 0000 0 011 0100 .... 110 11111 @msr_i
|
|
|
|
|
MSR_i_DAIFCLEAR 1101 0101 0000 0 011 0100 .... 111 11111 @msr_i
|
2024-04-19 16:32:57 +03:00
|
|
|
MSR_i_ALLINT 1101 0101 0000 0 001 0100 000 imm:1 000 11111
|
2023-06-19 13:20:20 +03:00
|
|
|
MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111
|
2023-06-19 13:20:20 +03:00
|
|
|
|
|
|
|
|
# MRS, MSR (register), SYS, SYSL. These are all essentially the
|
|
|
|
|
# same instruction as far as QEMU is concerned.
|
|
|
|
|
# NB: op0 is bits [20:19], but op0=0b00 is other insns, so we have
|
|
|
|
|
# to hand-decode it.
|
|
|
|
|
SYS 1101 0101 00 l:1 01 op1:3 crn:4 crm:4 op2:3 rt:5 op0=1
|
|
|
|
|
SYS 1101 0101 00 l:1 10 op1:3 crn:4 crm:4 op2:3 rt:5 op0=2
|
|
|
|
|
SYS 1101 0101 00 l:1 11 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3
|
2023-06-19 13:20:21 +03:00
|
|
|
|
|
|
|
|
# Exception generation
|
|
|
|
|
|
|
|
|
|
@i16 .... .... ... imm:16 ... .. &i
|
|
|
|
|
SVC 1101 0100 000 ................ 000 01 @i16
|
|
|
|
|
HVC 1101 0100 000 ................ 000 10 @i16
|
|
|
|
|
SMC 1101 0100 000 ................ 000 11 @i16
|
|
|
|
|
BRK 1101 0100 001 ................ 000 00 @i16
|
|
|
|
|
HLT 1101 0100 010 ................ 000 00 @i16
|
|
|
|
|
# These insns always UNDEF unless in halting debug state, which
|
|
|
|
|
# we don't implement. So we don't need to decode them. The patterns
|
|
|
|
|
# are listed here as documentation.
|
|
|
|
|
# DCPS1 1101 0100 101 ................ 000 01 @i16
|
|
|
|
|
# DCPS2 1101 0100 101 ................ 000 10 @i16
|
|
|
|
|
# DCPS3 1101 0100 101 ................ 000 11 @i16
|
target/arm: Convert load/store exclusive and ordered to decodetree
Convert the instructions in the load/store exclusive (STXR,
STLXR, LDXR, LDAXR) and load/store ordered (STLR, STLLR,
LDAR, LDLAR) to decodetree.
Note that for STLR, STLLR, LDAR, LDLAR this fixes an under-decoding
in the legacy decoder where we were not checking that the RES1 bits
in the Rs and Rt2 fields were set.
The new function ldst_iss_sf() is equivalent to the existing
disas_ldst_compute_iss_sf(), but it takes the pre-decoded 'ext' field
rather than taking an undecoded two-bit opc field and extracting
'ext' from it. Once all the loads and stores have been converted
to decodetree disas_ldst_compute_iss_sf() will be unused and
can be deleted.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230602155223.2040685-9-peter.maydell@linaro.org
2023-06-19 13:20:21 +03:00
|
|
|
|
|
|
|
|
# Loads and stores
|
|
|
|
|
|
|
|
|
|
&stxr rn rt rt2 rs sz lasr
|
|
|
|
|
&stlr rn rt sz lasr
|
|
|
|
|
@stxr sz:2 ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr
|
|
|
|
|
@stlr sz:2 ...... ... ..... lasr:1 ..... rn:5 rt:5 &stlr
|
target/arm: Convert LDXP, STXP, CASP, CAS to decodetree
Convert the load/store exclusive pair (LDXP, STXP, LDAXP, STLXP),
compare-and-swap pair (CASP, CASPA, CASPAL, CASPL), and compare-and
swap (CAS, CASA, CASAL, CASL) instructions to decodetree.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230602155223.2040685-10-peter.maydell@linaro.org
2023-06-19 13:20:21 +03:00
|
|
|
%imm1_30_p2 30:1 !function=plus_2
|
|
|
|
|
@stxp .. ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr sz=%imm1_30_p2
|
target/arm: Convert load/store exclusive and ordered to decodetree
Convert the instructions in the load/store exclusive (STXR,
STLXR, LDXR, LDAXR) and load/store ordered (STLR, STLLR,
LDAR, LDLAR) to decodetree.
Note that for STLR, STLLR, LDAR, LDLAR this fixes an under-decoding
in the legacy decoder where we were not checking that the RES1 bits
in the Rs and Rt2 fields were set.
The new function ldst_iss_sf() is equivalent to the existing
disas_ldst_compute_iss_sf(), but it takes the pre-decoded 'ext' field
rather than taking an undecoded two-bit opc field and extracting
'ext' from it. Once all the loads and stores have been converted
to decodetree disas_ldst_compute_iss_sf() will be unused and
can be deleted.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230602155223.2040685-9-peter.maydell@linaro.org
2023-06-19 13:20:21 +03:00
|
|
|
STXR .. 001000 000 ..... . ..... ..... ..... @stxr # inc STLXR
|
|
|
|
|
LDXR .. 001000 010 ..... . ..... ..... ..... @stxr # inc LDAXR
|
|
|
|
|
STLR .. 001000 100 11111 . 11111 ..... ..... @stlr # inc STLLR
|
|
|
|
|
LDAR .. 001000 110 11111 . 11111 ..... ..... @stlr # inc LDLAR
|
target/arm: Convert LDXP, STXP, CASP, CAS to decodetree
Convert the load/store exclusive pair (LDXP, STXP, LDAXP, STLXP),
compare-and-swap pair (CASP, CASPA, CASPAL, CASPL), and compare-and
swap (CAS, CASA, CASAL, CASL) instructions to decodetree.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230602155223.2040685-10-peter.maydell@linaro.org
2023-06-19 13:20:21 +03:00
|
|
|
|
|
|
|
|
STXP 1 . 001000 001 ..... . ..... ..... ..... @stxp # inc STLXP
|
|
|
|
|
LDXP 1 . 001000 011 ..... . ..... ..... ..... @stxp # inc LDAXP
|
|
|
|
|
|
|
|
|
|
# CASP, CASPA, CASPAL, CASPL (we don't decode the bits that determine
|
|
|
|
|
# acquire/release semantics because QEMU's cmpxchg always has those)
|
|
|
|
|
CASP 0 . 001000 0 - 1 rs:5 - 11111 rn:5 rt:5 sz=%imm1_30_p2
|
|
|
|
|
# CAS, CASA, CASAL, CASL
|
|
|
|
|
CAS sz:2 001000 1 - 1 rs:5 - 11111 rn:5 rt:5
|
2023-06-19 13:20:21 +03:00
|
|
|
|
|
|
|
|
&ldlit rt imm sz sign
|
|
|
|
|
@ldlit .. ... . .. ................... rt:5 &ldlit imm=%imm19
|
|
|
|
|
|
|
|
|
|
LD_lit 00 011 0 00 ................... ..... @ldlit sz=2 sign=0
|
|
|
|
|
LD_lit 01 011 0 00 ................... ..... @ldlit sz=3 sign=0
|
|
|
|
|
LD_lit 10 011 0 00 ................... ..... @ldlit sz=2 sign=1
|
|
|
|
|
LD_lit_v 00 011 1 00 ................... ..... @ldlit sz=2 sign=0
|
|
|
|
|
LD_lit_v 01 011 1 00 ................... ..... @ldlit sz=3 sign=0
|
|
|
|
|
LD_lit_v 10 011 1 00 ................... ..... @ldlit sz=4 sign=0
|
|
|
|
|
|
|
|
|
|
# PRFM
|
|
|
|
|
NOP 11 011 0 00 ------------------- -----
|
2023-06-19 13:20:22 +03:00
|
|
|
|
|
|
|
|
&ldstpair rt2 rt rn imm sz sign w p
|
|
|
|
|
@ldstpair .. ... . ... . imm:s7 rt2:5 rn:5 rt:5 &ldstpair
|
|
|
|
|
|
|
|
|
|
# STNP, LDNP: Signed offset, non-temporal hint. We don't emulate caches
|
|
|
|
|
# so we ignore hints about data access patterns, and handle these like
|
|
|
|
|
# plain signed offset.
|
|
|
|
|
STP 00 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
|
|
|
|
|
LDP 00 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
|
|
|
|
|
STP 10 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
|
|
|
|
|
LDP 10 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
|
|
|
|
|
STP_v 00 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
|
|
|
|
|
LDP_v 00 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
|
|
|
|
|
STP_v 01 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
|
|
|
|
|
LDP_v 01 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
|
|
|
|
|
STP_v 10 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0
|
|
|
|
|
LDP_v 10 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0
|
|
|
|
|
|
|
|
|
|
# STP and LDP: post-indexed
|
|
|
|
|
STP 00 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1
|
|
|
|
|
LDP 00 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1
|
|
|
|
|
LDP 01 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=1 w=1
|
|
|
|
|
STP 10 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1
|
|
|
|
|
LDP 10 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1
|
|
|
|
|
STP_v 00 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1
|
|
|
|
|
LDP_v 00 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1
|
|
|
|
|
STP_v 01 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1
|
|
|
|
|
LDP_v 01 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1
|
|
|
|
|
STP_v 10 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1
|
|
|
|
|
LDP_v 10 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1
|
|
|
|
|
|
|
|
|
|
# STP and LDP: offset
|
|
|
|
|
STP 00 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
|
|
|
|
|
LDP 00 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
|
|
|
|
|
LDP 01 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=0
|
|
|
|
|
STP 10 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
|
|
|
|
|
LDP 10 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
|
|
|
|
|
STP_v 00 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
|
|
|
|
|
LDP_v 00 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0
|
|
|
|
|
STP_v 01 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
|
|
|
|
|
LDP_v 01 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
|
|
|
|
|
STP_v 10 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0
|
|
|
|
|
LDP_v 10 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0
|
|
|
|
|
|
|
|
|
|
# STP and LDP: pre-indexed
|
|
|
|
|
STP 00 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1
|
|
|
|
|
LDP 00 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1
|
|
|
|
|
LDP 01 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=1
|
|
|
|
|
STP 10 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1
|
|
|
|
|
LDP 10 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1
|
|
|
|
|
STP_v 00 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1
|
|
|
|
|
LDP_v 00 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1
|
|
|
|
|
STP_v 01 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1
|
|
|
|
|
LDP_v 01 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1
|
|
|
|
|
STP_v 10 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1
|
|
|
|
|
LDP_v 10 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1
|
|
|
|
|
|
|
|
|
|
# STGP: store tag and pair
|
|
|
|
|
STGP 01 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1
|
|
|
|
|
STGP 01 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0
|
|
|
|
|
STGP 01 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1
|
2023-06-19 13:20:22 +03:00
|
|
|
|
|
|
|
|
# Load/store register (unscaled immediate)
|
|
|
|
|
&ldst_imm rt rn imm sz sign w p unpriv ext
|
|
|
|
|
@ldst_imm .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=0
|
|
|
|
|
@ldst_imm_pre .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=1
|
|
|
|
|
@ldst_imm_post .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=0 p=1 w=1
|
|
|
|
|
@ldst_imm_user .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=1 p=0 w=0
|
|
|
|
|
|
|
|
|
|
STR_i sz:2 111 0 00 00 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0
|
|
|
|
|
LDR_i 00 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=0
|
|
|
|
|
LDR_i 01 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=1
|
|
|
|
|
LDR_i 10 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=1 sz=2
|
|
|
|
|
LDR_i 11 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=3
|
|
|
|
|
LDR_i 00 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=0
|
|
|
|
|
LDR_i 01 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=1
|
|
|
|
|
LDR_i 10 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=0 sz=2
|
|
|
|
|
LDR_i 00 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=1 sz=0
|
|
|
|
|
LDR_i 01 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign=1 ext=1 sz=1
|
|
|
|
|
|
|
|
|
|
STR_i sz:2 111 0 00 00 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0
|
|
|
|
|
LDR_i 00 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=0
|
|
|
|
|
LDR_i 01 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=1
|
|
|
|
|
LDR_i 10 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=1 sz=2
|
|
|
|
|
LDR_i 11 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=3
|
|
|
|
|
LDR_i 00 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=0
|
|
|
|
|
LDR_i 01 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=1
|
|
|
|
|
LDR_i 10 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=0 sz=2
|
|
|
|
|
LDR_i 00 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=1 sz=0
|
|
|
|
|
LDR_i 01 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=1 ext=1 sz=1
|
|
|
|
|
|
|
|
|
|
STR_i sz:2 111 0 00 00 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=0
|
|
|
|
|
LDR_i 00 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=0
|
|
|
|
|
LDR_i 01 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=1
|
|
|
|
|
LDR_i 10 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=1 sz=2
|
|
|
|
|
LDR_i 11 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user sign=0 ext=0 sz=3
|
|
|
|
|
LDR_i 00 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=0
|
|
|
|
|
LDR_i 01 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=1
|
|
|
|
|
LDR_i 10 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=0 sz=2
|
|
|
|
|
LDR_i 00 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=1 sz=0
|
|
|
|
|
LDR_i 01 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user sign=1 ext=1 sz=1
|
|
|
|
|
|
|
|
|
|
STR_i sz:2 111 0 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0
|
|
|
|
|
LDR_i 00 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=0
|
|
|
|
|
LDR_i 01 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=1
|
|
|
|
|
LDR_i 10 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=1 sz=2
|
|
|
|
|
LDR_i 11 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=3
|
|
|
|
|
LDR_i 00 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=0
|
|
|
|
|
LDR_i 01 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=1
|
|
|
|
|
LDR_i 10 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=0 sz=2
|
|
|
|
|
LDR_i 00 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=1 sz=0
|
|
|
|
|
LDR_i 01 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=1 ext=1 sz=1
|
|
|
|
|
|
|
|
|
|
# PRFM : prefetch memory: a no-op for QEMU
|
|
|
|
|
NOP 11 111 0 00 10 0 --------- 00 ----- -----
|
|
|
|
|
|
|
|
|
|
STR_v_i sz:2 111 1 00 00 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0
|
|
|
|
|
STR_v_i 00 111 1 00 10 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=4
|
|
|
|
|
LDR_v_i sz:2 111 1 00 01 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0
|
|
|
|
|
LDR_v_i 00 111 1 00 11 0 ......... 00 ..... ..... @ldst_imm sign=0 ext=0 sz=4
|
|
|
|
|
|
|
|
|
|
STR_v_i sz:2 111 1 00 00 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0
|
|
|
|
|
STR_v_i 00 111 1 00 10 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=4
|
|
|
|
|
LDR_v_i sz:2 111 1 00 01 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0
|
|
|
|
|
LDR_v_i 00 111 1 00 11 0 ......... 01 ..... ..... @ldst_imm_post sign=0 ext=0 sz=4
|
|
|
|
|
|
|
|
|
|
STR_v_i sz:2 111 1 00 00 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0
|
|
|
|
|
STR_v_i 00 111 1 00 10 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4
|
|
|
|
|
LDR_v_i sz:2 111 1 00 01 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0
|
|
|
|
|
LDR_v_i 00 111 1 00 11 0 ......... 11 ..... ..... @ldst_imm_pre sign=0 ext=0 sz=4
|
2023-06-19 13:20:22 +03:00
|
|
|
|
|
|
|
|
# Load/store with an unsigned 12 bit immediate, which is scaled by the
|
|
|
|
|
# element size. The function gets the sz:imm and returns the scaled immediate.
|
|
|
|
|
%uimm_scaled 10:12 sz:3 !function=uimm_scaled
|
|
|
|
|
|
|
|
|
|
@ldst_uimm .. ... . .. .. ............ rn:5 rt:5 &ldst_imm unpriv=0 p=0 w=0 imm=%uimm_scaled
|
|
|
|
|
|
|
|
|
|
STR_i sz:2 111 0 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=0
|
|
|
|
|
LDR_i 00 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=0
|
|
|
|
|
LDR_i 01 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=1
|
|
|
|
|
LDR_i 10 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=1 sz=2
|
|
|
|
|
LDR_i 11 111 0 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=3
|
|
|
|
|
LDR_i 00 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=0
|
|
|
|
|
LDR_i 01 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=1
|
|
|
|
|
LDR_i 10 111 0 01 10 ............ ..... ..... @ldst_uimm sign=1 ext=0 sz=2
|
|
|
|
|
LDR_i 00 111 0 01 11 ............ ..... ..... @ldst_uimm sign=1 ext=1 sz=0
|
|
|
|
|
LDR_i 01 111 0 01 11 ............ ..... ..... @ldst_uimm sign=1 ext=1 sz=1
|
|
|
|
|
|
|
|
|
|
# PRFM
|
|
|
|
|
NOP 11 111 0 01 10 ------------ ----- -----
|
|
|
|
|
|
|
|
|
|
STR_v_i sz:2 111 1 01 00 ............ ..... ..... @ldst_uimm sign=0 ext=0
|
|
|
|
|
STR_v_i 00 111 1 01 10 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4
|
|
|
|
|
LDR_v_i sz:2 111 1 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0
|
|
|
|
|
LDR_v_i 00 111 1 01 11 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4
|
2023-06-19 13:20:23 +03:00
|
|
|
|
|
|
|
|
# Load/store with register offset
|
|
|
|
|
&ldst rm rn rt sign ext sz opt s
|
|
|
|
|
@ldst .. ... . .. .. . rm:5 opt:3 s:1 .. rn:5 rt:5 &ldst
|
|
|
|
|
STR sz:2 111 0 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0
|
|
|
|
|
LDR 00 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=0
|
|
|
|
|
LDR 01 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=1
|
|
|
|
|
LDR 10 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=1 sz=2
|
|
|
|
|
LDR 11 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=3
|
|
|
|
|
LDR 00 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=0
|
|
|
|
|
LDR 01 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=1
|
|
|
|
|
LDR 10 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=0 sz=2
|
|
|
|
|
LDR 00 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=1 sz=0
|
|
|
|
|
LDR 01 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=1 ext=1 sz=1
|
|
|
|
|
|
|
|
|
|
# PRFM
|
|
|
|
|
NOP 11 111 0 00 10 1 ----- -1- - 10 ----- -----
|
|
|
|
|
|
|
|
|
|
STR_v sz:2 111 1 00 00 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0
|
|
|
|
|
STR_v 00 111 1 00 10 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4
|
|
|
|
|
LDR_v sz:2 111 1 00 01 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0
|
|
|
|
|
LDR_v 00 111 1 00 11 1 ..... ... . 10 ..... ..... @ldst sign=0 ext=0 sz=4
|
2023-06-19 13:20:23 +03:00
|
|
|
|
|
|
|
|
# Atomic memory operations
|
|
|
|
|
&atomic rs rn rt a r sz
|
|
|
|
|
@atomic sz:2 ... . .. a:1 r:1 . rs:5 . ... .. rn:5 rt:5 &atomic
|
|
|
|
|
LDADD .. 111 0 00 . . 1 ..... 0000 00 ..... ..... @atomic
|
|
|
|
|
LDCLR .. 111 0 00 . . 1 ..... 0001 00 ..... ..... @atomic
|
|
|
|
|
LDEOR .. 111 0 00 . . 1 ..... 0010 00 ..... ..... @atomic
|
|
|
|
|
LDSET .. 111 0 00 . . 1 ..... 0011 00 ..... ..... @atomic
|
|
|
|
|
LDSMAX .. 111 0 00 . . 1 ..... 0100 00 ..... ..... @atomic
|
|
|
|
|
LDSMIN .. 111 0 00 . . 1 ..... 0101 00 ..... ..... @atomic
|
|
|
|
|
LDUMAX .. 111 0 00 . . 1 ..... 0110 00 ..... ..... @atomic
|
|
|
|
|
LDUMIN .. 111 0 00 . . 1 ..... 0111 00 ..... ..... @atomic
|
|
|
|
|
SWP .. 111 0 00 . . 1 ..... 1000 00 ..... ..... @atomic
|
|
|
|
|
|
|
|
|
|
LDAPR sz:2 111 0 00 1 0 1 11111 1100 00 rn:5 rt:5
|
2023-06-19 13:20:23 +03:00
|
|
|
|
|
|
|
|
# Load/store register (pointer authentication)
|
|
|
|
|
|
|
|
|
|
# LDRA immediate is 10 bits signed and scaled, but the bits aren't all contiguous
|
2023-11-06 18:00:29 +03:00
|
|
|
%ldra_imm 22:s1 12:9 !function=times_8
|
2023-06-19 13:20:23 +03:00
|
|
|
|
|
|
|
|
LDRA 11 111 0 00 m:1 . 1 ......... w:1 1 rn:5 rt:5 imm=%ldra_imm
|
2023-06-19 13:20:23 +03:00
|
|
|
|
|
|
|
|
&ldapr_stlr_i rn rt imm sz sign ext
|
|
|
|
|
@ldapr_stlr_i .. ...... .. . imm:9 .. rn:5 rt:5 &ldapr_stlr_i
|
|
|
|
|
STLR_i sz:2 011001 00 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0 ext=0
|
|
|
|
|
LDAPR_i sz:2 011001 01 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0 ext=0
|
|
|
|
|
LDAPR_i 00 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=0
|
|
|
|
|
LDAPR_i 01 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=1
|
|
|
|
|
LDAPR_i 10 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=0 sz=2
|
|
|
|
|
LDAPR_i 00 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=1 sz=0
|
|
|
|
|
LDAPR_i 01 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1 ext=1 sz=1
|
2023-06-19 13:20:24 +03:00
|
|
|
|
|
|
|
|
# Load/store multiple structures
|
|
|
|
|
# The 4-bit opcode in [15:12] encodes repeat count and structure elements
|
|
|
|
|
&ldst_mult rm rn rt sz q p rpt selem
|
|
|
|
|
@ldst_mult . q:1 ...... p:1 . . rm:5 .... sz:2 rn:5 rt:5 &ldst_mult
|
|
|
|
|
ST_mult 0 . 001100 . 0 0 ..... 0000 .. ..... ..... @ldst_mult rpt=1 selem=4
|
|
|
|
|
ST_mult 0 . 001100 . 0 0 ..... 0010 .. ..... ..... @ldst_mult rpt=4 selem=1
|
|
|
|
|
ST_mult 0 . 001100 . 0 0 ..... 0100 .. ..... ..... @ldst_mult rpt=1 selem=3
|
|
|
|
|
ST_mult 0 . 001100 . 0 0 ..... 0110 .. ..... ..... @ldst_mult rpt=3 selem=1
|
|
|
|
|
ST_mult 0 . 001100 . 0 0 ..... 0111 .. ..... ..... @ldst_mult rpt=1 selem=1
|
|
|
|
|
ST_mult 0 . 001100 . 0 0 ..... 1000 .. ..... ..... @ldst_mult rpt=1 selem=2
|
|
|
|
|
ST_mult 0 . 001100 . 0 0 ..... 1010 .. ..... ..... @ldst_mult rpt=2 selem=1
|
|
|
|
|
|
|
|
|
|
LD_mult 0 . 001100 . 1 0 ..... 0000 .. ..... ..... @ldst_mult rpt=1 selem=4
|
|
|
|
|
LD_mult 0 . 001100 . 1 0 ..... 0010 .. ..... ..... @ldst_mult rpt=4 selem=1
|
|
|
|
|
LD_mult 0 . 001100 . 1 0 ..... 0100 .. ..... ..... @ldst_mult rpt=1 selem=3
|
|
|
|
|
LD_mult 0 . 001100 . 1 0 ..... 0110 .. ..... ..... @ldst_mult rpt=3 selem=1
|
|
|
|
|
LD_mult 0 . 001100 . 1 0 ..... 0111 .. ..... ..... @ldst_mult rpt=1 selem=1
|
|
|
|
|
LD_mult 0 . 001100 . 1 0 ..... 1000 .. ..... ..... @ldst_mult rpt=1 selem=2
|
|
|
|
|
LD_mult 0 . 001100 . 1 0 ..... 1010 .. ..... ..... @ldst_mult rpt=2 selem=1
|
2023-06-19 13:20:24 +03:00
|
|
|
|
|
|
|
|
# Load/store single structure
|
|
|
|
|
&ldst_single rm rn rt p selem index scale
|
|
|
|
|
|
|
|
|
|
%ldst_single_selem 13:1 21:1 !function=plus_1
|
|
|
|
|
|
|
|
|
|
%ldst_single_index_b 30:1 10:3
|
|
|
|
|
%ldst_single_index_h 30:1 11:2
|
|
|
|
|
%ldst_single_index_s 30:1 12:1
|
|
|
|
|
|
|
|
|
|
@ldst_single_b .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \
|
|
|
|
|
&ldst_single scale=0 selem=%ldst_single_selem \
|
|
|
|
|
index=%ldst_single_index_b
|
|
|
|
|
@ldst_single_h .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \
|
|
|
|
|
&ldst_single scale=1 selem=%ldst_single_selem \
|
|
|
|
|
index=%ldst_single_index_h
|
|
|
|
|
@ldst_single_s .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \
|
|
|
|
|
&ldst_single scale=2 selem=%ldst_single_selem \
|
|
|
|
|
index=%ldst_single_index_s
|
|
|
|
|
@ldst_single_d . index:1 ...... p:1 .. rm:5 ...... rn:5 rt:5 \
|
|
|
|
|
&ldst_single scale=3 selem=%ldst_single_selem
|
|
|
|
|
|
|
|
|
|
ST_single 0 . 001101 . 0 . ..... 00 . ... ..... ..... @ldst_single_b
|
|
|
|
|
ST_single 0 . 001101 . 0 . ..... 01 . ..0 ..... ..... @ldst_single_h
|
|
|
|
|
ST_single 0 . 001101 . 0 . ..... 10 . .00 ..... ..... @ldst_single_s
|
|
|
|
|
ST_single 0 . 001101 . 0 . ..... 10 . 001 ..... ..... @ldst_single_d
|
|
|
|
|
|
|
|
|
|
LD_single 0 . 001101 . 1 . ..... 00 . ... ..... ..... @ldst_single_b
|
|
|
|
|
LD_single 0 . 001101 . 1 . ..... 01 . ..0 ..... ..... @ldst_single_h
|
|
|
|
|
LD_single 0 . 001101 . 1 . ..... 10 . .00 ..... ..... @ldst_single_s
|
|
|
|
|
LD_single 0 . 001101 . 1 . ..... 10 . 001 ..... ..... @ldst_single_d
|
|
|
|
|
|
|
|
|
|
# Replicating load case
|
|
|
|
|
LD_single_repl 0 q:1 001101 p:1 1 . rm:5 11 . 0 scale:2 rn:5 rt:5 selem=%ldst_single_selem
|
2023-06-19 13:20:24 +03:00
|
|
|
|
|
|
|
|
%tag_offset 12:s9 !function=scale_by_log2_tag_granule
|
|
|
|
|
&ldst_tag rn rt imm p w
|
|
|
|
|
@ldst_tag ........ .. . ......... .. rn:5 rt:5 &ldst_tag imm=%tag_offset
|
|
|
|
|
@ldst_tag_mult ........ .. . 000000000 .. rn:5 rt:5 &ldst_tag imm=0
|
|
|
|
|
|
|
|
|
|
STZGM 11011001 00 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0
|
|
|
|
|
STG 11011001 00 1 ......... 01 ..... ..... @ldst_tag p=1 w=1
|
|
|
|
|
STG 11011001 00 1 ......... 10 ..... ..... @ldst_tag p=0 w=0
|
|
|
|
|
STG 11011001 00 1 ......... 11 ..... ..... @ldst_tag p=0 w=1
|
|
|
|
|
|
|
|
|
|
LDG 11011001 01 1 ......... 00 ..... ..... @ldst_tag p=0 w=0
|
|
|
|
|
STZG 11011001 01 1 ......... 01 ..... ..... @ldst_tag p=1 w=1
|
|
|
|
|
STZG 11011001 01 1 ......... 10 ..... ..... @ldst_tag p=0 w=0
|
|
|
|
|
STZG 11011001 01 1 ......... 11 ..... ..... @ldst_tag p=0 w=1
|
|
|
|
|
|
|
|
|
|
STGM 11011001 10 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0
|
|
|
|
|
ST2G 11011001 10 1 ......... 01 ..... ..... @ldst_tag p=1 w=1
|
|
|
|
|
ST2G 11011001 10 1 ......... 10 ..... ..... @ldst_tag p=0 w=0
|
|
|
|
|
ST2G 11011001 10 1 ......... 11 ..... ..... @ldst_tag p=0 w=1
|
|
|
|
|
|
|
|
|
|
LDGM 11011001 11 1 ......... 00 ..... ..... @ldst_tag_mult p=0 w=0
|
|
|
|
|
STZ2G 11011001 11 1 ......... 01 ..... ..... @ldst_tag p=1 w=1
|
|
|
|
|
STZ2G 11011001 11 1 ......... 10 ..... ..... @ldst_tag p=0 w=0
|
|
|
|
|
STZ2G 11011001 11 1 ......... 11 ..... ..... @ldst_tag p=0 w=1
|
2023-09-12 17:04:29 +03:00
|
|
|
|
|
|
|
|
# Memory operations (memset, memcpy, memmove)
|
|
|
|
|
# Each of these comes in a set of three, eg SETP (prologue), SETM (main),
|
|
|
|
|
# SETE (epilogue), and each of those has different flavours to
|
|
|
|
|
# indicate whether memory accesses should be unpriv or non-temporal.
|
|
|
|
|
# We don't distinguish temporal and non-temporal accesses, but we
|
|
|
|
|
# do need to report it in syndrome register values.
|
|
|
|
|
|
|
|
|
|
# Memset
|
|
|
|
|
&set rs rn rd unpriv nontemp
|
|
|
|
|
# op2 bit 1 is nontemporal bit
|
|
|
|
|
@set .. ......... rs:5 .. nontemp:1 unpriv:1 .. rn:5 rd:5 &set
|
|
|
|
|
|
|
|
|
|
SETP 00 011001110 ..... 00 . . 01 ..... ..... @set
|
|
|
|
|
SETM 00 011001110 ..... 01 . . 01 ..... ..... @set
|
|
|
|
|
SETE 00 011001110 ..... 10 . . 01 ..... ..... @set
|
2023-09-12 17:04:31 +03:00
|
|
|
|
|
|
|
|
# Like SET, but also setting MTE tags
|
|
|
|
|
SETGP 00 011101110 ..... 00 . . 01 ..... ..... @set
|
|
|
|
|
SETGM 00 011101110 ..... 01 . . 01 ..... ..... @set
|
|
|
|
|
SETGE 00 011101110 ..... 10 . . 01 ..... ..... @set
|
2023-09-12 17:04:33 +03:00
|
|
|
|
|
|
|
|
# Memmove/Memcopy: the CPY insns allow overlapping src/dest and
|
|
|
|
|
# copy in the correct direction; the CPYF insns always copy forwards.
|
|
|
|
|
#
|
|
|
|
|
# options has the nontemporal and unpriv bits for src and dest
|
|
|
|
|
&cpy rs rn rd options
|
|
|
|
|
@cpy .. ... . ..... rs:5 options:4 .. rn:5 rd:5 &cpy
|
|
|
|
|
|
|
|
|
|
CPYFP 00 011 0 01000 ..... .... 01 ..... ..... @cpy
|
|
|
|
|
CPYFM 00 011 0 01010 ..... .... 01 ..... ..... @cpy
|
|
|
|
|
CPYFE 00 011 0 01100 ..... .... 01 ..... ..... @cpy
|
|
|
|
|
CPYP 00 011 1 01000 ..... .... 01 ..... ..... @cpy
|
|
|
|
|
CPYM 00 011 1 01010 ..... .... 01 ..... ..... @cpy
|
|
|
|
|
CPYE 00 011 1 01100 ..... .... 01 ..... ..... @cpy
|
2024-05-25 02:20:23 +03:00
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### Cryptographic AES
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AESE 01001110 00 10100 00100 10 ..... ..... @r2r_q1e0
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AESD 01001110 00 10100 00101 10 ..... ..... @r2r_q1e0
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AESMC 01001110 00 10100 00110 10 ..... ..... @rr_q1e0
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AESIMC 01001110 00 10100 00111 10 ..... ..... @rr_q1e0
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2024-05-25 02:20:24 +03:00
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### Cryptographic three-register SHA
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SHA1C 0101 1110 000 ..... 000000 ..... ..... @rrr_q1e0
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SHA1P 0101 1110 000 ..... 000100 ..... ..... @rrr_q1e0
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SHA1M 0101 1110 000 ..... 001000 ..... ..... @rrr_q1e0
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SHA1SU0 0101 1110 000 ..... 001100 ..... ..... @rrr_q1e0
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SHA256H 0101 1110 000 ..... 010000 ..... ..... @rrr_q1e0
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SHA256H2 0101 1110 000 ..... 010100 ..... ..... @rrr_q1e0
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SHA256SU1 0101 1110 000 ..... 011000 ..... ..... @rrr_q1e0
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2024-05-25 02:20:25 +03:00
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### Cryptographic two-register SHA
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SHA1H 0101 1110 0010 1000 0000 10 ..... ..... @rr_q1e0
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SHA1SU1 0101 1110 0010 1000 0001 10 ..... ..... @rr_q1e0
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SHA256SU0 0101 1110 0010 1000 0010 10 ..... ..... @rr_q1e0
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2024-05-25 02:20:26 +03:00
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### Cryptographic three-register SHA512
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SHA512H 1100 1110 011 ..... 100000 ..... ..... @rrr_q1e0
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SHA512H2 1100 1110 011 ..... 100001 ..... ..... @rrr_q1e0
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SHA512SU1 1100 1110 011 ..... 100010 ..... ..... @rrr_q1e0
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RAX1 1100 1110 011 ..... 100011 ..... ..... @rrr_q1e3
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SM3PARTW1 1100 1110 011 ..... 110000 ..... ..... @rrr_q1e0
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SM3PARTW2 1100 1110 011 ..... 110001 ..... ..... @rrr_q1e0
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SM4EKEY 1100 1110 011 ..... 110010 ..... ..... @rrr_q1e0
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2024-05-25 02:20:27 +03:00
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### Cryptographic two-register SHA512
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SHA512SU0 1100 1110 110 00000 100000 ..... ..... @rr_q1e0
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SM4E 1100 1110 110 00000 100001 ..... ..... @r2r_q1e0
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2024-05-25 02:20:28 +03:00
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### Cryptographic four-register
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EOR3 1100 1110 000 ..... 0 ..... ..... ..... @rrrr_q1e3
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BCAX 1100 1110 001 ..... 0 ..... ..... ..... @rrrr_q1e3
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SM3SS1 1100 1110 010 ..... 0 ..... ..... ..... @rrrr_q1e3
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2024-05-25 02:20:29 +03:00
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### Cryptographic three-register, imm2
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&crypto3i rd rn rm imm
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@crypto3i ........ ... rm:5 .. imm:2 .. rn:5 rd:5 &crypto3i
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SM3TT1A 11001110 010 ..... 10 .. 00 ..... ..... @crypto3i
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SM3TT1B 11001110 010 ..... 10 .. 01 ..... ..... @crypto3i
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SM3TT2A 11001110 010 ..... 10 .. 10 ..... ..... @crypto3i
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SM3TT2B 11001110 010 ..... 10 .. 11 ..... ..... @crypto3i
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2024-05-25 02:20:30 +03:00
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### Cryptographic XAR
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XAR 1100 1110 100 rm:5 imm:6 rn:5 rd:5
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2024-05-25 02:20:31 +03:00
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### Advanced SIMD scalar copy
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DUP_element_s 0101 1110 000 imm:5 0 0000 1 rn:5 rd:5
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### Advanced SIMD copy
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DUP_element_v 0 q:1 00 1110 000 imm:5 0 0000 1 rn:5 rd:5
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DUP_general 0 q:1 00 1110 000 imm:5 0 0001 1 rn:5 rd:5
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INS_general 0 1 00 1110 000 imm:5 0 0011 1 rn:5 rd:5
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SMOV 0 q:1 00 1110 000 imm:5 0 0101 1 rn:5 rd:5
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UMOV 0 q:1 00 1110 000 imm:5 0 0111 1 rn:5 rd:5
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INS_element 0 1 10 1110 000 di:5 0 si:4 1 rn:5 rd:5
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2024-05-25 02:20:32 +03:00
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### Advanced SIMD scalar three same
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2024-05-25 02:20:33 +03:00
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FADD_s 0001 1110 ..1 ..... 0010 10 ..... ..... @rrr_hsd
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FSUB_s 0001 1110 ..1 ..... 0011 10 ..... ..... @rrr_hsd
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FDIV_s 0001 1110 ..1 ..... 0001 10 ..... ..... @rrr_hsd
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FMUL_s 0001 1110 ..1 ..... 0000 10 ..... ..... @rrr_hsd
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2024-05-25 02:20:37 +03:00
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FNMUL_s 0001 1110 ..1 ..... 1000 10 ..... ..... @rrr_hsd
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2024-05-25 02:20:33 +03:00
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2024-05-25 02:20:34 +03:00
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FMAX_s 0001 1110 ..1 ..... 0100 10 ..... ..... @rrr_hsd
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FMIN_s 0001 1110 ..1 ..... 0101 10 ..... ..... @rrr_hsd
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FMAXNM_s 0001 1110 ..1 ..... 0110 10 ..... ..... @rrr_hsd
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FMINNM_s 0001 1110 ..1 ..... 0111 10 ..... ..... @rrr_hsd
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2024-05-25 02:20:32 +03:00
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FMULX_s 0101 1110 010 ..... 00011 1 ..... ..... @rrr_h
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FMULX_s 0101 1110 0.1 ..... 11011 1 ..... ..... @rrr_sd
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2024-05-25 02:20:39 +03:00
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FCMEQ_s 0101 1110 010 ..... 00100 1 ..... ..... @rrr_h
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FCMEQ_s 0101 1110 0.1 ..... 11100 1 ..... ..... @rrr_sd
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FCMGE_s 0111 1110 010 ..... 00100 1 ..... ..... @rrr_h
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FCMGE_s 0111 1110 0.1 ..... 11100 1 ..... ..... @rrr_sd
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FCMGT_s 0111 1110 110 ..... 00100 1 ..... ..... @rrr_h
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FCMGT_s 0111 1110 1.1 ..... 11100 1 ..... ..... @rrr_sd
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FACGE_s 0111 1110 010 ..... 00101 1 ..... ..... @rrr_h
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FACGE_s 0111 1110 0.1 ..... 11101 1 ..... ..... @rrr_sd
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FACGT_s 0111 1110 110 ..... 00101 1 ..... ..... @rrr_h
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FACGT_s 0111 1110 1.1 ..... 11101 1 ..... ..... @rrr_sd
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2024-05-25 02:20:40 +03:00
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FABD_s 0111 1110 110 ..... 00010 1 ..... ..... @rrr_h
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FABD_s 0111 1110 1.1 ..... 11010 1 ..... ..... @rrr_sd
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2024-05-25 02:20:41 +03:00
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FRECPS_s 0101 1110 010 ..... 00111 1 ..... ..... @rrr_h
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FRECPS_s 0101 1110 0.1 ..... 11111 1 ..... ..... @rrr_sd
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FRSQRTS_s 0101 1110 110 ..... 00111 1 ..... ..... @rrr_h
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FRSQRTS_s 0101 1110 1.1 ..... 11111 1 ..... ..... @rrr_sd
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2024-05-28 23:30:18 +03:00
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SQADD_s 0101 1110 ..1 ..... 00001 1 ..... ..... @rrr_e
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UQADD_s 0111 1110 ..1 ..... 00001 1 ..... ..... @rrr_e
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SQSUB_s 0101 1110 ..1 ..... 00101 1 ..... ..... @rrr_e
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UQSUB_s 0111 1110 ..1 ..... 00101 1 ..... ..... @rrr_e
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2024-05-28 23:30:19 +03:00
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SUQADD_s 0101 1110 ..1 00000 00111 0 ..... ..... @r2r_e
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USQADD_s 0111 1110 ..1 00000 00111 0 ..... ..... @r2r_e
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2024-05-28 23:30:20 +03:00
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SSHL_s 0101 1110 111 ..... 01000 1 ..... ..... @rrr_d
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USHL_s 0111 1110 111 ..... 01000 1 ..... ..... @rrr_d
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2024-05-28 23:30:22 +03:00
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SRSHL_s 0101 1110 111 ..... 01010 1 ..... ..... @rrr_d
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URSHL_s 0111 1110 111 ..... 01010 1 ..... ..... @rrr_d
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2024-05-28 23:30:24 +03:00
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SQSHL_s 0101 1110 ..1 ..... 01001 1 ..... ..... @rrr_e
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UQSHL_s 0111 1110 ..1 ..... 01001 1 ..... ..... @rrr_e
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2024-05-28 23:30:26 +03:00
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SQRSHL_s 0101 1110 ..1 ..... 01011 1 ..... ..... @rrr_e
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UQRSHL_s 0111 1110 ..1 ..... 01011 1 ..... ..... @rrr_e
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2024-05-28 23:30:20 +03:00
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2024-05-28 23:30:27 +03:00
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ADD_s 0101 1110 111 ..... 10000 1 ..... ..... @rrr_d
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SUB_s 0111 1110 111 ..... 10000 1 ..... ..... @rrr_d
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2024-05-25 02:20:42 +03:00
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### Advanced SIMD scalar pairwise
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FADDP_s 0101 1110 0011 0000 1101 10 ..... ..... @rr_h
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FADDP_s 0111 1110 0.11 0000 1101 10 ..... ..... @rr_sd
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2024-05-25 02:20:43 +03:00
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FMAXP_s 0101 1110 0011 0000 1111 10 ..... ..... @rr_h
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FMAXP_s 0111 1110 0.11 0000 1111 10 ..... ..... @rr_sd
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FMINP_s 0101 1110 1011 0000 1111 10 ..... ..... @rr_h
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FMINP_s 0111 1110 1.11 0000 1111 10 ..... ..... @rr_sd
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FMAXNMP_s 0101 1110 0011 0000 1100 10 ..... ..... @rr_h
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FMAXNMP_s 0111 1110 0.11 0000 1100 10 ..... ..... @rr_sd
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FMINNMP_s 0101 1110 1011 0000 1100 10 ..... ..... @rr_h
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FMINNMP_s 0111 1110 1.11 0000 1100 10 ..... ..... @rr_sd
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2024-05-25 02:20:45 +03:00
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ADDP_s 0101 1110 1111 0001 1011 10 ..... ..... @rr_d
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2024-05-25 02:20:32 +03:00
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### Advanced SIMD three same
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2024-05-25 02:20:33 +03:00
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FADD_v 0.00 1110 010 ..... 00010 1 ..... ..... @qrrr_h
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FADD_v 0.00 1110 0.1 ..... 11010 1 ..... ..... @qrrr_sd
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FSUB_v 0.00 1110 110 ..... 00010 1 ..... ..... @qrrr_h
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FSUB_v 0.00 1110 1.1 ..... 11010 1 ..... ..... @qrrr_sd
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FDIV_v 0.10 1110 010 ..... 00111 1 ..... ..... @qrrr_h
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FDIV_v 0.10 1110 0.1 ..... 11111 1 ..... ..... @qrrr_sd
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FMUL_v 0.10 1110 010 ..... 00011 1 ..... ..... @qrrr_h
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FMUL_v 0.10 1110 0.1 ..... 11011 1 ..... ..... @qrrr_sd
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2024-05-25 02:20:34 +03:00
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FMAX_v 0.00 1110 010 ..... 00110 1 ..... ..... @qrrr_h
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FMAX_v 0.00 1110 0.1 ..... 11110 1 ..... ..... @qrrr_sd
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FMIN_v 0.00 1110 110 ..... 00110 1 ..... ..... @qrrr_h
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FMIN_v 0.00 1110 1.1 ..... 11110 1 ..... ..... @qrrr_sd
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FMAXNM_v 0.00 1110 010 ..... 00000 1 ..... ..... @qrrr_h
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FMAXNM_v 0.00 1110 0.1 ..... 11000 1 ..... ..... @qrrr_sd
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FMINNM_v 0.00 1110 110 ..... 00000 1 ..... ..... @qrrr_h
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FMINNM_v 0.00 1110 1.1 ..... 11000 1 ..... ..... @qrrr_sd
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2024-05-25 02:20:32 +03:00
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FMULX_v 0.00 1110 010 ..... 00011 1 ..... ..... @qrrr_h
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FMULX_v 0.00 1110 0.1 ..... 11011 1 ..... ..... @qrrr_sd
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2024-05-25 02:20:38 +03:00
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FMLA_v 0.00 1110 010 ..... 00001 1 ..... ..... @qrrr_h
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FMLA_v 0.00 1110 0.1 ..... 11001 1 ..... ..... @qrrr_sd
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FMLS_v 0.00 1110 110 ..... 00001 1 ..... ..... @qrrr_h
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FMLS_v 0.00 1110 1.1 ..... 11001 1 ..... ..... @qrrr_sd
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2024-05-25 02:20:49 +03:00
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FMLAL_v 0.00 1110 001 ..... 11101 1 ..... ..... @qrrr_h
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FMLSL_v 0.00 1110 101 ..... 11101 1 ..... ..... @qrrr_h
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FMLAL2_v 0.10 1110 001 ..... 11001 1 ..... ..... @qrrr_h
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FMLSL2_v 0.10 1110 101 ..... 11001 1 ..... ..... @qrrr_h
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2024-05-25 02:20:39 +03:00
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FCMEQ_v 0.00 1110 010 ..... 00100 1 ..... ..... @qrrr_h
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FCMEQ_v 0.00 1110 0.1 ..... 11100 1 ..... ..... @qrrr_sd
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FCMGE_v 0.10 1110 010 ..... 00100 1 ..... ..... @qrrr_h
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FCMGE_v 0.10 1110 0.1 ..... 11100 1 ..... ..... @qrrr_sd
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FCMGT_v 0.10 1110 110 ..... 00100 1 ..... ..... @qrrr_h
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FCMGT_v 0.10 1110 1.1 ..... 11100 1 ..... ..... @qrrr_sd
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FACGE_v 0.10 1110 010 ..... 00101 1 ..... ..... @qrrr_h
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FACGE_v 0.10 1110 0.1 ..... 11101 1 ..... ..... @qrrr_sd
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FACGT_v 0.10 1110 110 ..... 00101 1 ..... ..... @qrrr_h
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FACGT_v 0.10 1110 1.1 ..... 11101 1 ..... ..... @qrrr_sd
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2024-05-25 02:20:40 +03:00
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FABD_v 0.10 1110 110 ..... 00010 1 ..... ..... @qrrr_h
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FABD_v 0.10 1110 1.1 ..... 11010 1 ..... ..... @qrrr_sd
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2024-05-25 02:20:41 +03:00
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FRECPS_v 0.00 1110 010 ..... 00111 1 ..... ..... @qrrr_h
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FRECPS_v 0.00 1110 0.1 ..... 11111 1 ..... ..... @qrrr_sd
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FRSQRTS_v 0.00 1110 110 ..... 00111 1 ..... ..... @qrrr_h
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FRSQRTS_v 0.00 1110 1.1 ..... 11111 1 ..... ..... @qrrr_sd
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2024-05-25 02:20:42 +03:00
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FADDP_v 0.10 1110 010 ..... 00010 1 ..... ..... @qrrr_h
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FADDP_v 0.10 1110 0.1 ..... 11010 1 ..... ..... @qrrr_sd
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2024-05-25 02:20:43 +03:00
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FMAXP_v 0.10 1110 010 ..... 00110 1 ..... ..... @qrrr_h
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FMAXP_v 0.10 1110 0.1 ..... 11110 1 ..... ..... @qrrr_sd
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FMINP_v 0.10 1110 110 ..... 00110 1 ..... ..... @qrrr_h
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FMINP_v 0.10 1110 1.1 ..... 11110 1 ..... ..... @qrrr_sd
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FMAXNMP_v 0.10 1110 010 ..... 00000 1 ..... ..... @qrrr_h
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FMAXNMP_v 0.10 1110 0.1 ..... 11000 1 ..... ..... @qrrr_sd
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FMINNMP_v 0.10 1110 110 ..... 00000 1 ..... ..... @qrrr_h
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FMINNMP_v 0.10 1110 1.1 ..... 11000 1 ..... ..... @qrrr_sd
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2024-05-25 02:20:45 +03:00
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ADDP_v 0.00 1110 ..1 ..... 10111 1 ..... ..... @qrrr_e
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2024-05-25 02:20:47 +03:00
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SMAXP_v 0.00 1110 ..1 ..... 10100 1 ..... ..... @qrrr_e
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SMINP_v 0.00 1110 ..1 ..... 10101 1 ..... ..... @qrrr_e
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UMAXP_v 0.10 1110 ..1 ..... 10100 1 ..... ..... @qrrr_e
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UMINP_v 0.10 1110 ..1 ..... 10101 1 ..... ..... @qrrr_e
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2024-05-25 02:20:45 +03:00
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2024-05-25 02:20:50 +03:00
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AND_v 0.00 1110 001 ..... 00011 1 ..... ..... @qrrr_b
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BIC_v 0.00 1110 011 ..... 00011 1 ..... ..... @qrrr_b
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ORR_v 0.00 1110 101 ..... 00011 1 ..... ..... @qrrr_b
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ORN_v 0.00 1110 111 ..... 00011 1 ..... ..... @qrrr_b
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EOR_v 0.10 1110 001 ..... 00011 1 ..... ..... @qrrr_b
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BSL_v 0.10 1110 011 ..... 00011 1 ..... ..... @qrrr_b
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BIT_v 0.10 1110 101 ..... 00011 1 ..... ..... @qrrr_b
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BIF_v 0.10 1110 111 ..... 00011 1 ..... ..... @qrrr_b
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2024-05-28 23:30:18 +03:00
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SQADD_v 0.00 1110 ..1 ..... 00001 1 ..... ..... @qrrr_e
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UQADD_v 0.10 1110 ..1 ..... 00001 1 ..... ..... @qrrr_e
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SQSUB_v 0.00 1110 ..1 ..... 00101 1 ..... ..... @qrrr_e
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UQSUB_v 0.10 1110 ..1 ..... 00101 1 ..... ..... @qrrr_e
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2024-05-28 23:30:19 +03:00
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SUQADD_v 0.00 1110 ..1 00000 00111 0 ..... ..... @qr2r_e
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USQADD_v 0.10 1110 ..1 00000 00111 0 ..... ..... @qr2r_e
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2024-05-28 23:30:20 +03:00
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SSHL_v 0.00 1110 ..1 ..... 01000 1 ..... ..... @qrrr_e
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USHL_v 0.10 1110 ..1 ..... 01000 1 ..... ..... @qrrr_e
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2024-05-28 23:30:22 +03:00
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SRSHL_v 0.00 1110 ..1 ..... 01010 1 ..... ..... @qrrr_e
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URSHL_v 0.10 1110 ..1 ..... 01010 1 ..... ..... @qrrr_e
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2024-05-28 23:30:24 +03:00
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SQSHL_v 0.00 1110 ..1 ..... 01001 1 ..... ..... @qrrr_e
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UQSHL_v 0.10 1110 ..1 ..... 01001 1 ..... ..... @qrrr_e
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2024-05-28 23:30:26 +03:00
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SQRSHL_v 0.00 1110 ..1 ..... 01011 1 ..... ..... @qrrr_e
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UQRSHL_v 0.10 1110 ..1 ..... 01011 1 ..... ..... @qrrr_e
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2024-05-28 23:30:20 +03:00
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2024-05-28 23:30:27 +03:00
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ADD_v 0.00 1110 ..1 ..... 10000 1 ..... ..... @qrrr_e
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SUB_v 0.10 1110 ..1 ..... 10000 1 ..... ..... @qrrr_e
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2024-05-25 02:20:32 +03:00
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### Advanced SIMD scalar x indexed element
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2024-05-25 02:20:33 +03:00
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FMUL_si 0101 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h
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FMUL_si 0101 1111 10 . ..... 1001 . 0 ..... ..... @rrx_s
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FMUL_si 0101 1111 11 0 ..... 1001 . 0 ..... ..... @rrx_d
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2024-05-25 02:20:38 +03:00
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FMLA_si 0101 1111 00 .. .... 0001 . 0 ..... ..... @rrx_h
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FMLA_si 0101 1111 10 .. .... 0001 . 0 ..... ..... @rrx_s
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FMLA_si 0101 1111 11 0. .... 0001 . 0 ..... ..... @rrx_d
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FMLS_si 0101 1111 00 .. .... 0101 . 0 ..... ..... @rrx_h
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FMLS_si 0101 1111 10 .. .... 0101 . 0 ..... ..... @rrx_s
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FMLS_si 0101 1111 11 0. .... 0101 . 0 ..... ..... @rrx_d
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2024-05-25 02:20:32 +03:00
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FMULX_si 0111 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h
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FMULX_si 0111 1111 10 . ..... 1001 . 0 ..... ..... @rrx_s
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FMULX_si 0111 1111 11 0 ..... 1001 . 0 ..... ..... @rrx_d
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### Advanced SIMD vector x indexed element
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2024-05-25 02:20:33 +03:00
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FMUL_vi 0.00 1111 00 .. .... 1001 . 0 ..... ..... @qrrx_h
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FMUL_vi 0.00 1111 10 . ..... 1001 . 0 ..... ..... @qrrx_s
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FMUL_vi 0.00 1111 11 0 ..... 1001 . 0 ..... ..... @qrrx_d
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2024-05-25 02:20:38 +03:00
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FMLA_vi 0.00 1111 00 .. .... 0001 . 0 ..... ..... @qrrx_h
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FMLA_vi 0.00 1111 10 . ..... 0001 . 0 ..... ..... @qrrx_s
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FMLA_vi 0.00 1111 11 0 ..... 0001 . 0 ..... ..... @qrrx_d
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FMLS_vi 0.00 1111 00 .. .... 0101 . 0 ..... ..... @qrrx_h
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FMLS_vi 0.00 1111 10 . ..... 0101 . 0 ..... ..... @qrrx_s
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FMLS_vi 0.00 1111 11 0 ..... 0101 . 0 ..... ..... @qrrx_d
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2024-05-25 02:20:32 +03:00
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FMULX_vi 0.10 1111 00 .. .... 1001 . 0 ..... ..... @qrrx_h
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FMULX_vi 0.10 1111 10 . ..... 1001 . 0 ..... ..... @qrrx_s
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FMULX_vi 0.10 1111 11 0 ..... 1001 . 0 ..... ..... @qrrx_d
|
2024-05-25 02:20:49 +03:00
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FMLAL_vi 0.00 1111 10 .. .... 0000 . 0 ..... ..... @qrrx_h
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FMLSL_vi 0.00 1111 10 .. .... 0100 . 0 ..... ..... @qrrx_h
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FMLAL2_vi 0.10 1111 10 .. .... 1000 . 0 ..... ..... @qrrx_h
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FMLSL2_vi 0.10 1111 10 .. .... 1100 . 0 ..... ..... @qrrx_h
|
