2007-09-17 01:08:06 +04:00
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/*
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2006-04-09 05:32:52 +04:00
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* Arm PrimeCell PL011 UART
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*
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* Copyright (c) 2006 CodeSourcery.
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* Written by Paul Brook
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*
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2011-06-26 06:21:35 +04:00
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* This code is licensed under the GPL.
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2006-04-09 05:32:52 +04:00
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*/
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2016-01-26 21:17:05 +03:00
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#include "qemu/osdep.h"
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2013-02-04 18:40:22 +04:00
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#include "hw/sysbus.h"
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2013-04-08 18:55:25 +04:00
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#include "sysemu/char.h"
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2015-12-15 15:16:16 +03:00
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#include "qemu/log.h"
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2016-10-12 20:54:36 +03:00
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#include "trace.h"
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2006-04-09 05:32:52 +04:00
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2013-07-25 01:29:17 +04:00
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#define TYPE_PL011 "pl011"
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#define PL011(obj) OBJECT_CHECK(PL011State, (obj), TYPE_PL011)
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2013-07-25 01:13:57 +04:00
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typedef struct PL011State {
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2013-07-25 01:29:17 +04:00
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SysBusDevice parent_obj;
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2011-10-10 19:08:49 +04:00
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MemoryRegion iomem;
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2006-04-09 05:32:52 +04:00
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uint32_t readbuff;
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uint32_t flags;
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uint32_t lcr;
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2014-03-18 22:18:40 +04:00
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uint32_t rsr;
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2006-04-09 05:32:52 +04:00
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uint32_t cr;
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uint32_t dmacr;
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uint32_t int_enabled;
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uint32_t int_level;
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uint32_t read_fifo[16];
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uint32_t ilpr;
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uint32_t ibrd;
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uint32_t fbrd;
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uint32_t ifl;
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int read_pos;
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int read_count;
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int read_trigger;
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2016-10-22 12:52:51 +03:00
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CharBackend chr;
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2007-04-07 22:14:41 +04:00
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qemu_irq irq;
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2009-05-15 01:35:07 +04:00
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const unsigned char *id;
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2013-07-25 01:13:57 +04:00
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} PL011State;
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2006-04-09 05:32:52 +04:00
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#define PL011_INT_TX 0x20
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#define PL011_INT_RX 0x10
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#define PL011_FLAG_TXFE 0x80
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#define PL011_FLAG_RXFF 0x40
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#define PL011_FLAG_TXFF 0x20
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#define PL011_FLAG_RXFE 0x10
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2009-05-15 01:35:07 +04:00
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static const unsigned char pl011_id_arm[8] =
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{ 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
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static const unsigned char pl011_id_luminary[8] =
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{ 0x11, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 };
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2006-04-09 05:32:52 +04:00
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2013-07-25 01:13:57 +04:00
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static void pl011_update(PL011State *s)
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2006-04-09 05:32:52 +04:00
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{
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uint32_t flags;
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2007-09-17 12:09:54 +04:00
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2006-04-09 05:32:52 +04:00
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flags = s->int_level & s->int_enabled;
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2016-10-12 20:54:36 +03:00
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trace_pl011_irq_state(flags != 0);
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2007-04-07 22:14:41 +04:00
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qemu_set_irq(s->irq, flags != 0);
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2006-04-09 05:32:52 +04:00
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}
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2012-10-23 14:30:10 +04:00
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static uint64_t pl011_read(void *opaque, hwaddr offset,
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2011-10-10 19:08:49 +04:00
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unsigned size)
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2006-04-09 05:32:52 +04:00
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{
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2013-07-25 01:13:57 +04:00
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PL011State *s = (PL011State *)opaque;
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2006-04-09 05:32:52 +04:00
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uint32_t c;
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2016-10-12 20:54:36 +03:00
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uint64_t r;
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2006-04-09 05:32:52 +04:00
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switch (offset >> 2) {
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case 0: /* UARTDR */
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s->flags &= ~PL011_FLAG_RXFF;
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c = s->read_fifo[s->read_pos];
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if (s->read_count > 0) {
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s->read_count--;
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if (++s->read_pos == 16)
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s->read_pos = 0;
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}
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if (s->read_count == 0) {
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s->flags |= PL011_FLAG_RXFE;
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}
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if (s->read_count == s->read_trigger - 1)
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s->int_level &= ~ PL011_INT_RX;
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2016-10-12 20:54:36 +03:00
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trace_pl011_read_fifo(s->read_count);
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2014-03-18 22:18:40 +04:00
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s->rsr = c >> 8;
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2006-04-09 05:32:52 +04:00
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pl011_update(s);
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2016-10-22 12:52:59 +03:00
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qemu_chr_fe_accept_input(&s->chr);
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2016-10-12 20:54:36 +03:00
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r = c;
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break;
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2014-03-18 22:18:40 +04:00
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case 1: /* UARTRSR */
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2016-10-12 20:54:36 +03:00
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r = s->rsr;
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break;
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2006-04-09 05:32:52 +04:00
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case 6: /* UARTFR */
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2016-10-12 20:54:36 +03:00
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r = s->flags;
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break;
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2006-04-09 05:32:52 +04:00
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case 8: /* UARTILPR */
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2016-10-12 20:54:36 +03:00
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r = s->ilpr;
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break;
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2006-04-09 05:32:52 +04:00
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case 9: /* UARTIBRD */
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2016-10-12 20:54:36 +03:00
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r = s->ibrd;
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break;
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2006-04-09 05:32:52 +04:00
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case 10: /* UARTFBRD */
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2016-10-12 20:54:36 +03:00
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r = s->fbrd;
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break;
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2006-04-09 05:32:52 +04:00
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case 11: /* UARTLCR_H */
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2016-10-12 20:54:36 +03:00
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r = s->lcr;
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break;
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2006-04-09 05:32:52 +04:00
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case 12: /* UARTCR */
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2016-10-12 20:54:36 +03:00
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r = s->cr;
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break;
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2006-04-09 05:32:52 +04:00
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case 13: /* UARTIFLS */
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2016-10-12 20:54:36 +03:00
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r = s->ifl;
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break;
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2006-04-09 05:32:52 +04:00
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case 14: /* UARTIMSC */
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2016-10-12 20:54:36 +03:00
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r = s->int_enabled;
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break;
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2006-04-09 05:32:52 +04:00
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case 15: /* UARTRIS */
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2016-10-12 20:54:36 +03:00
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r = s->int_level;
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break;
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2006-04-09 05:32:52 +04:00
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case 16: /* UARTMIS */
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2016-10-12 20:54:36 +03:00
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r = s->int_level & s->int_enabled;
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break;
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2006-04-09 05:32:52 +04:00
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case 18: /* UARTDMACR */
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2016-10-12 20:54:36 +03:00
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r = s->dmacr;
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break;
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case 0x3f8 ... 0x400:
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r = s->id[(offset - 0xfe0) >> 2];
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break;
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2006-04-09 05:32:52 +04:00
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default:
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2012-10-18 17:11:40 +04:00
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qemu_log_mask(LOG_GUEST_ERROR,
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"pl011_read: Bad offset %x\n", (int)offset);
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2016-10-12 20:54:36 +03:00
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r = 0;
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break;
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2006-04-09 05:32:52 +04:00
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}
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2016-10-12 20:54:36 +03:00
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trace_pl011_read(offset, r);
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return r;
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2006-04-09 05:32:52 +04:00
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}
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2013-07-25 01:13:57 +04:00
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static void pl011_set_read_trigger(PL011State *s)
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2006-04-09 05:32:52 +04:00
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{
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#if 0
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/* The docs say the RX interrupt is triggered when the FIFO exceeds
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the threshold. However linux only reads the FIFO in response to an
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interrupt. Triggering the interrupt when the FIFO is non-empty seems
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to make things work. */
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if (s->lcr & 0x10)
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s->read_trigger = (s->ifl >> 1) & 0x1c;
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else
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#endif
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s->read_trigger = 1;
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}
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2012-10-23 14:30:10 +04:00
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static void pl011_write(void *opaque, hwaddr offset,
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2011-10-10 19:08:49 +04:00
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uint64_t value, unsigned size)
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2006-04-09 05:32:52 +04:00
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{
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2013-07-25 01:13:57 +04:00
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PL011State *s = (PL011State *)opaque;
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2006-04-09 05:32:52 +04:00
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unsigned char ch;
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2016-10-12 20:54:36 +03:00
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trace_pl011_write(offset, value);
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2006-04-09 05:32:52 +04:00
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switch (offset >> 2) {
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case 0: /* UARTDR */
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/* ??? Check if transmitter is enabled. */
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ch = value;
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2016-10-22 12:52:59 +03:00
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/* XXX this blocks entire thread. Rewrite to use
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* qemu_chr_fe_write and background I/O callbacks */
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qemu_chr_fe_write_all(&s->chr, &ch, 1);
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2006-04-09 05:32:52 +04:00
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s->int_level |= PL011_INT_TX;
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pl011_update(s);
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break;
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2014-03-18 22:18:40 +04:00
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case 1: /* UARTRSR/UARTECR */
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s->rsr = 0;
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2006-04-09 05:32:52 +04:00
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break;
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2007-11-11 03:04:49 +03:00
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case 6: /* UARTFR */
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/* Writes to Flag register are ignored. */
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break;
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2006-04-09 05:32:52 +04:00
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case 8: /* UARTUARTILPR */
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s->ilpr = value;
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break;
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case 9: /* UARTIBRD */
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s->ibrd = value;
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break;
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case 10: /* UARTFBRD */
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s->fbrd = value;
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break;
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case 11: /* UARTLCR_H */
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2014-03-18 22:18:39 +04:00
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/* Reset the FIFO state on FIFO enable or disable */
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if ((s->lcr ^ value) & 0x10) {
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s->read_count = 0;
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s->read_pos = 0;
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}
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2006-04-09 05:32:52 +04:00
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s->lcr = value;
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pl011_set_read_trigger(s);
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break;
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case 12: /* UARTCR */
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/* ??? Need to implement the enable and loopback bits. */
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s->cr = value;
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break;
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case 13: /* UARTIFS */
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s->ifl = value;
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pl011_set_read_trigger(s);
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break;
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case 14: /* UARTIMSC */
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s->int_enabled = value;
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pl011_update(s);
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break;
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case 17: /* UARTICR */
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s->int_level &= ~value;
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pl011_update(s);
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break;
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case 18: /* UARTDMACR */
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s->dmacr = value;
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2012-10-18 17:11:40 +04:00
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if (value & 3) {
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qemu_log_mask(LOG_UNIMP, "pl011: DMA not implemented\n");
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}
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2006-04-09 05:32:52 +04:00
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break;
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default:
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2012-10-18 17:11:40 +04:00
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qemu_log_mask(LOG_GUEST_ERROR,
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"pl011_write: Bad offset %x\n", (int)offset);
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2006-04-09 05:32:52 +04:00
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}
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}
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2007-07-12 02:48:58 +04:00
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static int pl011_can_receive(void *opaque)
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2006-04-09 05:32:52 +04:00
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{
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2013-07-25 01:13:57 +04:00
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PL011State *s = (PL011State *)opaque;
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2016-10-12 20:54:36 +03:00
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int r;
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2006-04-09 05:32:52 +04:00
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2016-10-12 20:54:36 +03:00
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if (s->lcr & 0x10) {
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r = s->read_count < 16;
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} else {
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r = s->read_count < 1;
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}
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trace_pl011_can_receive(s->lcr, s->read_count, r);
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return r;
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2006-04-09 05:32:52 +04:00
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}
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2008-04-08 23:51:43 +04:00
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static void pl011_put_fifo(void *opaque, uint32_t value)
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2006-04-09 05:32:52 +04:00
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{
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2013-07-25 01:13:57 +04:00
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PL011State *s = (PL011State *)opaque;
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2006-04-09 05:32:52 +04:00
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int slot;
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slot = s->read_pos + s->read_count;
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if (slot >= 16)
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slot -= 16;
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2008-04-08 23:51:43 +04:00
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s->read_fifo[slot] = value;
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2006-04-09 05:32:52 +04:00
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s->read_count++;
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s->flags &= ~PL011_FLAG_RXFE;
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2016-10-12 20:54:36 +03:00
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trace_pl011_put_fifo(value, s->read_count);
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2014-03-18 22:18:41 +04:00
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if (!(s->lcr & 0x10) || s->read_count == 16) {
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2016-10-12 20:54:36 +03:00
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trace_pl011_put_fifo_full();
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2006-04-09 05:32:52 +04:00
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s->flags |= PL011_FLAG_RXFF;
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}
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if (s->read_count == s->read_trigger) {
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s->int_level |= PL011_INT_RX;
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pl011_update(s);
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}
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}
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2008-04-08 23:51:43 +04:00
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static void pl011_receive(void *opaque, const uint8_t *buf, int size)
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{
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pl011_put_fifo(opaque, *buf);
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}
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2006-04-09 05:32:52 +04:00
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static void pl011_event(void *opaque, int event)
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{
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2008-04-08 23:51:43 +04:00
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if (event == CHR_EVENT_BREAK)
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pl011_put_fifo(opaque, 0x400);
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2006-04-09 05:32:52 +04:00
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}
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2011-10-10 19:08:49 +04:00
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static const MemoryRegionOps pl011_ops = {
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.read = pl011_read,
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.write = pl011_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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2006-04-09 05:32:52 +04:00
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};
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2010-12-02 03:50:33 +03:00
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static const VMStateDescription vmstate_pl011 = {
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.name = "pl011",
|
2014-03-18 22:18:40 +04:00
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.version_id = 2,
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.minimum_version_id = 2,
|
2014-05-13 19:09:35 +04:00
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.fields = (VMStateField[]) {
|
2013-07-25 01:13:57 +04:00
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VMSTATE_UINT32(readbuff, PL011State),
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VMSTATE_UINT32(flags, PL011State),
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VMSTATE_UINT32(lcr, PL011State),
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2014-03-18 22:18:40 +04:00
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VMSTATE_UINT32(rsr, PL011State),
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2013-07-25 01:13:57 +04:00
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VMSTATE_UINT32(cr, PL011State),
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|
|
VMSTATE_UINT32(dmacr, PL011State),
|
|
|
|
VMSTATE_UINT32(int_enabled, PL011State),
|
|
|
|
VMSTATE_UINT32(int_level, PL011State),
|
|
|
|
VMSTATE_UINT32_ARRAY(read_fifo, PL011State, 16),
|
|
|
|
VMSTATE_UINT32(ilpr, PL011State),
|
|
|
|
VMSTATE_UINT32(ibrd, PL011State),
|
|
|
|
VMSTATE_UINT32(fbrd, PL011State),
|
|
|
|
VMSTATE_UINT32(ifl, PL011State),
|
|
|
|
VMSTATE_INT32(read_pos, PL011State),
|
|
|
|
VMSTATE_INT32(read_count, PL011State),
|
|
|
|
VMSTATE_INT32(read_trigger, PL011State),
|
2010-12-02 03:50:33 +03:00
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
2008-07-02 20:48:32 +04:00
|
|
|
|
2016-06-06 18:59:31 +03:00
|
|
|
static Property pl011_properties[] = {
|
|
|
|
DEFINE_PROP_CHR("chardev", PL011State, chr),
|
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
};
|
|
|
|
|
2013-07-25 01:29:17 +04:00
|
|
|
static void pl011_init(Object *obj)
|
2006-04-09 05:32:52 +04:00
|
|
|
{
|
2013-07-25 01:29:17 +04:00
|
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
|
|
|
|
PL011State *s = PL011(obj);
|
2006-04-09 05:32:52 +04:00
|
|
|
|
2013-06-07 05:25:08 +04:00
|
|
|
memory_region_init_io(&s->iomem, OBJECT(s), &pl011_ops, s, "pl011", 0x1000);
|
2013-07-25 01:29:17 +04:00
|
|
|
sysbus_init_mmio(sbd, &s->iomem);
|
|
|
|
sysbus_init_irq(sbd, &s->irq);
|
2009-05-15 01:35:07 +04:00
|
|
|
|
2006-04-09 05:32:52 +04:00
|
|
|
s->read_trigger = 1;
|
|
|
|
s->ifl = 0x12;
|
|
|
|
s->cr = 0x300;
|
|
|
|
s->flags = 0x90;
|
2009-05-15 01:35:07 +04:00
|
|
|
|
2013-07-25 01:29:17 +04:00
|
|
|
s->id = pl011_id_arm;
|
2009-05-15 01:35:07 +04:00
|
|
|
}
|
|
|
|
|
2013-07-25 01:29:17 +04:00
|
|
|
static void pl011_realize(DeviceState *dev, Error **errp)
|
2009-05-15 01:35:07 +04:00
|
|
|
{
|
2013-07-25 01:29:17 +04:00
|
|
|
PL011State *s = PL011(dev);
|
|
|
|
|
2016-10-22 12:52:59 +03:00
|
|
|
qemu_chr_fe_set_handlers(&s->chr, pl011_can_receive, pl011_receive,
|
2016-10-22 12:53:03 +03:00
|
|
|
pl011_event, s, NULL, true);
|
2009-05-15 01:35:07 +04:00
|
|
|
}
|
|
|
|
|
2013-07-25 01:29:17 +04:00
|
|
|
static void pl011_class_init(ObjectClass *oc, void *data)
|
2012-01-24 23:12:29 +04:00
|
|
|
{
|
2013-07-25 01:29:17 +04:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2012-01-24 23:12:29 +04:00
|
|
|
|
2013-07-25 01:29:17 +04:00
|
|
|
dc->realize = pl011_realize;
|
|
|
|
dc->vmsd = &vmstate_pl011;
|
2016-06-06 18:59:31 +03:00
|
|
|
dc->props = pl011_properties;
|
2012-01-24 23:12:29 +04:00
|
|
|
}
|
|
|
|
|
2013-01-10 19:19:07 +04:00
|
|
|
static const TypeInfo pl011_arm_info = {
|
2013-07-25 01:29:17 +04:00
|
|
|
.name = TYPE_PL011,
|
2011-12-08 07:34:16 +04:00
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
2013-07-25 01:13:57 +04:00
|
|
|
.instance_size = sizeof(PL011State),
|
2013-07-25 01:29:17 +04:00
|
|
|
.instance_init = pl011_init,
|
|
|
|
.class_init = pl011_class_init,
|
2012-01-24 23:12:29 +04:00
|
|
|
};
|
|
|
|
|
2013-07-25 01:29:17 +04:00
|
|
|
static void pl011_luminary_init(Object *obj)
|
2012-01-24 23:12:29 +04:00
|
|
|
{
|
2013-07-25 01:29:17 +04:00
|
|
|
PL011State *s = PL011(obj);
|
2012-01-24 23:12:29 +04:00
|
|
|
|
2013-07-25 01:29:17 +04:00
|
|
|
s->id = pl011_id_luminary;
|
2012-01-24 23:12:29 +04:00
|
|
|
}
|
|
|
|
|
2013-01-10 19:19:07 +04:00
|
|
|
static const TypeInfo pl011_luminary_info = {
|
2011-12-08 07:34:16 +04:00
|
|
|
.name = "pl011_luminary",
|
2013-07-25 01:29:17 +04:00
|
|
|
.parent = TYPE_PL011,
|
|
|
|
.instance_init = pl011_luminary_init,
|
2012-01-24 23:12:29 +04:00
|
|
|
};
|
|
|
|
|
2012-02-09 18:20:55 +04:00
|
|
|
static void pl011_register_types(void)
|
2009-05-15 01:35:07 +04:00
|
|
|
{
|
2011-12-08 07:34:16 +04:00
|
|
|
type_register_static(&pl011_arm_info);
|
|
|
|
type_register_static(&pl011_luminary_info);
|
2009-05-15 01:35:07 +04:00
|
|
|
}
|
|
|
|
|
2012-02-09 18:20:55 +04:00
|
|
|
type_init(pl011_register_types)
|