2019-03-22 21:51:19 +03:00
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/*
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* Sparc cpu parameters for qemu.
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*
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* SPDX-License-Identifier: LGPL-2.0+
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*/
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#ifndef SPARC_CPU_PARAM_H
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2022-05-06 16:49:10 +03:00
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#define SPARC_CPU_PARAM_H
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2019-03-22 21:51:19 +03:00
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#ifdef TARGET_SPARC64
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# define TARGET_LONG_BITS 64
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# define TARGET_PAGE_BITS 13 /* 8k */
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# define TARGET_PHYS_ADDR_SPACE_BITS 41
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# ifdef TARGET_ABI32
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# define TARGET_VIRT_ADDR_SPACE_BITS 32
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# else
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# define TARGET_VIRT_ADDR_SPACE_BITS 44
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# endif
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#else
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# define TARGET_LONG_BITS 32
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# define TARGET_PAGE_BITS 12 /* 4k */
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# define TARGET_PHYS_ADDR_SPACE_BITS 36
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# define TARGET_VIRT_ADDR_SPACE_BITS 32
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#endif
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2023-12-05 16:31:59 +03:00
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/*
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* From Oracle SPARC Architecture 2015:
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*
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* Compatibility notes: The PSO memory model described in SPARC V8 and
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* SPARC V9 compatibility architecture specifications was never implemented
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* in a SPARC V9 implementation and is not included in the Oracle SPARC
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* Architecture specification.
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*
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* The RMO memory model described in the SPARC V9 specification was
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* implemented in some non-Sun SPARC V9 implementations, but is not
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* directly supported in Oracle SPARC Architecture 2015 implementations.
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*
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* Therefore always use TSO in QEMU.
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*
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* D.5 Specification of Partial Store Order (PSO)
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* ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore.
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*
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* D.6 Specification of Total Store Order (TSO)
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* ... PSO with the additional requirement that all [stores] are followed
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* by an implied MEMBAR #StoreStore.
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*/
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#define TCG_GUEST_DEFAULT_MO (TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST)
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2019-03-22 21:51:19 +03:00
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#endif
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