2007-01-16 02:58:11 +03:00
|
|
|
/*
|
|
|
|
* QEMU Malta board support
|
|
|
|
*
|
|
|
|
* Copyright (c) 2006 Aurelien Jarno
|
|
|
|
*
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|
|
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
|
|
|
* of this software and associated documentation files (the "Software"), to deal
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|
|
* in the Software without restriction, including without limitation the rights
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|
|
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
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|
|
* copies of the Software, and to permit persons to whom the Software is
|
|
|
|
* furnished to do so, subject to the following conditions:
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|
|
|
*
|
|
|
|
* The above copyright notice and this permission notice shall be included in
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|
* all copies or substantial portions of the Software.
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|
*
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|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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|
*/
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|
|
|
2016-01-18 20:35:00 +03:00
|
|
|
#include "qemu/osdep.h"
|
2018-06-25 15:42:22 +03:00
|
|
|
#include "qemu/units.h"
|
2020-12-05 01:16:45 +03:00
|
|
|
#include "qemu/bitops.h"
|
2020-10-28 14:36:57 +03:00
|
|
|
#include "qemu/datadir.h"
|
mips/malta: pass RNG seed via env var and re-randomize on reboot
As of the kernel commit linked below, Linux ingests an RNG seed
passed as part of the environment block by the bootloader or firmware.
This mechanism works across all different environment block types,
generically, which pass some block via the second firmware argument. On
malta, this has been tested to work when passed as an argument from
U-Boot's linux_env_set.
As is the case on most other architectures (such as boston), when
booting with `-kernel`, QEMU, acting as the bootloader, should pass the
RNG seed, so that the machine has good entropy for Linux to consume. So
this commit implements that quite simply by using the guest random API,
which is what is used on nearly all other archs too. It also
reinitializes the seed on reboot, so that it is always fresh.
Link: https://git.kernel.org/torvalds/c/056a68cea01
Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-10-25 20:28:43 +03:00
|
|
|
#include "qemu/guest-random.h"
|
2020-10-12 12:58:02 +03:00
|
|
|
#include "hw/clock.h"
|
2018-01-06 18:37:26 +03:00
|
|
|
#include "hw/southbridge/piix.h"
|
2018-03-09 01:39:37 +03:00
|
|
|
#include "hw/isa/superio.h"
|
2013-02-05 20:06:20 +04:00
|
|
|
#include "hw/char/serial.h"
|
2012-10-24 10:43:34 +04:00
|
|
|
#include "net/net.h"
|
2013-02-04 18:40:22 +04:00
|
|
|
#include "hw/boards.h"
|
2018-11-14 03:31:27 +03:00
|
|
|
#include "hw/i2c/smbus_eeprom.h"
|
2013-02-05 20:06:20 +04:00
|
|
|
#include "hw/block/flash.h"
|
|
|
|
#include "hw/mips/mips.h"
|
2022-10-26 22:18:20 +03:00
|
|
|
#include "hw/mips/bootloader.h"
|
2013-02-04 18:40:22 +04:00
|
|
|
#include "hw/pci/pci.h"
|
2023-01-09 20:23:19 +03:00
|
|
|
#include "hw/pci/pci_bus.h"
|
2012-12-17 21:20:00 +04:00
|
|
|
#include "qemu/log.h"
|
2022-10-22 18:04:53 +03:00
|
|
|
#include "hw/ide/pci.h"
|
2019-08-12 08:23:42 +03:00
|
|
|
#include "hw/irq.h"
|
2013-02-04 18:40:22 +04:00
|
|
|
#include "hw/loader.h"
|
2009-09-20 18:58:02 +04:00
|
|
|
#include "elf.h"
|
2020-09-03 23:43:22 +03:00
|
|
|
#include "qom/object.h"
|
2013-02-04 18:40:22 +04:00
|
|
|
#include "hw/sysbus.h" /* SysBusDevice */
|
2013-06-14 11:30:45 +04:00
|
|
|
#include "qemu/host-utils.h"
|
2013-07-29 18:05:31 +04:00
|
|
|
#include "sysemu/qtest.h"
|
2019-08-12 08:23:38 +03:00
|
|
|
#include "sysemu/reset.h"
|
2019-08-12 08:23:59 +03:00
|
|
|
#include "sysemu/runstate.h"
|
2018-02-01 14:18:31 +03:00
|
|
|
#include "qapi/error.h"
|
2013-08-03 18:03:18 +04:00
|
|
|
#include "qemu/error-report.h"
|
2014-06-18 02:10:35 +04:00
|
|
|
#include "sysemu/kvm.h"
|
2021-03-05 16:54:49 +03:00
|
|
|
#include "semihosting/semihost.h"
|
2016-03-15 12:59:35 +03:00
|
|
|
#include "hw/mips/cps.h"
|
2020-10-12 12:58:02 +03:00
|
|
|
#include "hw/qdev-clock.h"
|
2022-12-18 03:06:45 +03:00
|
|
|
#include "target/mips/internal.h"
|
2022-12-30 17:35:24 +03:00
|
|
|
#include "trace.h"
|
2023-11-22 17:34:58 +03:00
|
|
|
#include "cpu.h"
|
2007-01-16 02:58:11 +03:00
|
|
|
|
2020-12-15 09:41:55 +03:00
|
|
|
#define ENVP_PADDR 0x2000
|
|
|
|
#define ENVP_VADDR cpu_mips_phys_to_kseg0(NULL, ENVP_PADDR)
|
2019-08-19 15:07:54 +03:00
|
|
|
#define ENVP_NB_ENTRIES 16
|
|
|
|
#define ENVP_ENTRY_SIZE 256
|
2007-01-16 02:58:11 +03:00
|
|
|
|
2012-01-28 09:18:18 +04:00
|
|
|
/* Hardware addresses */
|
2019-08-19 15:07:54 +03:00
|
|
|
#define FLASH_ADDRESS 0x1e000000ULL
|
|
|
|
#define FPGA_ADDRESS 0x1f000000ULL
|
|
|
|
#define RESET_ADDRESS 0x1fc00000ULL
|
2012-01-28 09:18:18 +04:00
|
|
|
|
2019-08-19 15:07:54 +03:00
|
|
|
#define FLASH_SIZE 0x400000
|
2023-11-22 17:34:58 +03:00
|
|
|
#define BIOS_SIZE (4 * MiB)
|
2012-01-28 09:18:18 +04:00
|
|
|
|
2022-10-26 02:53:53 +03:00
|
|
|
#define PIIX4_PCI_DEVFN PCI_DEVFN(10, 0)
|
|
|
|
|
2007-01-16 02:58:11 +03:00
|
|
|
typedef struct {
|
2011-08-08 23:14:25 +04:00
|
|
|
MemoryRegion iomem;
|
|
|
|
MemoryRegion iomem_lo; /* 0 - 0x900 */
|
|
|
|
MemoryRegion iomem_hi; /* 0xa00 - 0x100000 */
|
2007-01-16 02:58:11 +03:00
|
|
|
uint32_t leds;
|
|
|
|
uint32_t brk;
|
|
|
|
uint32_t gpout;
|
2007-02-28 23:04:26 +03:00
|
|
|
uint32_t i2cin;
|
2007-01-16 02:58:11 +03:00
|
|
|
uint32_t i2coe;
|
|
|
|
uint32_t i2cout;
|
|
|
|
uint32_t i2csel;
|
2016-10-22 12:52:52 +03:00
|
|
|
CharBackend display;
|
2007-01-16 02:58:11 +03:00
|
|
|
char display_text[9];
|
2019-10-23 18:50:06 +03:00
|
|
|
SerialMM *uart;
|
2016-10-22 12:52:45 +03:00
|
|
|
bool display_inited;
|
2007-01-16 02:58:11 +03:00
|
|
|
} MaltaFPGAState;
|
|
|
|
|
2023-11-22 17:34:58 +03:00
|
|
|
#if TARGET_BIG_ENDIAN
|
|
|
|
#define BIOS_FILENAME "mips_bios.bin"
|
|
|
|
#else
|
|
|
|
#define BIOS_FILENAME "mipsel_bios.bin"
|
|
|
|
#endif
|
|
|
|
|
2013-07-28 00:19:54 +04:00
|
|
|
#define TYPE_MIPS_MALTA "mips-malta"
|
2020-09-16 21:25:19 +03:00
|
|
|
OBJECT_DECLARE_SIMPLE_TYPE(MaltaState, MIPS_MALTA)
|
2013-07-28 00:19:54 +04:00
|
|
|
|
2020-09-03 23:43:22 +03:00
|
|
|
struct MaltaState {
|
2013-07-28 00:19:54 +04:00
|
|
|
SysBusDevice parent_obj;
|
|
|
|
|
2020-10-12 12:58:02 +03:00
|
|
|
Clock *cpuclk;
|
2019-05-07 19:34:09 +03:00
|
|
|
MIPSCPSState cps;
|
2020-09-03 23:43:22 +03:00
|
|
|
};
|
2011-11-29 09:34:48 +04:00
|
|
|
|
2007-11-09 20:52:11 +03:00
|
|
|
static struct _loaderparams {
|
2015-05-25 16:21:04 +03:00
|
|
|
int ram_size, ram_low_size;
|
2007-11-09 20:52:11 +03:00
|
|
|
const char *kernel_filename;
|
|
|
|
const char *kernel_cmdline;
|
|
|
|
const char *initrd_filename;
|
|
|
|
} loaderparams;
|
|
|
|
|
2007-01-16 02:58:11 +03:00
|
|
|
/* Malta FPGA */
|
2022-12-30 17:35:24 +03:00
|
|
|
static void malta_fpga_update_display_leds(MaltaFPGAState *s)
|
2007-01-16 02:58:11 +03:00
|
|
|
{
|
|
|
|
char leds_text[9];
|
|
|
|
int i;
|
|
|
|
|
2007-06-22 03:38:12 +04:00
|
|
|
for (i = 7 ; i >= 0 ; i--) {
|
2019-08-19 15:07:54 +03:00
|
|
|
if (s->leds & (1 << i)) {
|
2007-06-22 03:38:12 +04:00
|
|
|
leds_text[i] = '#';
|
2019-08-19 15:07:54 +03:00
|
|
|
} else {
|
2007-06-22 03:38:12 +04:00
|
|
|
leds_text[i] = ' ';
|
2019-08-19 15:07:54 +03:00
|
|
|
}
|
2007-06-09 19:44:26 +04:00
|
|
|
}
|
2007-06-22 03:38:12 +04:00
|
|
|
leds_text[8] = '\0';
|
|
|
|
|
2022-12-30 17:35:24 +03:00
|
|
|
trace_malta_fpga_leds(leds_text);
|
2016-10-22 12:52:55 +03:00
|
|
|
qemu_chr_fe_printf(&s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n",
|
2016-10-22 12:52:52 +03:00
|
|
|
leds_text);
|
2022-12-30 17:35:24 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static void malta_fpga_update_display_ascii(MaltaFPGAState *s)
|
|
|
|
{
|
2022-12-30 17:35:24 +03:00
|
|
|
trace_malta_fpga_display(s->display_text);
|
2016-10-22 12:52:55 +03:00
|
|
|
qemu_chr_fe_printf(&s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|",
|
2016-10-22 12:52:52 +03:00
|
|
|
s->display_text);
|
2007-01-16 02:58:11 +03:00
|
|
|
}
|
|
|
|
|
2007-02-28 23:04:26 +03:00
|
|
|
/*
|
|
|
|
* EEPROM 24C01 / 24C02 emulation.
|
|
|
|
*
|
|
|
|
* Emulation for serial EEPROMs:
|
|
|
|
* 24C01 - 1024 bit (128 x 8)
|
|
|
|
* 24C02 - 2048 bit (256 x 8)
|
|
|
|
*
|
|
|
|
* Typical device names include Microchip 24C02SC or SGS Thomson ST24C02.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#if defined(DEBUG)
|
2019-12-06 16:58:04 +03:00
|
|
|
# define logout(fmt, ...) \
|
|
|
|
fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ## __VA_ARGS__)
|
2007-02-28 23:04:26 +03:00
|
|
|
#else
|
2009-05-13 21:53:17 +04:00
|
|
|
# define logout(fmt, ...) ((void)0)
|
2007-02-28 23:04:26 +03:00
|
|
|
#endif
|
|
|
|
|
2009-10-02 01:12:16 +04:00
|
|
|
struct _eeprom24c0x_t {
|
2007-02-28 23:04:26 +03:00
|
|
|
uint8_t tick;
|
|
|
|
uint8_t address;
|
|
|
|
uint8_t command;
|
|
|
|
uint8_t ack;
|
|
|
|
uint8_t scl;
|
|
|
|
uint8_t sda;
|
|
|
|
uint8_t data;
|
2019-08-19 15:07:54 +03:00
|
|
|
/* uint16_t size; */
|
2007-02-28 23:04:26 +03:00
|
|
|
uint8_t contents[256];
|
|
|
|
};
|
|
|
|
|
2009-10-02 01:12:16 +04:00
|
|
|
typedef struct _eeprom24c0x_t eeprom24c0x_t;
|
2007-02-28 23:04:26 +03:00
|
|
|
|
2013-06-14 11:30:47 +04:00
|
|
|
static eeprom24c0x_t spd_eeprom = {
|
2009-09-21 23:50:05 +04:00
|
|
|
.contents = {
|
2019-08-19 15:07:54 +03:00
|
|
|
/* 00000000: */
|
|
|
|
0x80, 0x08, 0xFF, 0x0D, 0x0A, 0xFF, 0x40, 0x00,
|
|
|
|
/* 00000008: */
|
|
|
|
0x01, 0x75, 0x54, 0x00, 0x82, 0x08, 0x00, 0x01,
|
|
|
|
/* 00000010: */
|
|
|
|
0x8F, 0x04, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00,
|
|
|
|
/* 00000018: */
|
|
|
|
0x00, 0x00, 0x00, 0x14, 0x0F, 0x14, 0x2D, 0xFF,
|
|
|
|
/* 00000020: */
|
|
|
|
0x15, 0x08, 0x15, 0x08, 0x00, 0x00, 0x00, 0x00,
|
|
|
|
/* 00000028: */
|
|
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
|
|
/* 00000030: */
|
|
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
|
|
/* 00000038: */
|
|
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0xD0,
|
|
|
|
/* 00000040: */
|
|
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
|
|
/* 00000048: */
|
|
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
|
|
/* 00000050: */
|
|
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
|
|
/* 00000058: */
|
|
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
|
|
/* 00000060: */
|
|
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
|
|
/* 00000068: */
|
|
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
|
|
/* 00000070: */
|
|
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
|
|
/* 00000078: */
|
|
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0xF4,
|
2007-02-28 23:04:26 +03:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2013-06-14 11:30:47 +04:00
|
|
|
static void generate_eeprom_spd(uint8_t *eeprom, ram_addr_t ram_size)
|
2013-06-14 11:30:45 +04:00
|
|
|
{
|
2023-10-09 11:21:22 +03:00
|
|
|
enum sdram_type type;
|
2013-06-14 11:30:47 +04:00
|
|
|
uint8_t *spd = spd_eeprom.contents;
|
2013-06-14 11:30:45 +04:00
|
|
|
uint8_t nbanks = 0;
|
|
|
|
uint16_t density = 0;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* work in terms of MB */
|
2018-06-25 15:42:22 +03:00
|
|
|
ram_size /= MiB;
|
2013-06-14 11:30:45 +04:00
|
|
|
|
|
|
|
while ((ram_size >= 4) && (nbanks <= 2)) {
|
|
|
|
int sz_log2 = MIN(31 - clz32(ram_size), 14);
|
|
|
|
nbanks++;
|
|
|
|
density |= 1 << (sz_log2 - 2);
|
|
|
|
ram_size -= 1 << sz_log2;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* split to 2 banks if possible */
|
|
|
|
if ((nbanks == 1) && (density > 1)) {
|
|
|
|
nbanks++;
|
|
|
|
density >>= 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (density & 0xff00) {
|
|
|
|
density = (density & 0xe0) | ((density >> 8) & 0x1f);
|
|
|
|
type = DDR2;
|
|
|
|
} else if (!(density & 0x1f)) {
|
|
|
|
type = DDR2;
|
|
|
|
} else {
|
|
|
|
type = SDR;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ram_size) {
|
2017-09-11 22:52:56 +03:00
|
|
|
warn_report("SPD cannot represent final " RAM_ADDR_FMT "MB"
|
|
|
|
" of SDRAM", ram_size);
|
2013-06-14 11:30:45 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
/* fill in SPD memory information */
|
|
|
|
spd[2] = type;
|
|
|
|
spd[5] = nbanks;
|
|
|
|
spd[31] = density;
|
|
|
|
|
|
|
|
/* checksum */
|
|
|
|
spd[63] = 0;
|
|
|
|
for (i = 0; i < 63; i++) {
|
|
|
|
spd[63] += spd[i];
|
|
|
|
}
|
2013-06-14 11:30:47 +04:00
|
|
|
|
|
|
|
/* copy for SMBUS */
|
|
|
|
memcpy(eeprom, spd, sizeof(spd_eeprom.contents));
|
|
|
|
}
|
|
|
|
|
|
|
|
static void generate_eeprom_serial(uint8_t *eeprom)
|
|
|
|
{
|
|
|
|
int i, pos = 0;
|
|
|
|
uint8_t mac[6] = { 0x00 };
|
|
|
|
uint8_t sn[5] = { 0x01, 0x23, 0x45, 0x67, 0x89 };
|
|
|
|
|
|
|
|
/* version */
|
|
|
|
eeprom[pos++] = 0x01;
|
|
|
|
|
|
|
|
/* count */
|
|
|
|
eeprom[pos++] = 0x02;
|
|
|
|
|
|
|
|
/* MAC address */
|
|
|
|
eeprom[pos++] = 0x01; /* MAC */
|
|
|
|
eeprom[pos++] = 0x06; /* length */
|
|
|
|
memcpy(&eeprom[pos], mac, sizeof(mac));
|
|
|
|
pos += sizeof(mac);
|
|
|
|
|
|
|
|
/* serial number */
|
|
|
|
eeprom[pos++] = 0x02; /* serial */
|
|
|
|
eeprom[pos++] = 0x05; /* length */
|
|
|
|
memcpy(&eeprom[pos], sn, sizeof(sn));
|
|
|
|
pos += sizeof(sn);
|
|
|
|
|
|
|
|
/* checksum */
|
|
|
|
eeprom[pos] = 0;
|
|
|
|
for (i = 0; i < pos; i++) {
|
|
|
|
eeprom[pos] += eeprom[i];
|
|
|
|
}
|
2013-06-14 11:30:45 +04:00
|
|
|
}
|
|
|
|
|
2013-06-14 11:30:47 +04:00
|
|
|
static uint8_t eeprom24c0x_read(eeprom24c0x_t *eeprom)
|
2007-02-28 23:04:26 +03:00
|
|
|
{
|
|
|
|
logout("%u: scl = %u, sda = %u, data = 0x%02x\n",
|
2013-06-14 11:30:47 +04:00
|
|
|
eeprom->tick, eeprom->scl, eeprom->sda, eeprom->data);
|
|
|
|
return eeprom->sda;
|
2007-02-28 23:04:26 +03:00
|
|
|
}
|
|
|
|
|
2013-06-14 11:30:47 +04:00
|
|
|
static void eeprom24c0x_write(eeprom24c0x_t *eeprom, int scl, int sda)
|
2007-02-28 23:04:26 +03:00
|
|
|
{
|
2013-06-14 11:30:47 +04:00
|
|
|
if (eeprom->scl && scl && (eeprom->sda != sda)) {
|
2007-02-28 23:04:26 +03:00
|
|
|
logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n",
|
2013-06-14 11:30:47 +04:00
|
|
|
eeprom->tick, eeprom->scl, scl, eeprom->sda, sda,
|
|
|
|
sda ? "stop" : "start");
|
2007-02-28 23:04:26 +03:00
|
|
|
if (!sda) {
|
2013-06-14 11:30:47 +04:00
|
|
|
eeprom->tick = 1;
|
|
|
|
eeprom->command = 0;
|
2007-02-28 23:04:26 +03:00
|
|
|
}
|
2013-06-14 11:30:47 +04:00
|
|
|
} else if (eeprom->tick == 0 && !eeprom->ack) {
|
2007-02-28 23:04:26 +03:00
|
|
|
/* Waiting for start. */
|
|
|
|
logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n",
|
2013-06-14 11:30:47 +04:00
|
|
|
eeprom->tick, eeprom->scl, scl, eeprom->sda, sda);
|
|
|
|
} else if (!eeprom->scl && scl) {
|
2007-02-28 23:04:26 +03:00
|
|
|
logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n",
|
2013-06-14 11:30:47 +04:00
|
|
|
eeprom->tick, eeprom->scl, scl, eeprom->sda, sda);
|
|
|
|
if (eeprom->ack) {
|
2007-02-28 23:04:26 +03:00
|
|
|
logout("\ti2c ack bit = 0\n");
|
|
|
|
sda = 0;
|
2013-06-14 11:30:47 +04:00
|
|
|
eeprom->ack = 0;
|
|
|
|
} else if (eeprom->sda == sda) {
|
2007-02-28 23:04:26 +03:00
|
|
|
uint8_t bit = (sda != 0);
|
|
|
|
logout("\ti2c bit = %d\n", bit);
|
2013-06-14 11:30:47 +04:00
|
|
|
if (eeprom->tick < 9) {
|
|
|
|
eeprom->command <<= 1;
|
|
|
|
eeprom->command += bit;
|
|
|
|
eeprom->tick++;
|
|
|
|
if (eeprom->tick == 9) {
|
|
|
|
logout("\tcommand 0x%04x, %s\n", eeprom->command,
|
|
|
|
bit ? "read" : "write");
|
|
|
|
eeprom->ack = 1;
|
2007-02-28 23:04:26 +03:00
|
|
|
}
|
2013-06-14 11:30:47 +04:00
|
|
|
} else if (eeprom->tick < 17) {
|
|
|
|
if (eeprom->command & 1) {
|
|
|
|
sda = ((eeprom->data & 0x80) != 0);
|
2007-02-28 23:04:26 +03:00
|
|
|
}
|
2013-06-14 11:30:47 +04:00
|
|
|
eeprom->address <<= 1;
|
|
|
|
eeprom->address += bit;
|
|
|
|
eeprom->tick++;
|
|
|
|
eeprom->data <<= 1;
|
|
|
|
if (eeprom->tick == 17) {
|
|
|
|
eeprom->data = eeprom->contents[eeprom->address];
|
|
|
|
logout("\taddress 0x%04x, data 0x%02x\n",
|
|
|
|
eeprom->address, eeprom->data);
|
|
|
|
eeprom->ack = 1;
|
|
|
|
eeprom->tick = 0;
|
2007-02-28 23:04:26 +03:00
|
|
|
}
|
2013-06-14 11:30:47 +04:00
|
|
|
} else if (eeprom->tick >= 17) {
|
2007-02-28 23:04:26 +03:00
|
|
|
sda = 0;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
logout("\tsda changed with raising scl\n");
|
|
|
|
}
|
|
|
|
} else {
|
2013-06-14 11:30:47 +04:00
|
|
|
logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom->tick, eeprom->scl,
|
|
|
|
scl, eeprom->sda, sda);
|
2007-02-28 23:04:26 +03:00
|
|
|
}
|
2013-06-14 11:30:47 +04:00
|
|
|
eeprom->scl = scl;
|
|
|
|
eeprom->sda = sda;
|
2007-02-28 23:04:26 +03:00
|
|
|
}
|
|
|
|
|
2012-10-23 14:30:10 +04:00
|
|
|
static uint64_t malta_fpga_read(void *opaque, hwaddr addr,
|
2011-08-08 23:14:25 +04:00
|
|
|
unsigned size)
|
2007-01-16 02:58:11 +03:00
|
|
|
{
|
|
|
|
MaltaFPGAState *s = opaque;
|
|
|
|
uint32_t val = 0;
|
|
|
|
uint32_t saddr;
|
|
|
|
|
|
|
|
saddr = (addr & 0xfffff);
|
|
|
|
|
|
|
|
switch (saddr) {
|
|
|
|
|
|
|
|
/* SWITCH Register */
|
|
|
|
case 0x00200:
|
2019-08-19 15:07:54 +03:00
|
|
|
val = 0x00000000;
|
2009-11-14 15:10:43 +03:00
|
|
|
break;
|
2007-01-16 02:58:11 +03:00
|
|
|
|
|
|
|
/* STATUS Register */
|
|
|
|
case 0x00208:
|
2022-03-23 18:57:18 +03:00
|
|
|
#if TARGET_BIG_ENDIAN
|
2007-01-16 02:58:11 +03:00
|
|
|
val = 0x00000012;
|
|
|
|
#else
|
|
|
|
val = 0x00000010;
|
|
|
|
#endif
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* JMPRS Register */
|
|
|
|
case 0x00210:
|
|
|
|
val = 0x00;
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* LEDBAR Register */
|
|
|
|
case 0x00408:
|
|
|
|
val = s->leds;
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* BRKRES Register */
|
|
|
|
case 0x00508:
|
|
|
|
val = s->brk;
|
|
|
|
break;
|
|
|
|
|
2007-06-04 22:29:37 +04:00
|
|
|
/* UART Registers are handled directly by the serial device */
|
2007-03-31 20:54:14 +04:00
|
|
|
|
2007-01-16 02:58:11 +03:00
|
|
|
/* GPOUT Register */
|
|
|
|
case 0x00a00:
|
|
|
|
val = s->gpout;
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* XXX: implement a real I2C controller */
|
|
|
|
|
|
|
|
/* GPINP Register */
|
|
|
|
case 0x00a08:
|
|
|
|
/* IN = OUT until a real I2C control is implemented */
|
2019-08-19 15:07:54 +03:00
|
|
|
if (s->i2csel) {
|
2007-01-16 02:58:11 +03:00
|
|
|
val = s->i2cout;
|
2019-08-19 15:07:54 +03:00
|
|
|
} else {
|
2007-01-16 02:58:11 +03:00
|
|
|
val = 0x00;
|
2019-08-19 15:07:54 +03:00
|
|
|
}
|
2007-01-16 02:58:11 +03:00
|
|
|
break;
|
|
|
|
|
|
|
|
/* I2CINP Register */
|
|
|
|
case 0x00b00:
|
2013-06-14 11:30:47 +04:00
|
|
|
val = ((s->i2cin & ~1) | eeprom24c0x_read(&spd_eeprom));
|
2007-01-16 02:58:11 +03:00
|
|
|
break;
|
|
|
|
|
|
|
|
/* I2COE Register */
|
|
|
|
case 0x00b08:
|
|
|
|
val = s->i2coe;
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* I2COUT Register */
|
|
|
|
case 0x00b10:
|
|
|
|
val = s->i2cout;
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* I2CSEL Register */
|
|
|
|
case 0x00b18:
|
2007-02-28 23:04:26 +03:00
|
|
|
val = s->i2csel;
|
2007-01-16 02:58:11 +03:00
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
2020-05-18 23:09:19 +03:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"malta_fpga_read: Bad register addr 0x%"HWADDR_PRIX"\n",
|
|
|
|
addr);
|
2007-01-16 02:58:11 +03:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
2012-10-23 14:30:10 +04:00
|
|
|
static void malta_fpga_write(void *opaque, hwaddr addr,
|
2011-08-08 23:14:25 +04:00
|
|
|
uint64_t val, unsigned size)
|
2007-01-16 02:58:11 +03:00
|
|
|
{
|
|
|
|
MaltaFPGAState *s = opaque;
|
|
|
|
uint32_t saddr;
|
|
|
|
|
|
|
|
saddr = (addr & 0xfffff);
|
|
|
|
|
|
|
|
switch (saddr) {
|
|
|
|
|
|
|
|
/* SWITCH Register */
|
|
|
|
case 0x00200:
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* JMPRS Register */
|
|
|
|
case 0x00210:
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* LEDBAR Register */
|
|
|
|
case 0x00408:
|
|
|
|
s->leds = val & 0xff;
|
2022-12-30 17:35:24 +03:00
|
|
|
malta_fpga_update_display_leds(s);
|
2007-01-16 02:58:11 +03:00
|
|
|
break;
|
|
|
|
|
|
|
|
/* ASCIIWORD Register */
|
|
|
|
case 0x00410:
|
2011-08-08 23:14:25 +04:00
|
|
|
snprintf(s->display_text, 9, "%08X", (uint32_t)val);
|
2022-12-30 17:35:24 +03:00
|
|
|
malta_fpga_update_display_ascii(s);
|
2007-01-16 02:58:11 +03:00
|
|
|
break;
|
|
|
|
|
|
|
|
/* ASCIIPOS0 to ASCIIPOS7 Registers */
|
|
|
|
case 0x00418:
|
|
|
|
case 0x00420:
|
|
|
|
case 0x00428:
|
|
|
|
case 0x00430:
|
|
|
|
case 0x00438:
|
|
|
|
case 0x00440:
|
|
|
|
case 0x00448:
|
|
|
|
case 0x00450:
|
|
|
|
s->display_text[(saddr - 0x00418) >> 3] = (char) val;
|
2022-12-30 17:35:24 +03:00
|
|
|
malta_fpga_update_display_ascii(s);
|
2007-01-16 02:58:11 +03:00
|
|
|
break;
|
|
|
|
|
|
|
|
/* SOFTRES Register */
|
|
|
|
case 0x00500:
|
2019-08-19 15:07:54 +03:00
|
|
|
if (val == 0x42) {
|
2017-05-16 00:41:13 +03:00
|
|
|
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
|
2019-08-19 15:07:54 +03:00
|
|
|
}
|
2007-01-16 02:58:11 +03:00
|
|
|
break;
|
|
|
|
|
|
|
|
/* BRKRES Register */
|
|
|
|
case 0x00508:
|
|
|
|
s->brk = val & 0xff;
|
|
|
|
break;
|
|
|
|
|
2007-06-04 22:29:37 +04:00
|
|
|
/* UART Registers are handled directly by the serial device */
|
2007-03-31 20:54:14 +04:00
|
|
|
|
2007-01-16 02:58:11 +03:00
|
|
|
/* GPOUT Register */
|
|
|
|
case 0x00a00:
|
|
|
|
s->gpout = val & 0xff;
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* I2COE Register */
|
|
|
|
case 0x00b08:
|
|
|
|
s->i2coe = val & 0x03;
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* I2COUT Register */
|
|
|
|
case 0x00b10:
|
2013-06-14 11:30:47 +04:00
|
|
|
eeprom24c0x_write(&spd_eeprom, val & 0x02, val & 0x01);
|
2007-02-28 23:04:26 +03:00
|
|
|
s->i2cout = val;
|
2007-01-16 02:58:11 +03:00
|
|
|
break;
|
|
|
|
|
|
|
|
/* I2CSEL Register */
|
|
|
|
case 0x00b18:
|
2007-02-28 23:04:26 +03:00
|
|
|
s->i2csel = val & 0x01;
|
2007-01-16 02:58:11 +03:00
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
2020-05-18 23:09:19 +03:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"malta_fpga_write: Bad register addr 0x%"HWADDR_PRIX"\n",
|
|
|
|
addr);
|
2007-01-16 02:58:11 +03:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-08-08 23:14:25 +04:00
|
|
|
static const MemoryRegionOps malta_fpga_ops = {
|
|
|
|
.read = malta_fpga_read,
|
|
|
|
.write = malta_fpga_write,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
2007-01-16 02:58:11 +03:00
|
|
|
};
|
|
|
|
|
2007-11-18 04:44:38 +03:00
|
|
|
static void malta_fpga_reset(void *opaque)
|
2007-01-16 02:58:11 +03:00
|
|
|
{
|
|
|
|
MaltaFPGAState *s = opaque;
|
|
|
|
|
|
|
|
s->leds = 0x00;
|
|
|
|
s->brk = 0x0a;
|
|
|
|
s->gpout = 0x00;
|
2007-02-28 23:04:26 +03:00
|
|
|
s->i2cin = 0x3;
|
2007-01-16 02:58:11 +03:00
|
|
|
s->i2coe = 0x0;
|
|
|
|
s->i2cout = 0x3;
|
|
|
|
s->i2csel = 0x1;
|
|
|
|
|
|
|
|
s->display_text[8] = '\0';
|
|
|
|
snprintf(s->display_text, 9, " ");
|
2009-01-18 17:08:04 +03:00
|
|
|
}
|
|
|
|
|
chardev: Use QEMUChrEvent enum in IOEventHandler typedef
The Chardev events are listed in the QEMUChrEvent enum.
By using the enum in the IOEventHandler typedef we:
- make the IOEventHandler type more explicit (this handler
process out-of-band information, while the IOReadHandler
is in-band),
- help static code analyzers.
This patch was produced with the following spatch script:
@match@
expression backend, opaque, context, set_open;
identifier fd_can_read, fd_read, fd_event, be_change;
@@
qemu_chr_fe_set_handlers(backend, fd_can_read, fd_read, fd_event,
be_change, opaque, context, set_open);
@depends on match@
identifier opaque, event;
identifier match.fd_event;
@@
static
-void fd_event(void *opaque, int event)
+void fd_event(void *opaque, QEMUChrEvent event)
{
...
}
Then the typedef was modified manually in
include/chardev/char-fe.h.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Acked-by: Corey Minyard <cminyard@mvista.com>
Acked-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20191218172009.8868-15-philmd@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-12-18 20:20:09 +03:00
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static void malta_fgpa_display_event(void *opaque, QEMUChrEvent event)
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2009-01-18 17:08:04 +03:00
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{
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2016-10-22 12:52:45 +03:00
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MaltaFPGAState *s = opaque;
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if (event == CHR_EVENT_OPENED && !s->display_inited) {
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2016-10-22 12:52:55 +03:00
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qemu_chr_fe_printf(&s->display, "\e[HMalta LEDBAR\r\n");
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qemu_chr_fe_printf(&s->display, "+--------+\r\n");
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qemu_chr_fe_printf(&s->display, "+ +\r\n");
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qemu_chr_fe_printf(&s->display, "+--------+\r\n");
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qemu_chr_fe_printf(&s->display, "\n");
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qemu_chr_fe_printf(&s->display, "Malta ASCII\r\n");
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qemu_chr_fe_printf(&s->display, "+--------+\r\n");
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qemu_chr_fe_printf(&s->display, "+ +\r\n");
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qemu_chr_fe_printf(&s->display, "+--------+\r\n");
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2016-10-22 12:52:45 +03:00
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s->display_inited = true;
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}
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2007-01-16 02:58:11 +03:00
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}
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2011-08-08 23:14:25 +04:00
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static MaltaFPGAState *malta_fpga_init(MemoryRegion *address_space,
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2016-12-07 16:20:22 +03:00
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hwaddr base, qemu_irq uart_irq, Chardev *uart_chr)
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2007-01-16 02:58:11 +03:00
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{
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MaltaFPGAState *s;
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2016-12-07 16:20:22 +03:00
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Chardev *chr;
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2007-01-16 02:58:11 +03:00
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2019-12-06 16:58:04 +03:00
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s = g_new0(MaltaFPGAState, 1);
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2007-01-16 02:58:11 +03:00
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2013-06-06 13:41:28 +04:00
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memory_region_init_io(&s->iomem, NULL, &malta_fpga_ops, s,
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2011-08-08 23:14:25 +04:00
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"malta-fpga", 0x100000);
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2013-06-06 13:41:28 +04:00
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memory_region_init_alias(&s->iomem_lo, NULL, "malta-fpga",
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2011-08-08 23:14:25 +04:00
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&s->iomem, 0, 0x900);
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2013-06-06 13:41:28 +04:00
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memory_region_init_alias(&s->iomem_hi, NULL, "malta-fpga",
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2020-09-05 23:01:24 +03:00
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&s->iomem, 0xa00, 0x100000 - 0xa00);
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2007-03-31 20:54:14 +04:00
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2011-08-08 23:14:25 +04:00
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memory_region_add_subregion(address_space, base, &s->iomem_lo);
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memory_region_add_subregion(address_space, base + 0xa00, &s->iomem_hi);
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2007-01-16 02:58:11 +03:00
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2019-02-13 16:18:13 +03:00
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chr = qemu_chr_new("fpga", "vc:320x200", NULL);
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2016-10-22 12:52:55 +03:00
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qemu_chr_fe_init(&s->display, chr, NULL);
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qemu_chr_fe_set_handlers(&s->display, NULL, NULL,
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2017-07-06 15:08:49 +03:00
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malta_fgpa_display_event, NULL, s, NULL, true);
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2009-01-18 17:08:04 +03:00
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2011-08-12 03:07:16 +04:00
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s->uart = serial_mm_init(address_space, base + 0x900, 3, uart_irq,
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230400, uart_chr, DEVICE_NATIVE_ENDIAN);
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2007-03-31 20:54:14 +04:00
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2007-01-16 02:58:11 +03:00
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malta_fpga_reset(s);
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2009-06-27 11:25:07 +04:00
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qemu_register_reset(malta_fpga_reset, s);
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2007-01-16 02:58:11 +03:00
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return s;
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}
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/* Network support */
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2013-06-06 12:48:51 +04:00
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static void network_init(PCIBus *pci_bus)
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2007-01-16 02:58:11 +03:00
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{
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int i;
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2019-08-19 15:07:54 +03:00
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for (i = 0; i < nb_nics; i++) {
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2009-01-13 22:47:10 +03:00
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NICInfo *nd = &nd_table[i];
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2009-06-18 17:14:08 +04:00
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const char *default_devaddr = NULL;
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2009-01-13 22:47:10 +03:00
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if (i == 0 && (!nd->model || strcmp(nd->model, "pcnet") == 0))
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2007-01-16 02:58:11 +03:00
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/* The malta board has a PCNet card using PCI SLOT 11 */
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2009-06-18 17:14:08 +04:00
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default_devaddr = "0b";
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2009-01-13 22:47:10 +03:00
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2013-06-06 12:48:51 +04:00
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pci_nic_init_nofail(nd, pci_bus, "pcnet", default_devaddr);
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2007-01-16 02:58:11 +03:00
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}
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}
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2022-12-11 23:25:48 +03:00
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static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr,
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uint64_t kernel_entry)
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2018-08-02 17:16:42 +03:00
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{
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2022-10-26 02:54:46 +03:00
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static const char pci_pins_cfg[PCI_NUM_PINS] = {
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10, 10, 11, 11 /* PIIX IRQRC[A:D] */
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};
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2023-08-23 09:53:19 +03:00
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/* Bus endianness is always reversed */
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2022-03-23 18:57:18 +03:00
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#if TARGET_BIG_ENDIAN
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2023-03-30 18:26:13 +03:00
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#define cpu_to_gt32(x) (x)
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2018-08-02 17:16:43 +03:00
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#else
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2023-03-30 18:26:13 +03:00
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#define cpu_to_gt32(x) bswap32(x)
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2022-12-11 20:42:23 +03:00
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#endif
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2018-08-02 17:16:43 +03:00
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2022-12-11 20:47:21 +03:00
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/* setup MEM-to-PCI0 mapping as done by YAMON */
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/* move GT64120 registers from 0x14000000 to 0x1be00000 */
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2022-12-11 23:25:48 +03:00
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bl_gen_write_u32(p, /* GT_ISD */
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2022-12-11 20:47:21 +03:00
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cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68),
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cpu_to_gt32(0x1be00000 << 3));
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2022-12-11 20:54:49 +03:00
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/* setup PCI0 io window to 0x18000000-0x181fffff */
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2022-12-11 23:25:48 +03:00
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bl_gen_write_u32(p, /* GT_PCI0IOLD */
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2022-12-11 20:54:49 +03:00
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cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48),
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cpu_to_gt32(0x18000000 << 3));
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2022-12-11 23:25:48 +03:00
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bl_gen_write_u32(p, /* GT_PCI0IOHD */
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2022-12-11 20:54:49 +03:00
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cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50),
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cpu_to_gt32(0x08000000 << 3));
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2022-12-11 20:42:23 +03:00
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/* setup PCI0 mem windows */
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2022-12-11 23:25:48 +03:00
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bl_gen_write_u32(p, /* GT_PCI0M0LD */
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2022-12-11 20:49:13 +03:00
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cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58),
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cpu_to_gt32(0x10000000 << 3));
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2022-12-11 23:25:48 +03:00
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bl_gen_write_u32(p, /* GT_PCI0M0HD */
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2022-12-11 20:49:13 +03:00
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cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60),
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cpu_to_gt32(0x07e00000 << 3));
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2022-12-11 23:25:48 +03:00
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bl_gen_write_u32(p, /* GT_PCI0M1LD */
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2022-12-11 20:42:23 +03:00
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cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80),
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cpu_to_gt32(0x18200000 << 3));
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2022-12-11 23:25:48 +03:00
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bl_gen_write_u32(p, /* GT_PCI0M1HD */
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2022-12-11 20:42:23 +03:00
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cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88),
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cpu_to_gt32(0x0bc00000 << 3));
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2018-08-02 17:16:43 +03:00
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2022-12-11 20:42:23 +03:00
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#undef cpu_to_gt32
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2018-08-02 17:16:43 +03:00
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2022-10-26 02:54:46 +03:00
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/*
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* The PIIX ISA bridge is on PCI bus 0 dev 10 func 0.
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* Load the PIIX IRQC[A:D] routing config address, then
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* write routing configuration to the config data register.
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*/
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bl_gen_write_u32(p, /* GT_PCI0_CFGADDR */
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cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcf8),
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tswap32((1 << 31) /* ConfigEn */
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| PCI_BUILD_BDF(0, PIIX4_PCI_DEVFN) << 8
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| PIIX_PIRQCA));
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bl_gen_write_u32(p, /* GT_PCI0_CFGDATA */
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cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcfc),
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tswap32(ldl_be_p(pci_pins_cfg)));
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2022-12-11 23:25:48 +03:00
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bl_gen_jump_kernel(p,
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2022-12-11 21:08:50 +03:00
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true, ENVP_VADDR - 64,
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/*
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2022-12-11 23:25:48 +03:00
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* If semihosting is used, arguments have already
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* been passed, so we preserve $a0.
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2022-12-11 21:08:50 +03:00
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*/
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!semihosting_get_argc(), 2,
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true, ENVP_VADDR,
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true, ENVP_VADDR + 8,
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true, loaderparams.ram_low_size,
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kernel_entry);
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2018-08-02 17:16:42 +03:00
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}
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2022-12-11 23:25:48 +03:00
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static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
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uint64_t kernel_entry)
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{
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uint16_t *p;
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/* Small bootloader */
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p = (uint16_t *)base;
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stw_p(p++, 0x2800); stw_p(p++, 0x001c);
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/* bc to_here */
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stw_p(p++, 0x8000); stw_p(p++, 0xc000);
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/* nop */
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stw_p(p++, 0x8000); stw_p(p++, 0xc000);
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/* nop */
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stw_p(p++, 0x8000); stw_p(p++, 0xc000);
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/* nop */
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stw_p(p++, 0x8000); stw_p(p++, 0xc000);
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/* nop */
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stw_p(p++, 0x8000); stw_p(p++, 0xc000);
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/* nop */
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stw_p(p++, 0x8000); stw_p(p++, 0xc000);
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/* nop */
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stw_p(p++, 0x8000); stw_p(p++, 0xc000);
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/* nop */
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/* to_here: */
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bl_setup_gt64120_jump_kernel((void **)&p, run_addr, kernel_entry);
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}
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2019-08-19 15:07:54 +03:00
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/*
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* ROM and pseudo bootloader
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*
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* The following code implements a very very simple bootloader. It first
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* loads the registers a0 to a3 to the values expected by the OS, and
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* then jump at the kernel address.
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*
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* The bootloader should pass the locations of the kernel arguments and
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* environment variables tables. Those tables contain the 32-bit address
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* of NULL terminated strings. The environment variables table should be
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* terminated by a NULL address.
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*
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* For a simpler implementation, the number of kernel arguments is fixed
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* to two (the name of the kernel and the command line), and the two
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* tables are actually the same one.
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*
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* The registers a0 to a3 should contain the following values:
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* a0 - number of kernel arguments
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* a1 - 32-bit address of the kernel arguments table
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* a2 - 32-bit address of the environment variables table
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* a3 - RAM size in bytes
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*/
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2020-12-15 09:41:53 +03:00
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static void write_bootloader(uint8_t *base, uint64_t run_addr,
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uint64_t kernel_entry)
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2007-01-16 02:58:11 +03:00
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{
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uint32_t *p;
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/* Small bootloader */
|
2009-04-10 07:36:49 +04:00
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p = (uint32_t *)base;
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2014-06-18 02:10:35 +04:00
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2019-12-06 16:58:04 +03:00
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stl_p(p++, 0x08000000 | /* j 0x1fc00580 */
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2014-06-18 02:10:35 +04:00
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((run_addr + 0x580) & 0x0fffffff) >> 2);
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2019-12-06 16:58:04 +03:00
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stl_p(p++, 0x00000000); /* nop */
|
2007-01-16 02:58:11 +03:00
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2007-05-04 18:34:34 +04:00
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/* YAMON service vector */
|
2019-12-06 16:58:04 +03:00
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stl_p(base + 0x500, run_addr + 0x0580); /* start: */
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stl_p(base + 0x504, run_addr + 0x083c); /* print_count: */
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stl_p(base + 0x520, run_addr + 0x0580); /* start: */
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stl_p(base + 0x52c, run_addr + 0x0800); /* flush_cache: */
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stl_p(base + 0x534, run_addr + 0x0808); /* print: */
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stl_p(base + 0x538, run_addr + 0x0800); /* reg_cpu_isr: */
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stl_p(base + 0x53c, run_addr + 0x0800); /* unred_cpu_isr: */
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stl_p(base + 0x540, run_addr + 0x0800); /* reg_ic_isr: */
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stl_p(base + 0x544, run_addr + 0x0800); /* unred_ic_isr: */
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stl_p(base + 0x548, run_addr + 0x0800); /* reg_esr: */
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stl_p(base + 0x54c, run_addr + 0x0800); /* unreg_esr: */
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stl_p(base + 0x550, run_addr + 0x0800); /* getchar: */
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stl_p(base + 0x554, run_addr + 0x0800); /* syscon_read: */
|
2007-05-04 18:34:34 +04:00
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|
2007-01-16 02:58:11 +03:00
|
|
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/* Second part of the bootloader */
|
2009-04-10 07:36:49 +04:00
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p = (uint32_t *) (base + 0x580);
|
2015-06-19 13:08:43 +03:00
|
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|
2022-10-26 22:18:21 +03:00
|
|
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/*
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|
|
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* Load BAR registers as done by YAMON:
|
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*
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|
|
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* - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff
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* - set up PCI0 MEM0 at 0x10000000, size 0x7e00000
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* - set up PCI0 MEM1 at 0x18200000, size 0xbc00000
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*
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*/
|
2007-04-19 19:38:26 +04:00
|
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|
|
2023-05-12 17:43:38 +03:00
|
|
|
bl_setup_gt64120_jump_kernel((void **)&p, run_addr, kernel_entry);
|
2007-05-04 18:34:34 +04:00
|
|
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|
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/* YAMON subroutines */
|
2009-04-10 07:36:49 +04:00
|
|
|
p = (uint32_t *) (base + 0x800);
|
2019-12-06 16:58:04 +03:00
|
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stl_p(p++, 0x03e00009); /* jalr ra */
|
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stl_p(p++, 0x24020000); /* li v0,0 */
|
2014-06-18 02:10:35 +04:00
|
|
|
/* 808 YAMON print */
|
2019-12-06 16:58:04 +03:00
|
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stl_p(p++, 0x03e06821); /* move t5,ra */
|
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stl_p(p++, 0x00805821); /* move t3,a0 */
|
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stl_p(p++, 0x00a05021); /* move t2,a1 */
|
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stl_p(p++, 0x91440000); /* lbu a0,0(t2) */
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stl_p(p++, 0x254a0001); /* addiu t2,t2,1 */
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|
|
stl_p(p++, 0x10800005); /* beqz a0,834 */
|
|
|
|
stl_p(p++, 0x00000000); /* nop */
|
|
|
|
stl_p(p++, 0x0ff0021c); /* jal 870 */
|
|
|
|
stl_p(p++, 0x00000000); /* nop */
|
|
|
|
stl_p(p++, 0x1000fff9); /* b 814 */
|
|
|
|
stl_p(p++, 0x00000000); /* nop */
|
|
|
|
stl_p(p++, 0x01a00009); /* jalr t5 */
|
|
|
|
stl_p(p++, 0x01602021); /* move a0,t3 */
|
2007-05-04 18:34:34 +04:00
|
|
|
/* 0x83c YAMON print_count */
|
2019-12-06 16:58:04 +03:00
|
|
|
stl_p(p++, 0x03e06821); /* move t5,ra */
|
|
|
|
stl_p(p++, 0x00805821); /* move t3,a0 */
|
|
|
|
stl_p(p++, 0x00a05021); /* move t2,a1 */
|
|
|
|
stl_p(p++, 0x00c06021); /* move t4,a2 */
|
|
|
|
stl_p(p++, 0x91440000); /* lbu a0,0(t2) */
|
|
|
|
stl_p(p++, 0x0ff0021c); /* jal 870 */
|
|
|
|
stl_p(p++, 0x00000000); /* nop */
|
|
|
|
stl_p(p++, 0x254a0001); /* addiu t2,t2,1 */
|
|
|
|
stl_p(p++, 0x258cffff); /* addiu t4,t4,-1 */
|
|
|
|
stl_p(p++, 0x1580fffa); /* bnez t4,84c */
|
|
|
|
stl_p(p++, 0x00000000); /* nop */
|
|
|
|
stl_p(p++, 0x01a00009); /* jalr t5 */
|
|
|
|
stl_p(p++, 0x01602021); /* move a0,t3 */
|
2007-05-04 18:34:34 +04:00
|
|
|
/* 0x870 */
|
2019-12-06 16:58:04 +03:00
|
|
|
stl_p(p++, 0x3c08b800); /* lui t0,0xb400 */
|
|
|
|
stl_p(p++, 0x350803f8); /* ori t0,t0,0x3f8 */
|
|
|
|
stl_p(p++, 0x91090005); /* lbu t1,5(t0) */
|
|
|
|
stl_p(p++, 0x00000000); /* nop */
|
|
|
|
stl_p(p++, 0x31290040); /* andi t1,t1,0x40 */
|
|
|
|
stl_p(p++, 0x1120fffc); /* beqz t1,878 <outch+0x8> */
|
|
|
|
stl_p(p++, 0x00000000); /* nop */
|
|
|
|
stl_p(p++, 0x03e00009); /* jalr ra */
|
|
|
|
stl_p(p++, 0xa1040000); /* sb a0,0(t0) */
|
2007-01-16 02:58:11 +03:00
|
|
|
}
|
|
|
|
|
2022-02-20 19:39:25 +03:00
|
|
|
static void G_GNUC_PRINTF(3, 4) prom_set(uint32_t *prom_buf, int index,
|
2010-09-23 23:28:05 +04:00
|
|
|
const char *string, ...)
|
2007-01-16 02:58:11 +03:00
|
|
|
{
|
|
|
|
va_list ap;
|
2020-12-15 09:41:53 +03:00
|
|
|
uint32_t table_addr;
|
2007-01-16 02:58:11 +03:00
|
|
|
|
2019-08-19 15:07:54 +03:00
|
|
|
if (index >= ENVP_NB_ENTRIES) {
|
2007-01-16 02:58:11 +03:00
|
|
|
return;
|
2019-08-19 15:07:54 +03:00
|
|
|
}
|
2007-01-16 02:58:11 +03:00
|
|
|
|
|
|
|
if (string == NULL) {
|
2009-11-14 15:04:29 +03:00
|
|
|
prom_buf[index] = 0;
|
2007-01-16 02:58:11 +03:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2020-12-15 09:41:53 +03:00
|
|
|
table_addr = sizeof(uint32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE;
|
2020-12-15 09:41:55 +03:00
|
|
|
prom_buf[index] = tswap32(ENVP_VADDR + table_addr);
|
2007-01-16 02:58:11 +03:00
|
|
|
|
|
|
|
va_start(ap, string);
|
2009-11-14 15:04:29 +03:00
|
|
|
vsnprintf((char *)prom_buf + table_addr, ENVP_ENTRY_SIZE, string, ap);
|
2007-01-16 02:58:11 +03:00
|
|
|
va_end(ap);
|
|
|
|
}
|
|
|
|
|
mips/malta: pass RNG seed via env var and re-randomize on reboot
As of the kernel commit linked below, Linux ingests an RNG seed
passed as part of the environment block by the bootloader or firmware.
This mechanism works across all different environment block types,
generically, which pass some block via the second firmware argument. On
malta, this has been tested to work when passed as an argument from
U-Boot's linux_env_set.
As is the case on most other architectures (such as boston), when
booting with `-kernel`, QEMU, acting as the bootloader, should pass the
RNG seed, so that the machine has good entropy for Linux to consume. So
this commit implements that quite simply by using the guest random API,
which is what is used on nearly all other archs too. It also
reinitializes the seed on reboot, so that it is always fresh.
Link: https://git.kernel.org/torvalds/c/056a68cea01
Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-10-25 20:28:43 +03:00
|
|
|
static void reinitialize_rng_seed(void *opaque)
|
|
|
|
{
|
|
|
|
char *rng_seed_hex = opaque;
|
|
|
|
uint8_t rng_seed[32];
|
|
|
|
|
|
|
|
qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
|
|
|
|
for (size_t i = 0; i < sizeof(rng_seed); ++i) {
|
|
|
|
sprintf(rng_seed_hex + i * 2, "%02x", rng_seed[i]);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-01-16 02:58:11 +03:00
|
|
|
/* Kernel */
|
2020-12-15 09:41:53 +03:00
|
|
|
static uint64_t load_kernel(void)
|
2007-01-16 02:58:11 +03:00
|
|
|
{
|
2020-12-15 09:41:53 +03:00
|
|
|
uint64_t kernel_entry, kernel_high, initrd_size;
|
2018-09-13 13:07:13 +03:00
|
|
|
long kernel_size;
|
2009-10-02 01:12:16 +04:00
|
|
|
ram_addr_t initrd_offset;
|
2009-11-14 15:04:29 +03:00
|
|
|
uint32_t *prom_buf;
|
|
|
|
long prom_size;
|
|
|
|
int prom_index = 0;
|
mips/malta: pass RNG seed via env var and re-randomize on reboot
As of the kernel commit linked below, Linux ingests an RNG seed
passed as part of the environment block by the bootloader or firmware.
This mechanism works across all different environment block types,
generically, which pass some block via the second firmware argument. On
malta, this has been tested to work when passed as an argument from
U-Boot's linux_env_set.
As is the case on most other architectures (such as boston), when
booting with `-kernel`, QEMU, acting as the bootloader, should pass the
RNG seed, so that the machine has good entropy for Linux to consume. So
this commit implements that quite simply by using the guest random API,
which is what is used on nearly all other archs too. It also
reinitializes the seed on reboot, so that it is always fresh.
Link: https://git.kernel.org/torvalds/c/056a68cea01
Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-10-25 20:28:43 +03:00
|
|
|
uint8_t rng_seed[32];
|
|
|
|
char rng_seed_hex[sizeof(rng_seed) * 2 + 1];
|
|
|
|
size_t rng_seed_prom_offset;
|
2009-09-20 18:58:02 +04:00
|
|
|
|
2019-01-15 15:18:03 +03:00
|
|
|
kernel_size = load_elf(loaderparams.kernel_filename, NULL,
|
|
|
|
cpu_mips_kseg0_to_phys, NULL,
|
2020-12-15 09:41:53 +03:00
|
|
|
&kernel_entry, NULL,
|
2023-09-07 14:35:00 +03:00
|
|
|
&kernel_high, NULL, TARGET_BIG_ENDIAN, EM_MIPS,
|
2020-01-27 01:55:04 +03:00
|
|
|
1, 0);
|
2017-07-27 02:56:13 +03:00
|
|
|
if (kernel_size < 0) {
|
hw/mips: Replace fprintf(stderr, "*\n" with error_report()
Replace a large number of the fprintf(stderr, "*\n" calls with
error_report(). The functions were renamed with these commands and then
compiler issues where manually fixed.
find ./* -type f -exec sed -i \
'N;N;N;N;N;N;N;N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N;N;N;N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N;N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
Some lines where then manually tweaked to pass checkpatch.
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Yongbok Kim <yongbok.kim@imgtec.com>
Cc: "Hervé Poussineau" <hpoussin@reactos.org>
Conversions that aren't followed by exit() dropped, because they might
be inappropriate.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20180203084315.20497-6-armbru@redhat.com>
2018-02-03 11:43:06 +03:00
|
|
|
error_report("could not load kernel '%s': %s",
|
2017-07-27 02:56:13 +03:00
|
|
|
loaderparams.kernel_filename,
|
|
|
|
load_elf_strerror(kernel_size));
|
2007-06-06 20:54:26 +04:00
|
|
|
exit(1);
|
2007-01-16 02:58:11 +03:00
|
|
|
}
|
2014-06-26 13:44:25 +04:00
|
|
|
|
2017-07-31 16:09:13 +03:00
|
|
|
/* Check where the kernel has been linked */
|
2022-12-18 03:06:45 +03:00
|
|
|
if (kernel_entry <= USEG_LIMIT) {
|
|
|
|
error_report("Trap-and-Emul kernels (Linux CONFIG_KVM_GUEST)"
|
|
|
|
" are not supported");
|
|
|
|
exit(1);
|
2014-06-18 02:10:35 +04:00
|
|
|
}
|
2007-01-16 02:58:11 +03:00
|
|
|
|
|
|
|
/* load initrd */
|
|
|
|
initrd_size = 0;
|
2007-04-01 21:56:37 +04:00
|
|
|
initrd_offset = 0;
|
2007-11-09 20:52:11 +03:00
|
|
|
if (loaderparams.initrd_filename) {
|
2019-08-19 15:07:54 +03:00
|
|
|
initrd_size = get_image_size(loaderparams.initrd_filename);
|
2007-04-01 21:56:37 +04:00
|
|
|
if (initrd_size > 0) {
|
2019-08-19 15:07:54 +03:00
|
|
|
/*
|
|
|
|
* The kernel allocates the bootmap memory in the low memory after
|
|
|
|
* the initrd. It takes at most 128kiB for 2GB RAM and 4kiB
|
|
|
|
* pages.
|
|
|
|
*/
|
2020-09-27 14:18:17 +03:00
|
|
|
initrd_offset = ROUND_UP(loaderparams.ram_low_size
|
|
|
|
- (initrd_size + 128 * KiB),
|
|
|
|
INITRD_PAGE_SIZE);
|
2017-06-23 13:42:56 +03:00
|
|
|
if (kernel_high >= initrd_offset) {
|
hw/mips: Replace fprintf(stderr, "*\n" with error_report()
Replace a large number of the fprintf(stderr, "*\n" calls with
error_report(). The functions were renamed with these commands and then
compiler issues where manually fixed.
find ./* -type f -exec sed -i \
'N;N;N;N;N;N;N;N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N;N;N;N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N;N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
Some lines where then manually tweaked to pass checkpatch.
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Yongbok Kim <yongbok.kim@imgtec.com>
Cc: "Hervé Poussineau" <hpoussin@reactos.org>
Conversions that aren't followed by exit() dropped, because they might
be inappropriate.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20180203084315.20497-6-armbru@redhat.com>
2018-02-03 11:43:06 +03:00
|
|
|
error_report("memory too small for initial ram disk '%s'",
|
|
|
|
loaderparams.initrd_filename);
|
2007-04-01 21:56:37 +04:00
|
|
|
exit(1);
|
|
|
|
}
|
2009-04-10 00:05:49 +04:00
|
|
|
initrd_size = load_image_targphys(loaderparams.initrd_filename,
|
|
|
|
initrd_offset,
|
2020-10-28 13:20:52 +03:00
|
|
|
loaderparams.ram_size - initrd_offset);
|
2007-04-01 21:56:37 +04:00
|
|
|
}
|
2007-01-16 02:58:11 +03:00
|
|
|
if (initrd_size == (target_ulong) -1) {
|
hw/mips: Replace fprintf(stderr, "*\n" with error_report()
Replace a large number of the fprintf(stderr, "*\n" calls with
error_report(). The functions were renamed with these commands and then
compiler issues where manually fixed.
find ./* -type f -exec sed -i \
'N;N;N;N;N;N;N;N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N;N;N;N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N;N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N;N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
find ./* -type f -exec sed -i \
'N; {s|fprintf(stderr, "\(.*\)\\n"\(.*\));|error_report("\1"\2);|Ig}' \
{} +
Some lines where then manually tweaked to pass checkpatch.
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Yongbok Kim <yongbok.kim@imgtec.com>
Cc: "Hervé Poussineau" <hpoussin@reactos.org>
Conversions that aren't followed by exit() dropped, because they might
be inappropriate.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20180203084315.20497-6-armbru@redhat.com>
2018-02-03 11:43:06 +03:00
|
|
|
error_report("could not load initial ram disk '%s'",
|
|
|
|
loaderparams.initrd_filename);
|
2007-01-16 02:58:11 +03:00
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-11-14 15:04:29 +03:00
|
|
|
/* Setup prom parameters. */
|
|
|
|
prom_size = ENVP_NB_ENTRIES * (sizeof(int32_t) + ENVP_ENTRY_SIZE);
|
2011-08-21 07:09:37 +04:00
|
|
|
prom_buf = g_malloc(prom_size);
|
2009-11-14 15:04:29 +03:00
|
|
|
|
2010-09-21 00:18:01 +04:00
|
|
|
prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_filename);
|
2009-11-14 15:04:29 +03:00
|
|
|
if (initrd_size > 0) {
|
2019-08-19 15:07:54 +03:00
|
|
|
prom_set(prom_buf, prom_index++,
|
|
|
|
"rd_start=0x%" PRIx64 " rd_size=%" PRId64 " %s",
|
2022-12-18 03:06:45 +03:00
|
|
|
cpu_mips_phys_to_kseg0(NULL, initrd_offset),
|
2019-08-19 15:07:54 +03:00
|
|
|
initrd_size, loaderparams.kernel_cmdline);
|
2009-11-14 15:04:29 +03:00
|
|
|
} else {
|
2010-09-21 00:18:01 +04:00
|
|
|
prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_cmdline);
|
2009-11-14 15:04:29 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
prom_set(prom_buf, prom_index++, "memsize");
|
2015-05-25 16:21:04 +03:00
|
|
|
prom_set(prom_buf, prom_index++, "%u", loaderparams.ram_low_size);
|
|
|
|
|
|
|
|
prom_set(prom_buf, prom_index++, "ememsize");
|
|
|
|
prom_set(prom_buf, prom_index++, "%u", loaderparams.ram_size);
|
2014-06-18 02:10:35 +04:00
|
|
|
|
2009-11-14 15:04:29 +03:00
|
|
|
prom_set(prom_buf, prom_index++, "modetty0");
|
|
|
|
prom_set(prom_buf, prom_index++, "38400n8r");
|
mips/malta: pass RNG seed via env var and re-randomize on reboot
As of the kernel commit linked below, Linux ingests an RNG seed
passed as part of the environment block by the bootloader or firmware.
This mechanism works across all different environment block types,
generically, which pass some block via the second firmware argument. On
malta, this has been tested to work when passed as an argument from
U-Boot's linux_env_set.
As is the case on most other architectures (such as boston), when
booting with `-kernel`, QEMU, acting as the bootloader, should pass the
RNG seed, so that the machine has good entropy for Linux to consume. So
this commit implements that quite simply by using the guest random API,
which is what is used on nearly all other archs too. It also
reinitializes the seed on reboot, so that it is always fresh.
Link: https://git.kernel.org/torvalds/c/056a68cea01
Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-10-25 20:28:43 +03:00
|
|
|
|
|
|
|
qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
|
|
|
|
for (size_t i = 0; i < sizeof(rng_seed); ++i) {
|
|
|
|
sprintf(rng_seed_hex + i * 2, "%02x", rng_seed[i]);
|
|
|
|
}
|
|
|
|
prom_set(prom_buf, prom_index++, "rngseed");
|
|
|
|
rng_seed_prom_offset = prom_index * ENVP_ENTRY_SIZE +
|
|
|
|
sizeof(uint32_t) * ENVP_NB_ENTRIES;
|
|
|
|
prom_set(prom_buf, prom_index++, "%s", rng_seed_hex);
|
|
|
|
|
2009-11-14 15:04:29 +03:00
|
|
|
prom_set(prom_buf, prom_index++, NULL);
|
|
|
|
|
2020-12-15 09:41:55 +03:00
|
|
|
rom_add_blob_fixed("prom", prom_buf, prom_size, ENVP_PADDR);
|
mips/malta: pass RNG seed via env var and re-randomize on reboot
As of the kernel commit linked below, Linux ingests an RNG seed
passed as part of the environment block by the bootloader or firmware.
This mechanism works across all different environment block types,
generically, which pass some block via the second firmware argument. On
malta, this has been tested to work when passed as an argument from
U-Boot's linux_env_set.
As is the case on most other architectures (such as boston), when
booting with `-kernel`, QEMU, acting as the bootloader, should pass the
RNG seed, so that the machine has good entropy for Linux to consume. So
this commit implements that quite simply by using the guest random API,
which is what is used on nearly all other archs too. It also
reinitializes the seed on reboot, so that it is always fresh.
Link: https://git.kernel.org/torvalds/c/056a68cea01
Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-10-25 20:28:43 +03:00
|
|
|
qemu_register_reset_nosnapshotload(reinitialize_rng_seed,
|
|
|
|
rom_ptr(ENVP_PADDR, prom_size) + rng_seed_prom_offset);
|
2007-01-16 02:58:11 +03:00
|
|
|
|
2015-04-28 12:11:02 +03:00
|
|
|
g_free(prom_buf);
|
2007-04-01 21:56:37 +04:00
|
|
|
return kernel_entry;
|
2007-01-16 02:58:11 +03:00
|
|
|
}
|
|
|
|
|
2012-12-17 06:27:07 +04:00
|
|
|
static void malta_mips_config(MIPSCPU *cpu)
|
2011-08-30 01:07:41 +04:00
|
|
|
{
|
2019-05-18 23:54:27 +03:00
|
|
|
MachineState *ms = MACHINE(qdev_get_machine());
|
|
|
|
unsigned int smp_cpus = ms->smp.cpus;
|
2012-12-17 06:27:07 +04:00
|
|
|
CPUMIPSState *env = &cpu->env;
|
|
|
|
CPUState *cs = CPU(cpu);
|
|
|
|
|
2020-12-02 20:53:09 +03:00
|
|
|
if (ase_mt_available(env)) {
|
2020-12-05 01:16:45 +03:00
|
|
|
env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0,
|
|
|
|
CP0MVPC0_PTC, 8,
|
|
|
|
smp_cpus * cs->nr_threads - 1);
|
|
|
|
env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0,
|
|
|
|
CP0MVPC0_PVPE, 4, smp_cpus - 1);
|
2020-12-02 20:53:09 +03:00
|
|
|
}
|
2011-08-30 01:07:41 +04:00
|
|
|
}
|
|
|
|
|
2023-01-09 20:23:19 +03:00
|
|
|
static int malta_pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
|
|
|
|
{
|
|
|
|
int slot;
|
|
|
|
|
|
|
|
slot = PCI_SLOT(pci_dev->devfn);
|
|
|
|
|
|
|
|
switch (slot) {
|
|
|
|
/* PIIX4 USB */
|
|
|
|
case 10:
|
|
|
|
return 3;
|
|
|
|
/* AMD 79C973 Ethernet */
|
|
|
|
case 11:
|
|
|
|
return 1;
|
|
|
|
/* Crystal 4281 Sound */
|
|
|
|
case 12:
|
|
|
|
return 2;
|
|
|
|
/* PCI slot 1 to 4 */
|
|
|
|
case 18 ... 21:
|
|
|
|
return ((slot - 18) + irq_num) & 0x03;
|
|
|
|
/* Unknown device, don't do any translation */
|
|
|
|
default:
|
|
|
|
return irq_num;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-01-16 02:58:11 +03:00
|
|
|
static void main_cpu_reset(void *opaque)
|
|
|
|
{
|
2012-05-05 16:14:00 +04:00
|
|
|
MIPSCPU *cpu = opaque;
|
|
|
|
CPUMIPSState *env = &cpu->env;
|
|
|
|
|
|
|
|
cpu_reset(CPU(cpu));
|
2007-01-16 02:58:11 +03:00
|
|
|
|
2019-08-19 15:07:54 +03:00
|
|
|
/*
|
|
|
|
* The bootloader does not need to be rewritten as it is located in a
|
|
|
|
* read only location. The kernel location and the arguments table
|
|
|
|
* location does not change.
|
|
|
|
*/
|
2007-11-09 20:52:11 +03:00
|
|
|
if (loaderparams.kernel_filename) {
|
2015-06-19 13:08:41 +03:00
|
|
|
env->CP0_Status &= ~(1 << CP0St_ERL);
|
2007-04-06 03:12:54 +04:00
|
|
|
}
|
2011-08-30 01:07:41 +04:00
|
|
|
|
2012-12-17 06:27:07 +04:00
|
|
|
malta_mips_config(cpu);
|
2007-01-16 02:58:11 +03:00
|
|
|
}
|
|
|
|
|
2020-10-12 12:58:02 +03:00
|
|
|
static void create_cpu_without_cps(MachineState *ms, MaltaState *s,
|
2016-03-15 12:59:35 +03:00
|
|
|
qemu_irq *cbus_irq, qemu_irq *i8259_irq)
|
2016-03-15 12:59:34 +03:00
|
|
|
{
|
|
|
|
CPUMIPSState *env;
|
|
|
|
MIPSCPU *cpu;
|
|
|
|
int i;
|
|
|
|
|
2019-05-18 23:54:20 +03:00
|
|
|
for (i = 0; i < ms->smp.cpus; i++) {
|
2020-10-12 12:58:02 +03:00
|
|
|
cpu = mips_cpu_create_with_clock(ms->cpu_type, s->cpuclk);
|
2016-03-15 12:59:34 +03:00
|
|
|
|
|
|
|
/* Init internal devices */
|
2016-03-15 16:32:19 +03:00
|
|
|
cpu_mips_irq_init_cpu(cpu);
|
|
|
|
cpu_mips_clock_init(cpu);
|
2016-03-15 12:59:34 +03:00
|
|
|
qemu_register_reset(main_cpu_reset, cpu);
|
|
|
|
}
|
|
|
|
|
|
|
|
cpu = MIPS_CPU(first_cpu);
|
|
|
|
env = &cpu->env;
|
|
|
|
*i8259_irq = env->irq[2];
|
|
|
|
*cbus_irq = env->irq[4];
|
|
|
|
}
|
|
|
|
|
2019-05-18 23:54:20 +03:00
|
|
|
static void create_cps(MachineState *ms, MaltaState *s,
|
2016-03-15 12:59:35 +03:00
|
|
|
qemu_irq *cbus_irq, qemu_irq *i8259_irq)
|
|
|
|
{
|
sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 1
I'm converting from qdev_set_parent_bus()/realize to qdev_realize();
recent commit "qdev: Convert uses of qdev_set_parent_bus() with
Coccinelle" explains why.
sysbus_init_child_obj() is a wrapper around
object_initialize_child_with_props() and qdev_set_parent_bus(). It
passes no properties.
Convert sysbus_init_child_obj()/realize to object_initialize_child()/
qdev_realize().
Coccinelle script:
@@
expression parent, name, size, type, errp;
expression child;
symbol true;
@@
- sysbus_init_child_obj(parent, name, &child, size, type);
+ sysbus_init_child_XXX(parent, name, &child, size, type);
...
- object_property_set_bool(OBJECT(&child), true, "realized", errp);
+ sysbus_realize(SYS_BUS_DEVICE(&child), errp);
@@
expression parent, name, size, type, errp;
expression child;
symbol true;
@@
- sysbus_init_child_obj(parent, name, child, size, type);
+ sysbus_init_child_XXX(parent, name, child, size, type);
...
- object_property_set_bool(OBJECT(child), true, "realized", errp);
+ sysbus_realize(SYS_BUS_DEVICE(child), errp);
@@
expression parent, name, size, type;
expression child;
expression dev;
expression expr;
@@
- sysbus_init_child_obj(parent, name, child, size, type);
+ sysbus_init_child_XXX(parent, name, child, size, type);
...
dev = DEVICE(child);
... when != dev = expr;
- qdev_init_nofail(dev);
+ sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
@@
expression parent, propname, type;
expression child;
@@
- sysbus_init_child_XXX(parent, propname, child, sizeof(*child), type)
+ object_initialize_child(parent, propname, child, type)
@@
expression parent, propname, type;
expression child;
@@
- sysbus_init_child_XXX(parent, propname, &child, sizeof(child), type)
+ object_initialize_child(parent, propname, &child, type)
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-48-armbru@redhat.com>
2020-06-10 08:32:36 +03:00
|
|
|
object_initialize_child(OBJECT(s), "cps", &s->cps, TYPE_MIPS_CPS);
|
qom: Put name parameter before value / visitor parameter
The object_property_set_FOO() setters take property name and value in
an unusual order:
void object_property_set_FOO(Object *obj, FOO_TYPE value,
const char *name, Error **errp)
Having to pass value before name feels grating. Swap them.
Same for object_property_set(), object_property_get(), and
object_property_parse().
Convert callers with this Coccinelle script:
@@
identifier fun = {
object_property_get, object_property_parse, object_property_set_str,
object_property_set_link, object_property_set_bool,
object_property_set_int, object_property_set_uint, object_property_set,
object_property_set_qobject
};
expression obj, v, name, errp;
@@
- fun(obj, v, name, errp)
+ fun(obj, name, v, errp)
Chokes on hw/arm/musicpal.c's lcd_refresh() with the unhelpful error
message "no position information". Convert that one manually.
Fails to convert hw/arm/armsse.c, because Coccinelle gets confused by
ARMSSE being used both as typedef and function-like macro there.
Convert manually.
Fails to convert hw/rx/rx-gdbsim.c, because Coccinelle gets confused
by RXCPU being used both as typedef and function-like macro there.
Convert manually. The other files using RXCPU that way don't need
conversion.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <20200707160613.848843-27-armbru@redhat.com>
[Straightforwad conflict with commit 2336172d9b "audio: set default
value for pcspk.iobase property" resolved]
2020-07-07 19:05:54 +03:00
|
|
|
object_property_set_str(OBJECT(&s->cps), "cpu-type", ms->cpu_type,
|
2020-05-05 13:19:04 +03:00
|
|
|
&error_fatal);
|
hw/mips: Declare all length properties as unsigned
Some length properties are signed, other unsigned:
hw/mips/cps.c:183: DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1),
hw/mips/cps.c:184: DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 256),
hw/misc/mips_cmgcr.c:215: DEFINE_PROP_INT32("num-vp", MIPSGCRState, num_vps, 1),
hw/misc/mips_cpc.c:167: DEFINE_PROP_UINT32("num-vp", MIPSCPCState, num_vp, 0x1),
hw/misc/mips_itu.c:552: DEFINE_PROP_INT32("num-fifo", MIPSITUState, num_fifo,
hw/misc/mips_itu.c:554: DEFINE_PROP_INT32("num-semaphores", MIPSITUState,
Since negative values are not used (the minimum is '0'),
unify by declaring all properties as unsigned.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230203113650.78146-9-philmd@linaro.org>
2023-02-02 12:46:45 +03:00
|
|
|
object_property_set_uint(OBJECT(&s->cps), "num-vp", ms->smp.cpus,
|
2020-05-05 13:19:04 +03:00
|
|
|
&error_fatal);
|
2020-10-12 12:58:02 +03:00
|
|
|
qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", s->cpuclk);
|
sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 1
I'm converting from qdev_set_parent_bus()/realize to qdev_realize();
recent commit "qdev: Convert uses of qdev_set_parent_bus() with
Coccinelle" explains why.
sysbus_init_child_obj() is a wrapper around
object_initialize_child_with_props() and qdev_set_parent_bus(). It
passes no properties.
Convert sysbus_init_child_obj()/realize to object_initialize_child()/
qdev_realize().
Coccinelle script:
@@
expression parent, name, size, type, errp;
expression child;
symbol true;
@@
- sysbus_init_child_obj(parent, name, &child, size, type);
+ sysbus_init_child_XXX(parent, name, &child, size, type);
...
- object_property_set_bool(OBJECT(&child), true, "realized", errp);
+ sysbus_realize(SYS_BUS_DEVICE(&child), errp);
@@
expression parent, name, size, type, errp;
expression child;
symbol true;
@@
- sysbus_init_child_obj(parent, name, child, size, type);
+ sysbus_init_child_XXX(parent, name, child, size, type);
...
- object_property_set_bool(OBJECT(child), true, "realized", errp);
+ sysbus_realize(SYS_BUS_DEVICE(child), errp);
@@
expression parent, name, size, type;
expression child;
expression dev;
expression expr;
@@
- sysbus_init_child_obj(parent, name, child, size, type);
+ sysbus_init_child_XXX(parent, name, child, size, type);
...
dev = DEVICE(child);
... when != dev = expr;
- qdev_init_nofail(dev);
+ sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
@@
expression parent, propname, type;
expression child;
@@
- sysbus_init_child_XXX(parent, propname, child, sizeof(*child), type)
+ object_initialize_child(parent, propname, child, type)
@@
expression parent, propname, type;
expression child;
@@
- sysbus_init_child_XXX(parent, propname, &child, sizeof(child), type)
+ object_initialize_child(parent, propname, &child, type)
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-48-armbru@redhat.com>
2020-06-10 08:32:36 +03:00
|
|
|
sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal);
|
2016-03-15 12:59:35 +03:00
|
|
|
|
2019-05-07 19:34:09 +03:00
|
|
|
sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1);
|
2016-03-15 12:59:35 +03:00
|
|
|
|
2019-05-07 19:34:09 +03:00
|
|
|
*i8259_irq = get_cps_irq(&s->cps, 3);
|
2016-03-15 12:59:35 +03:00
|
|
|
*cbus_irq = NULL;
|
|
|
|
}
|
|
|
|
|
2019-05-18 23:54:20 +03:00
|
|
|
static void mips_create_cpu(MachineState *ms, MaltaState *s,
|
2017-10-05 16:51:10 +03:00
|
|
|
qemu_irq *cbus_irq, qemu_irq *i8259_irq)
|
2016-03-15 12:59:35 +03:00
|
|
|
{
|
2020-12-08 00:32:49 +03:00
|
|
|
if ((ms->smp.cpus > 1) && cpu_type_supports_cps_smp(ms->cpu_type)) {
|
2019-05-18 23:54:20 +03:00
|
|
|
create_cps(ms, s, cbus_irq, i8259_irq);
|
2016-03-15 12:59:35 +03:00
|
|
|
} else {
|
2020-10-12 12:58:02 +03:00
|
|
|
create_cpu_without_cps(ms, s, cbus_irq, i8259_irq);
|
2016-03-15 12:59:35 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-02-18 03:10:59 +03:00
|
|
|
static
|
2014-05-07 18:42:57 +04:00
|
|
|
void mips_malta_init(MachineState *machine)
|
2007-01-16 02:58:11 +03:00
|
|
|
{
|
2014-05-07 18:42:57 +04:00
|
|
|
ram_addr_t ram_size = machine->ram_size;
|
2014-06-18 02:10:35 +04:00
|
|
|
ram_addr_t ram_low_size;
|
2014-05-07 18:42:57 +04:00
|
|
|
const char *kernel_filename = machine->kernel_filename;
|
|
|
|
const char *kernel_cmdline = machine->kernel_cmdline;
|
|
|
|
const char *initrd_filename = machine->initrd_filename;
|
2009-05-30 03:52:44 +04:00
|
|
|
char *filename;
|
2019-03-08 12:45:56 +03:00
|
|
|
PFlashCFI01 *fl;
|
2011-08-04 16:55:30 +04:00
|
|
|
MemoryRegion *system_memory = get_system_memory();
|
2013-09-06 16:57:44 +04:00
|
|
|
MemoryRegion *ram_low_preio = g_new(MemoryRegion, 1);
|
|
|
|
MemoryRegion *ram_low_postio;
|
2013-06-14 11:30:44 +04:00
|
|
|
MemoryRegion *bios, *bios_copy = g_new(MemoryRegion, 1);
|
2013-06-14 11:30:47 +04:00
|
|
|
const size_t smbus_eeprom_size = 8 * 256;
|
|
|
|
uint8_t *smbus_eeprom_buf = g_malloc0(smbus_eeprom_size);
|
2020-12-15 09:41:53 +03:00
|
|
|
uint64_t kernel_entry, bootloader_run_addr;
|
2007-01-16 02:58:11 +03:00
|
|
|
PCIBus *pci_bus;
|
2011-12-16 01:09:51 +04:00
|
|
|
ISABus *isa_bus;
|
2016-03-15 12:59:34 +03:00
|
|
|
qemu_irq cbus_irq, i8259_irq;
|
2013-08-03 02:18:51 +04:00
|
|
|
I2CBus *smbus;
|
2009-07-22 18:42:57 +04:00
|
|
|
DriveInfo *dinfo;
|
2008-01-04 22:11:32 +03:00
|
|
|
int fl_idx = 0;
|
2020-10-12 18:56:40 +03:00
|
|
|
MaltaState *s;
|
2022-06-03 21:50:41 +03:00
|
|
|
PCIDevice *piix4;
|
2020-10-12 18:56:40 +03:00
|
|
|
DeviceState *dev;
|
2007-01-16 02:58:11 +03:00
|
|
|
|
2020-10-12 18:56:40 +03:00
|
|
|
s = MIPS_MALTA(qdev_new(TYPE_MIPS_MALTA));
|
|
|
|
sysbus_realize_and_unref(SYS_BUS_DEVICE(s), &error_fatal);
|
2011-11-29 09:34:48 +04:00
|
|
|
|
2016-03-15 12:59:35 +03:00
|
|
|
/* create CPU */
|
2019-05-18 23:54:20 +03:00
|
|
|
mips_create_cpu(machine, s, &cbus_irq, &i8259_irq);
|
2007-01-16 02:58:11 +03:00
|
|
|
|
|
|
|
/* allocate RAM */
|
2018-06-25 15:42:22 +03:00
|
|
|
if (ram_size > 2 * GiB) {
|
|
|
|
error_report("Too much memory for this machine: %" PRId64 "MB,"
|
|
|
|
" maximum 2048MB", ram_size / MiB);
|
2009-01-24 18:07:25 +03:00
|
|
|
exit(1);
|
|
|
|
}
|
2013-09-06 16:57:44 +04:00
|
|
|
|
|
|
|
/* register RAM at high address where it is undisturbed by IO */
|
2020-02-19 19:09:29 +03:00
|
|
|
memory_region_add_subregion(system_memory, 0x80000000, machine->ram);
|
2013-09-06 16:57:44 +04:00
|
|
|
|
|
|
|
/* alias for pre IO hole access */
|
|
|
|
memory_region_init_alias(ram_low_preio, NULL, "mips_malta_low_preio.ram",
|
2020-02-19 19:09:29 +03:00
|
|
|
machine->ram, 0, MIN(ram_size, 256 * MiB));
|
2013-09-06 16:57:44 +04:00
|
|
|
memory_region_add_subregion(system_memory, 0, ram_low_preio);
|
|
|
|
|
|
|
|
/* alias for post IO hole access, if there is enough RAM */
|
2018-06-25 15:42:22 +03:00
|
|
|
if (ram_size > 512 * MiB) {
|
2013-09-06 16:57:44 +04:00
|
|
|
ram_low_postio = g_new(MemoryRegion, 1);
|
|
|
|
memory_region_init_alias(ram_low_postio, NULL,
|
|
|
|
"mips_malta_low_postio.ram",
|
2020-02-19 19:09:29 +03:00
|
|
|
machine->ram, 512 * MiB,
|
2018-06-25 15:42:22 +03:00
|
|
|
ram_size - 512 * MiB);
|
|
|
|
memory_region_add_subregion(system_memory, 512 * MiB,
|
|
|
|
ram_low_postio);
|
2013-09-06 16:57:44 +04:00
|
|
|
}
|
2007-01-16 02:58:11 +03:00
|
|
|
|
2007-06-06 21:19:24 +04:00
|
|
|
/* FPGA */
|
2018-03-09 01:39:37 +03:00
|
|
|
|
2012-11-14 18:04:42 +04:00
|
|
|
/* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 */
|
2018-04-20 17:52:43 +03:00
|
|
|
malta_fpga_init(system_memory, FPGA_ADDRESS, cbus_irq, serial_hd(2));
|
2007-06-06 21:19:24 +04:00
|
|
|
|
2012-01-28 09:18:17 +04:00
|
|
|
/* Load firmware in flash / BIOS. */
|
|
|
|
dinfo = drive_get(IF_PFLASH, 0, fl_idx);
|
2019-03-08 12:46:09 +03:00
|
|
|
fl = pflash_cfi01_register(FLASH_ADDRESS, "mips_malta.bios",
|
2019-03-08 12:46:08 +03:00
|
|
|
FLASH_SIZE,
|
2014-10-07 15:59:18 +04:00
|
|
|
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
|
2019-03-08 12:46:10 +03:00
|
|
|
65536,
|
2023-09-07 14:35:00 +03:00
|
|
|
4, 0x0000, 0x0000, 0x0000, 0x0000,
|
|
|
|
TARGET_BIG_ENDIAN);
|
2012-01-28 09:18:17 +04:00
|
|
|
bios = pflash_cfi01_get_memory(fl);
|
|
|
|
fl_idx++;
|
2008-01-04 22:11:32 +03:00
|
|
|
if (kernel_filename) {
|
2018-06-25 15:42:22 +03:00
|
|
|
ram_low_size = MIN(ram_size, 256 * MiB);
|
2022-12-18 03:06:45 +03:00
|
|
|
bootloader_run_addr = cpu_mips_phys_to_kseg0(NULL, RESET_ADDRESS);
|
2014-06-18 02:10:35 +04:00
|
|
|
|
2008-01-04 22:11:32 +03:00
|
|
|
/* Write a small bootloader to the flash location. */
|
2015-05-25 16:21:04 +03:00
|
|
|
loaderparams.ram_size = ram_size;
|
|
|
|
loaderparams.ram_low_size = ram_low_size;
|
2008-01-04 22:11:32 +03:00
|
|
|
loaderparams.kernel_filename = kernel_filename;
|
|
|
|
loaderparams.kernel_cmdline = kernel_cmdline;
|
|
|
|
loaderparams.initrd_filename = initrd_filename;
|
2009-11-14 03:04:29 +03:00
|
|
|
kernel_entry = load_kernel();
|
2014-06-18 02:10:35 +04:00
|
|
|
|
2020-12-08 00:32:49 +03:00
|
|
|
if (!cpu_type_supports_isa(machine->cpu_type, ISA_NANOMIPS32)) {
|
2018-08-02 17:16:42 +03:00
|
|
|
write_bootloader(memory_region_get_ram_ptr(bios),
|
|
|
|
bootloader_run_addr, kernel_entry);
|
|
|
|
} else {
|
|
|
|
write_bootloader_nanomips(memory_region_get_ram_ptr(bios),
|
|
|
|
bootloader_run_addr, kernel_entry);
|
|
|
|
}
|
2008-01-04 22:11:32 +03:00
|
|
|
} else {
|
2019-03-08 12:46:07 +03:00
|
|
|
target_long bios_size = FLASH_SIZE;
|
2012-01-28 09:18:17 +04:00
|
|
|
/* Load firmware from flash. */
|
|
|
|
if (!dinfo) {
|
2008-01-04 22:11:32 +03:00
|
|
|
/* Load a BIOS image. */
|
2020-07-21 09:15:05 +03:00
|
|
|
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS,
|
2020-10-26 17:30:21 +03:00
|
|
|
machine->firmware ?: BIOS_FILENAME);
|
2009-05-30 03:52:44 +04:00
|
|
|
if (filename) {
|
2012-01-28 09:18:18 +04:00
|
|
|
bios_size = load_image_targphys(filename, FLASH_ADDRESS,
|
2009-05-30 03:52:44 +04:00
|
|
|
BIOS_SIZE);
|
2011-08-21 07:09:37 +04:00
|
|
|
g_free(filename);
|
2009-05-30 03:52:44 +04:00
|
|
|
} else {
|
|
|
|
bios_size = -1;
|
|
|
|
}
|
2013-07-29 18:05:31 +04:00
|
|
|
if ((bios_size < 0 || bios_size > BIOS_SIZE) &&
|
2020-10-26 17:30:21 +03:00
|
|
|
machine->firmware && !qtest_enabled()) {
|
|
|
|
error_report("Could not load MIPS bios '%s'", machine->firmware);
|
2013-08-03 18:03:18 +04:00
|
|
|
exit(1);
|
2008-01-04 22:11:32 +03:00
|
|
|
}
|
2007-06-06 21:19:24 +04:00
|
|
|
}
|
2019-08-19 15:07:54 +03:00
|
|
|
/*
|
|
|
|
* In little endian mode the 32bit words in the bios are swapped,
|
|
|
|
* a neat trick which allows bi-endian firmware.
|
|
|
|
*/
|
2022-03-23 18:57:18 +03:00
|
|
|
#if !TARGET_BIG_ENDIAN
|
2007-06-07 16:17:52 +04:00
|
|
|
{
|
2018-06-26 12:35:40 +03:00
|
|
|
uint32_t *end, *addr;
|
|
|
|
const size_t swapsize = MIN(bios_size, 0x3e0000);
|
|
|
|
addr = rom_ptr(FLASH_ADDRESS, swapsize);
|
2013-06-14 11:30:43 +04:00
|
|
|
if (!addr) {
|
|
|
|
addr = memory_region_get_ram_ptr(bios);
|
|
|
|
}
|
2018-06-26 12:35:40 +03:00
|
|
|
end = (void *)addr + swapsize;
|
2009-04-10 07:36:49 +04:00
|
|
|
while (addr < end) {
|
|
|
|
bswap32s(addr);
|
2011-11-13 15:42:42 +04:00
|
|
|
addr++;
|
2007-06-07 16:17:52 +04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
2007-06-06 21:19:24 +04:00
|
|
|
}
|
|
|
|
|
2013-06-14 11:30:44 +04:00
|
|
|
/*
|
|
|
|
* Map the BIOS at a 2nd physical location, as on the real board.
|
|
|
|
* Copy it so that we can patch in the MIPS revision, which cannot be
|
|
|
|
* handled by an overlapping region as the resulting ROM code subpage
|
|
|
|
* regions are not executable.
|
|
|
|
*/
|
2018-06-04 14:03:58 +03:00
|
|
|
memory_region_init_ram(bios_copy, NULL, "bios.1fc", BIOS_SIZE,
|
Fix bad error handling after memory_region_init_ram()
Symptom:
$ qemu-system-x86_64 -m 10000000
Unexpected error in ram_block_add() at /work/armbru/qemu/exec.c:1456:
upstream-qemu: cannot set up guest memory 'pc.ram': Cannot allocate memory
Aborted (core dumped)
Root cause: commit ef701d7 screwed up handling of out-of-memory
conditions. Before the commit, we report the error and exit(1), in
one place, ram_block_add(). The commit lifts the error handling up
the call chain some, to three places. Fine. Except it uses
&error_abort in these places, changing the behavior from exit(1) to
abort(), and thus undoing the work of commit 3922825 "exec: Don't
abort when we can't allocate guest memory".
The three places are:
* memory_region_init_ram()
Commit 4994653 (right after commit ef701d7) lifted the error
handling further, through memory_region_init_ram(), multiplying the
incorrect use of &error_abort. Later on, imitation of existing
(bad) code may have created more.
* memory_region_init_ram_ptr()
The &error_abort is still there.
* memory_region_init_rom_device()
Doesn't need fixing, because commit 33e0eb5 (soon after commit
ef701d7) lifted the error handling further, and in the process
changed it from &error_abort to passing it up the call chain.
Correct, because the callers are realize() methods.
Fix the error handling after memory_region_init_ram() with a
Coccinelle semantic patch:
@r@
expression mr, owner, name, size, err;
position p;
@@
memory_region_init_ram(mr, owner, name, size,
(
- &error_abort
+ &error_fatal
|
err@p
)
);
@script:python@
p << r.p;
@@
print "%s:%s:%s" % (p[0].file, p[0].line, p[0].column)
When the last argument is &error_abort, it gets replaced by
&error_fatal. This is the fix.
If the last argument is anything else, its position is reported. This
lets us check the fix is complete. Four positions get reported:
* ram_backend_memory_alloc()
Error is passed up the call chain, ultimately through
user_creatable_complete(). As far as I can tell, it's callers all
handle the error sanely.
* fsl_imx25_realize(), fsl_imx31_realize(), dp8393x_realize()
DeviceClass.realize() methods, errors handled sanely further up the
call chain.
We're good. Test case again behaves:
$ qemu-system-x86_64 -m 10000000
qemu-system-x86_64: cannot set up guest memory 'pc.ram': Cannot allocate memory
[Exit 1 ]
The next commits will repair the rest of commit ef701d7's damage.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <1441983105-26376-3-git-send-email-armbru@redhat.com>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
2015-09-11 17:51:43 +03:00
|
|
|
&error_fatal);
|
2013-06-14 11:30:44 +04:00
|
|
|
if (!rom_copy(memory_region_get_ram_ptr(bios_copy),
|
2013-07-29 09:00:29 +04:00
|
|
|
FLASH_ADDRESS, BIOS_SIZE)) {
|
2013-06-14 11:30:44 +04:00
|
|
|
memcpy(memory_region_get_ram_ptr(bios_copy),
|
2013-07-29 09:00:29 +04:00
|
|
|
memory_region_get_ram_ptr(bios), BIOS_SIZE);
|
2013-06-14 11:30:44 +04:00
|
|
|
}
|
|
|
|
memory_region_set_readonly(bios_copy, true);
|
|
|
|
memory_region_add_subregion(system_memory, RESET_ADDRESS, bios_copy);
|
2012-01-28 09:18:16 +04:00
|
|
|
|
2013-06-14 11:30:44 +04:00
|
|
|
/* Board ID = 0x420 (Malta Board with CoreLV) */
|
|
|
|
stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
|
2007-01-16 02:58:11 +03:00
|
|
|
|
|
|
|
/* Northbridge */
|
2022-10-26 02:54:06 +03:00
|
|
|
dev = qdev_new("gt64120");
|
2023-09-07 14:35:00 +03:00
|
|
|
qdev_prop_set_bit(dev, "cpu-little-endian", !TARGET_BIG_ENDIAN);
|
2022-10-26 02:54:06 +03:00
|
|
|
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
|
2022-02-17 13:19:24 +03:00
|
|
|
pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci"));
|
2023-01-09 20:23:19 +03:00
|
|
|
pci_bus_map_irqs(pci_bus, malta_pci_slot_get_pirq);
|
2007-01-16 02:58:11 +03:00
|
|
|
|
|
|
|
/* Southbridge */
|
2023-10-07 15:38:32 +03:00
|
|
|
piix4 = pci_new_multifunction(PIIX4_PCI_DEVFN, TYPE_PIIX4_PCI_DEVICE);
|
|
|
|
qdev_prop_set_uint32(DEVICE(piix4), "smb_io_base", 0x1100);
|
|
|
|
pci_realize_and_unref(piix4, pci_bus, &error_fatal);
|
2022-10-22 18:04:53 +03:00
|
|
|
isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix4), "isa.0"));
|
|
|
|
|
|
|
|
dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "ide"));
|
|
|
|
pci_ide_create_devs(PCI_DEVICE(dev));
|
2011-09-12 14:00:05 +04:00
|
|
|
|
2018-01-06 18:37:21 +03:00
|
|
|
/* Interrupt controller */
|
2022-10-22 18:04:53 +03:00
|
|
|
qdev_connect_gpio_out_named(DEVICE(piix4), "intr", 0, i8259_irq);
|
2011-09-12 14:00:05 +04:00
|
|
|
|
2018-03-09 01:39:36 +03:00
|
|
|
/* generate SPD EEPROM data */
|
2022-10-22 18:04:50 +03:00
|
|
|
dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "pm"));
|
|
|
|
smbus = I2C_BUS(qdev_get_child_bus(dev, "i2c"));
|
2018-03-09 01:39:36 +03:00
|
|
|
generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size);
|
|
|
|
generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]);
|
|
|
|
smbus_eeprom_init(smbus, 8, smbus_eeprom_buf, smbus_eeprom_size);
|
|
|
|
g_free(smbus_eeprom_buf);
|
2007-01-16 02:58:11 +03:00
|
|
|
|
2018-03-09 01:39:37 +03:00
|
|
|
/* Super I/O: SMS FDC37M817 */
|
|
|
|
isa_create_simple(isa_bus, TYPE_FDC37M81X_SUPERIO);
|
2007-01-16 02:58:11 +03:00
|
|
|
|
|
|
|
/* Network card */
|
2013-06-06 12:48:51 +04:00
|
|
|
network_init(pci_bus);
|
2007-03-19 01:18:43 +03:00
|
|
|
|
|
|
|
/* Optional PCI video card */
|
2012-09-08 13:53:12 +04:00
|
|
|
pci_vga_init(pci_bus);
|
2007-01-16 02:58:11 +03:00
|
|
|
}
|
|
|
|
|
2020-10-12 12:58:02 +03:00
|
|
|
static void mips_malta_instance_init(Object *obj)
|
|
|
|
{
|
|
|
|
MaltaState *s = MIPS_MALTA(obj);
|
|
|
|
|
|
|
|
s->cpuclk = qdev_init_clock_out(DEVICE(obj), "cpu-refclk");
|
|
|
|
clock_set_hz(s->cpuclk, 320000000); /* 320 MHz */
|
|
|
|
}
|
|
|
|
|
2013-01-10 19:19:07 +04:00
|
|
|
static const TypeInfo mips_malta_device = {
|
2013-07-28 00:19:54 +04:00
|
|
|
.name = TYPE_MIPS_MALTA,
|
2011-12-08 07:34:16 +04:00
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
|
|
.instance_size = sizeof(MaltaState),
|
2020-10-12 12:58:02 +03:00
|
|
|
.instance_init = mips_malta_instance_init,
|
2011-11-29 09:34:48 +04:00
|
|
|
};
|
|
|
|
|
2022-07-28 14:50:34 +03:00
|
|
|
GlobalProperty malta_compat[] = {
|
|
|
|
{ "PIIX4_PM", "memory-hotplug-support", "off" },
|
|
|
|
{ "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" },
|
|
|
|
{ "PIIX4_PM", "acpi-root-pci-hotplug", "off" },
|
|
|
|
{ "PIIX4_PM", "x-not-migrate-acpi-index", "true" },
|
|
|
|
};
|
|
|
|
const size_t malta_compat_len = G_N_ELEMENTS(malta_compat);
|
|
|
|
|
2015-09-04 21:37:08 +03:00
|
|
|
static void mips_malta_machine_init(MachineClass *mc)
|
2011-11-29 09:34:48 +04:00
|
|
|
{
|
2015-09-04 21:37:08 +03:00
|
|
|
mc->desc = "MIPS Malta Core LV";
|
|
|
|
mc->init = mips_malta_init;
|
2017-02-15 13:05:40 +03:00
|
|
|
mc->block_default_type = IF_IDE;
|
2015-09-04 21:37:08 +03:00
|
|
|
mc->max_cpus = 16;
|
2020-02-07 19:19:47 +03:00
|
|
|
mc->is_default = true;
|
2017-10-05 16:51:10 +03:00
|
|
|
#ifdef TARGET_MIPS64
|
|
|
|
mc->default_cpu_type = MIPS_CPU_TYPE_NAME("20Kc");
|
|
|
|
#else
|
|
|
|
mc->default_cpu_type = MIPS_CPU_TYPE_NAME("24Kf");
|
|
|
|
#endif
|
2020-02-19 19:09:29 +03:00
|
|
|
mc->default_ram_id = "mips_malta.ram";
|
2022-07-28 14:50:34 +03:00
|
|
|
compat_props_add(mc->compat_props, malta_compat, malta_compat_len);
|
2011-11-29 09:34:48 +04:00
|
|
|
}
|
|
|
|
|
2015-09-04 21:37:08 +03:00
|
|
|
DEFINE_MACHINE("malta", mips_malta_machine_init)
|
|
|
|
|
|
|
|
static void mips_malta_register_types(void)
|
2009-05-21 03:38:09 +04:00
|
|
|
{
|
2015-09-04 21:37:08 +03:00
|
|
|
type_register_static(&mips_malta_device);
|
2009-05-21 03:38:09 +04:00
|
|
|
}
|
|
|
|
|
2012-02-09 18:20:55 +04:00
|
|
|
type_init(mips_malta_register_types)
|