2022-06-06 15:42:52 +03:00
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* QEMU LoongArch CPU
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*
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* Copyright (c) 2021 Loongson Technology Corporation Limited
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*/
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#ifndef LOONGARCH_CPU_H
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#define LOONGARCH_CPU_H
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#include "exec/cpu-defs.h"
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#include "fpu/softfloat-types.h"
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#include "hw/registerfields.h"
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#define TCG_GUEST_DEFAULT_MO (0)
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#define FCSR0_M1 0x1f /* FCSR1 mask, Enables */
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#define FCSR0_M2 0x1f1f0000 /* FCSR2 mask, Cause and Flags */
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#define FCSR0_M3 0x300 /* FCSR3 mask, Round Mode */
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#define FCSR0_RM 8 /* Round Mode bit num on fcsr0 */
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FIELD(FCSR0, ENABLES, 0, 5)
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FIELD(FCSR0, RM, 8, 2)
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FIELD(FCSR0, FLAGS, 16, 5)
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FIELD(FCSR0, CAUSE, 24, 5)
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#define GET_FP_CAUSE(REG) FIELD_EX32(REG, FCSR0, CAUSE)
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#define SET_FP_CAUSE(REG, V) FIELD_DP32(REG, FCSR0, CAUSE, V)
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#define GET_FP_ENABLES(REG) FIELD_EX32(REG, FCSR0, ENABLES)
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#define SET_FP_ENABLES(REG, V) FIELD_DP32(REG, FCSR0, ENABLES, V)
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#define GET_FP_FLAGS(REG) FIELD_EX32(REG, FCSR0, FLAGS)
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#define SET_FP_FLAGS(REG, V) FIELD_DP32(REG, FCSR0, FLAGS, V)
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#define UPDATE_FP_FLAGS(REG, V) \
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do { \
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(REG) |= FIELD_DP32(0, FCSR0, FLAGS, V); \
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} while (0)
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#define FP_INEXACT 1
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#define FP_UNDERFLOW 2
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#define FP_OVERFLOW 4
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#define FP_DIV0 8
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#define FP_INVALID 16
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#define EXCCODE_EXTERNAL_INT 64 /* plus external interrupt number */
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#define EXCCODE_INT 0
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#define EXCCODE_PIL 1
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#define EXCCODE_PIS 2
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#define EXCCODE_PIF 3
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#define EXCCODE_PME 4
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#define EXCCODE_PNR 5
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#define EXCCODE_PNX 6
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#define EXCCODE_PPI 7
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#define EXCCODE_ADEF 8 /* Different exception subcode */
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#define EXCCODE_ADEM 8
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#define EXCCODE_ALE 9
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#define EXCCODE_BCE 10
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#define EXCCODE_SYS 11
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#define EXCCODE_BRK 12
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#define EXCCODE_INE 13
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#define EXCCODE_IPE 14
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#define EXCCODE_FPD 15
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#define EXCCODE_SXD 16
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#define EXCCODE_ASXD 17
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#define EXCCODE_FPE 18 /* Different exception subcode */
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#define EXCCODE_VFPE 18
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#define EXCCODE_WPEF 19 /* Different exception subcode */
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#define EXCCODE_WPEM 19
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#define EXCCODE_BTD 20
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#define EXCCODE_BTE 21
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#define EXCCODE_DBP 26 /* Reserved subcode used for debug */
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/* cpucfg[0] bits */
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FIELD(CPUCFG0, PRID, 0, 32)
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/* cpucfg[1] bits */
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FIELD(CPUCFG1, ARCH, 0, 2)
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FIELD(CPUCFG1, PGMMU, 2, 1)
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FIELD(CPUCFG1, IOCSR, 3, 1)
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FIELD(CPUCFG1, PALEN, 4, 8)
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FIELD(CPUCFG1, VALEN, 12, 8)
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FIELD(CPUCFG1, UAL, 20, 1)
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FIELD(CPUCFG1, RI, 21, 1)
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FIELD(CPUCFG1, EP, 22, 1)
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FIELD(CPUCFG1, RPLV, 23, 1)
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FIELD(CPUCFG1, HP, 24, 1)
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FIELD(CPUCFG1, IOCSR_BRD, 25, 1)
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FIELD(CPUCFG1, MSG_INT, 26, 1)
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/* cpucfg[2] bits */
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FIELD(CPUCFG2, FP, 0, 1)
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FIELD(CPUCFG2, FP_SP, 1, 1)
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FIELD(CPUCFG2, FP_DP, 2, 1)
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FIELD(CPUCFG2, FP_VER, 3, 3)
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FIELD(CPUCFG2, LSX, 6, 1)
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FIELD(CPUCFG2, LASX, 7, 1)
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FIELD(CPUCFG2, COMPLEX, 8, 1)
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FIELD(CPUCFG2, CRYPTO, 9, 1)
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FIELD(CPUCFG2, LVZ, 10, 1)
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FIELD(CPUCFG2, LVZ_VER, 11, 3)
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FIELD(CPUCFG2, LLFTP, 14, 1)
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FIELD(CPUCFG2, LLFTP_VER, 15, 3)
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FIELD(CPUCFG2, LBT_X86, 18, 1)
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FIELD(CPUCFG2, LBT_ARM, 19, 1)
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FIELD(CPUCFG2, LBT_MIPS, 20, 1)
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FIELD(CPUCFG2, LSPW, 21, 1)
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FIELD(CPUCFG2, LAM, 22, 1)
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/* cpucfg[3] bits */
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FIELD(CPUCFG3, CCDMA, 0, 1)
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FIELD(CPUCFG3, SFB, 1, 1)
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FIELD(CPUCFG3, UCACC, 2, 1)
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FIELD(CPUCFG3, LLEXC, 3, 1)
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FIELD(CPUCFG3, SCDLY, 4, 1)
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FIELD(CPUCFG3, LLDBAR, 5, 1)
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FIELD(CPUCFG3, ITLBHMC, 6, 1)
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FIELD(CPUCFG3, ICHMC, 7, 1)
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FIELD(CPUCFG3, SPW_LVL, 8, 3)
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FIELD(CPUCFG3, SPW_HP_HF, 11, 1)
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FIELD(CPUCFG3, RVA, 12, 1)
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FIELD(CPUCFG3, RVAMAX, 13, 4)
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/* cpucfg[4] bits */
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FIELD(CPUCFG4, CC_FREQ, 0, 32)
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/* cpucfg[5] bits */
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FIELD(CPUCFG5, CC_MUL, 0, 16)
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FIELD(CPUCFG5, CC_DIV, 16, 16)
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/* cpucfg[6] bits */
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FIELD(CPUCFG6, PMP, 0, 1)
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FIELD(CPUCFG6, PMVER, 1, 3)
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FIELD(CPUCFG6, PMNUM, 4, 4)
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FIELD(CPUCFG6, PMBITS, 8, 6)
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FIELD(CPUCFG6, UPM, 14, 1)
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/* cpucfg[16] bits */
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FIELD(CPUCFG16, L1_IUPRE, 0, 1)
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FIELD(CPUCFG16, L1_IUUNIFY, 1, 1)
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FIELD(CPUCFG16, L1_DPRE, 2, 1)
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FIELD(CPUCFG16, L2_IUPRE, 3, 1)
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FIELD(CPUCFG16, L2_IUUNIFY, 4, 1)
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FIELD(CPUCFG16, L2_IUPRIV, 5, 1)
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FIELD(CPUCFG16, L2_IUINCL, 6, 1)
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FIELD(CPUCFG16, L2_DPRE, 7, 1)
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FIELD(CPUCFG16, L2_DPRIV, 8, 1)
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FIELD(CPUCFG16, L2_DINCL, 9, 1)
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FIELD(CPUCFG16, L3_IUPRE, 10, 1)
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FIELD(CPUCFG16, L3_IUUNIFY, 11, 1)
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FIELD(CPUCFG16, L3_IUPRIV, 12, 1)
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FIELD(CPUCFG16, L3_IUINCL, 13, 1)
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FIELD(CPUCFG16, L3_DPRE, 14, 1)
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FIELD(CPUCFG16, L3_DPRIV, 15, 1)
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FIELD(CPUCFG16, L3_DINCL, 16, 1)
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/* cpucfg[17] bits */
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FIELD(CPUCFG17, L1IU_WAYS, 0, 16)
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FIELD(CPUCFG17, L1IU_SETS, 16, 8)
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FIELD(CPUCFG17, L1IU_SIZE, 24, 7)
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/* cpucfg[18] bits */
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FIELD(CPUCFG18, L1D_WAYS, 0, 16)
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FIELD(CPUCFG18, L1D_SETS, 16, 8)
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FIELD(CPUCFG18, L1D_SIZE, 24, 7)
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/* cpucfg[19] bits */
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FIELD(CPUCFG19, L2IU_WAYS, 0, 16)
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FIELD(CPUCFG19, L2IU_SETS, 16, 8)
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FIELD(CPUCFG19, L2IU_SIZE, 24, 7)
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/* cpucfg[20] bits */
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FIELD(CPUCFG20, L3IU_WAYS, 0, 16)
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FIELD(CPUCFG20, L3IU_SETS, 16, 8)
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FIELD(CPUCFG20, L3IU_SIZE, 24, 7)
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2022-06-06 15:43:09 +03:00
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/*CSR_CRMD */
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FIELD(CSR_CRMD, PLV, 0, 2)
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FIELD(CSR_CRMD, IE, 2, 1)
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FIELD(CSR_CRMD, DA, 3, 1)
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FIELD(CSR_CRMD, PG, 4, 1)
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FIELD(CSR_CRMD, DATF, 5, 2)
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FIELD(CSR_CRMD, DATM, 7, 2)
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FIELD(CSR_CRMD, WE, 9, 1)
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2022-06-06 15:42:52 +03:00
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extern const char * const regnames[32];
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extern const char * const fregnames[32];
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typedef struct CPUArchState {
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uint64_t gpr[32];
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uint64_t pc;
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uint64_t fpr[32];
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float_status fp_status;
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bool cf[8];
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uint32_t fcsr0;
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uint32_t fcsr0_mask;
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uint32_t cpucfg[21];
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uint64_t lladdr; /* LL virtual address compared against SC */
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uint64_t llval;
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uint64_t badaddr;
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2022-06-06 15:43:09 +03:00
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/* LoongArch CSRs */
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uint64_t CSR_CRMD;
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uint64_t CSR_PRMD;
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uint64_t CSR_EUEN;
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uint64_t CSR_MISC;
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uint64_t CSR_ECFG;
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uint64_t CSR_ESTAT;
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uint64_t CSR_ERA;
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uint64_t CSR_BADV;
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uint64_t CSR_BADI;
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uint64_t CSR_EENTRY;
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uint64_t CSR_TLBIDX;
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uint64_t CSR_TLBEHI;
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uint64_t CSR_TLBELO0;
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uint64_t CSR_TLBELO1;
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uint64_t CSR_ASID;
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uint64_t CSR_PGDL;
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uint64_t CSR_PGDH;
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uint64_t CSR_PGD;
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uint64_t CSR_PWCL;
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uint64_t CSR_PWCH;
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uint64_t CSR_STLBPS;
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uint64_t CSR_RVACFG;
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uint64_t CSR_PRCFG1;
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uint64_t CSR_PRCFG2;
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uint64_t CSR_PRCFG3;
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uint64_t CSR_SAVE[16];
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uint64_t CSR_TID;
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uint64_t CSR_TCFG;
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uint64_t CSR_TVAL;
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uint64_t CSR_CNTC;
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uint64_t CSR_TICLR;
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uint64_t CSR_LLBCTL;
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uint64_t CSR_IMPCTL1;
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uint64_t CSR_IMPCTL2;
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uint64_t CSR_TLBRENTRY;
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uint64_t CSR_TLBRBADV;
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uint64_t CSR_TLBRERA;
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uint64_t CSR_TLBRSAVE;
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uint64_t CSR_TLBRELO0;
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uint64_t CSR_TLBRELO1;
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uint64_t CSR_TLBREHI;
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uint64_t CSR_TLBRPRMD;
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uint64_t CSR_MERRCTL;
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uint64_t CSR_MERRINFO1;
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uint64_t CSR_MERRINFO2;
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uint64_t CSR_MERRENTRY;
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uint64_t CSR_MERRERA;
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uint64_t CSR_MERRSAVE;
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uint64_t CSR_CTAG;
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uint64_t CSR_DMW[4];
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uint64_t CSR_DBG;
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uint64_t CSR_DERA;
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uint64_t CSR_DSAVE;
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2022-06-06 15:42:52 +03:00
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} CPULoongArchState;
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/**
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* LoongArchCPU:
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* @env: #CPULoongArchState
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*
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* A LoongArch CPU.
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*/
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struct ArchCPU {
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/*< private >*/
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CPUState parent_obj;
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/*< public >*/
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CPUNegativeOffsetState neg;
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CPULoongArchState env;
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};
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#define TYPE_LOONGARCH_CPU "loongarch-cpu"
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OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass,
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LOONGARCH_CPU)
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/**
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* LoongArchCPUClass:
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* @parent_realize: The parent class' realize handler.
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* @parent_reset: The parent class' reset handler.
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*
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* A LoongArch CPU model.
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*/
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struct LoongArchCPUClass {
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/*< private >*/
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CPUClass parent_class;
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/*< public >*/
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DeviceRealize parent_realize;
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DeviceReset parent_reset;
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};
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void loongarch_cpu_list(void);
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#define cpu_list loongarch_cpu_list
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#include "exec/cpu-all.h"
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#define LOONGARCH_CPU_TYPE_SUFFIX "-" TYPE_LOONGARCH_CPU
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#define LOONGARCH_CPU_TYPE_NAME(model) model LOONGARCH_CPU_TYPE_SUFFIX
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#define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU
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#endif /* LOONGARCH_CPU_H */
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