258 lines
9.5 KiB
C
258 lines
9.5 KiB
C
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/*
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* MIPS TLB (Translation lookaside buffer) helpers.
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*
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* Copyright (c) 2004-2005 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "../internal.h"
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static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx)
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{
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/*
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* Interpret access control mode and mmu_idx.
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* AdE? TLB?
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* AM K S U E K S U E
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* UK 0 0 1 1 0 0 - - 0
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* MK 1 0 1 1 0 1 - - !eu
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* MSK 2 0 0 1 0 1 1 - !eu
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* MUSK 3 0 0 0 0 1 1 1 !eu
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* MUSUK 4 0 0 0 0 0 1 1 0
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* USK 5 0 0 1 0 0 0 - 0
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* - 6 - - - - - - - -
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* UUSK 7 0 0 0 0 0 0 0 0
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*/
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int32_t adetlb_mask;
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switch (mmu_idx) {
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case 3: /* ERL */
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/* If EU is set, always unmapped */
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if (eu) {
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return 0;
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}
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/* fall through */
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case MIPS_HFLAG_KM:
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/* Never AdE, TLB mapped if AM={1,2,3} */
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adetlb_mask = 0x70000000;
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goto check_tlb;
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case MIPS_HFLAG_SM:
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/* AdE if AM={0,1}, TLB mapped if AM={2,3,4} */
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adetlb_mask = 0xc0380000;
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goto check_ade;
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case MIPS_HFLAG_UM:
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/* AdE if AM={0,1,2,5}, TLB mapped if AM={3,4} */
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adetlb_mask = 0xe4180000;
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/* fall through */
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check_ade:
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/* does this AM cause AdE in current execution mode */
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if ((adetlb_mask << am) < 0) {
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return TLBRET_BADADDR;
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}
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adetlb_mask <<= 8;
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/* fall through */
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check_tlb:
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/* is this AM mapped in current execution mode */
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return ((adetlb_mask << am) < 0);
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default:
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assert(0);
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return TLBRET_BADADDR;
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};
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}
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static int get_seg_physical_address(CPUMIPSState *env, hwaddr *physical,
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int *prot, target_ulong real_address,
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MMUAccessType access_type, int mmu_idx,
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unsigned int am, bool eu,
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target_ulong segmask,
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hwaddr physical_base)
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{
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int mapped = is_seg_am_mapped(am, eu, mmu_idx);
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if (mapped < 0) {
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/* is_seg_am_mapped can report TLBRET_BADADDR */
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return mapped;
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} else if (mapped) {
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/* The segment is TLB mapped */
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return env->tlb->map_address(env, physical, prot, real_address,
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access_type);
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} else {
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/* The segment is unmapped */
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*physical = physical_base | (real_address & segmask);
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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return TLBRET_MATCH;
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}
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}
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static int get_segctl_physical_address(CPUMIPSState *env, hwaddr *physical,
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int *prot, target_ulong real_address,
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MMUAccessType access_type, int mmu_idx,
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uint16_t segctl, target_ulong segmask)
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{
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unsigned int am = (segctl & CP0SC_AM_MASK) >> CP0SC_AM;
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bool eu = (segctl >> CP0SC_EU) & 1;
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hwaddr pa = ((hwaddr)segctl & CP0SC_PA_MASK) << 20;
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return get_seg_physical_address(env, physical, prot, real_address,
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access_type, mmu_idx, am, eu, segmask,
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pa & ~(hwaddr)segmask);
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}
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int get_physical_address(CPUMIPSState *env, hwaddr *physical,
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int *prot, target_ulong real_address,
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MMUAccessType access_type, int mmu_idx)
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{
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/* User mode can only access useg/xuseg */
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#if defined(TARGET_MIPS64)
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int user_mode = mmu_idx == MIPS_HFLAG_UM;
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int supervisor_mode = mmu_idx == MIPS_HFLAG_SM;
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int kernel_mode = !user_mode && !supervisor_mode;
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int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
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int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
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int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
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#endif
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int ret = TLBRET_MATCH;
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/* effective address (modified for KVM T&E kernel segments) */
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target_ulong address = real_address;
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if (mips_um_ksegs_enabled()) {
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/* KVM T&E adds guest kernel segments in useg */
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if (real_address >= KVM_KSEG0_BASE) {
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if (real_address < KVM_KSEG2_BASE) {
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/* kseg0 */
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address += KSEG0_BASE - KVM_KSEG0_BASE;
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} else if (real_address <= USEG_LIMIT) {
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/* kseg2/3 */
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address += KSEG2_BASE - KVM_KSEG2_BASE;
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}
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}
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}
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if (address <= USEG_LIMIT) {
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/* useg */
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uint16_t segctl;
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if (address >= 0x40000000UL) {
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segctl = env->CP0_SegCtl2;
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} else {
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segctl = env->CP0_SegCtl2 >> 16;
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}
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ret = get_segctl_physical_address(env, physical, prot,
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real_address, access_type,
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mmu_idx, segctl, 0x3FFFFFFF);
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#if defined(TARGET_MIPS64)
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} else if (address < 0x4000000000000000ULL) {
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/* xuseg */
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if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
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ret = env->tlb->map_address(env, physical, prot,
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real_address, access_type);
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} else {
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ret = TLBRET_BADADDR;
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}
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} else if (address < 0x8000000000000000ULL) {
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/* xsseg */
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if ((supervisor_mode || kernel_mode) &&
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SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
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ret = env->tlb->map_address(env, physical, prot,
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real_address, access_type);
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} else {
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ret = TLBRET_BADADDR;
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}
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} else if (address < 0xC000000000000000ULL) {
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/* xkphys */
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if ((address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
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/* KX/SX/UX bit to check for each xkphys EVA access mode */
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static const uint8_t am_ksux[8] = {
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[CP0SC_AM_UK] = (1u << CP0St_KX),
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[CP0SC_AM_MK] = (1u << CP0St_KX),
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[CP0SC_AM_MSK] = (1u << CP0St_SX),
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[CP0SC_AM_MUSK] = (1u << CP0St_UX),
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[CP0SC_AM_MUSUK] = (1u << CP0St_UX),
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[CP0SC_AM_USK] = (1u << CP0St_SX),
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[6] = (1u << CP0St_KX),
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[CP0SC_AM_UUSK] = (1u << CP0St_UX),
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};
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unsigned int am = CP0SC_AM_UK;
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unsigned int xr = (env->CP0_SegCtl2 & CP0SC2_XR_MASK) >> CP0SC2_XR;
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if (xr & (1 << ((address >> 59) & 0x7))) {
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am = (env->CP0_SegCtl1 & CP0SC1_XAM_MASK) >> CP0SC1_XAM;
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}
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/* Does CP0_Status.KX/SX/UX permit the access mode (am) */
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if (env->CP0_Status & am_ksux[am]) {
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ret = get_seg_physical_address(env, physical, prot,
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real_address, access_type,
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mmu_idx, am, false, env->PAMask,
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0);
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} else {
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ret = TLBRET_BADADDR;
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}
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} else {
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ret = TLBRET_BADADDR;
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}
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} else if (address < 0xFFFFFFFF80000000ULL) {
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/* xkseg */
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if (kernel_mode && KX &&
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address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
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ret = env->tlb->map_address(env, physical, prot,
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real_address, access_type);
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} else {
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ret = TLBRET_BADADDR;
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}
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#endif
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} else if (address < KSEG1_BASE) {
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/* kseg0 */
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ret = get_segctl_physical_address(env, physical, prot, real_address,
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access_type, mmu_idx,
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env->CP0_SegCtl1 >> 16, 0x1FFFFFFF);
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} else if (address < KSEG2_BASE) {
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/* kseg1 */
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ret = get_segctl_physical_address(env, physical, prot, real_address,
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access_type, mmu_idx,
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env->CP0_SegCtl1, 0x1FFFFFFF);
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} else if (address < KSEG3_BASE) {
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/* sseg (kseg2) */
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ret = get_segctl_physical_address(env, physical, prot, real_address,
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access_type, mmu_idx,
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env->CP0_SegCtl0 >> 16, 0x1FFFFFFF);
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} else {
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/*
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* kseg3
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* XXX: debug segment is not emulated
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*/
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ret = get_segctl_physical_address(env, physical, prot, real_address,
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access_type, mmu_idx,
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env->CP0_SegCtl0, 0x1FFFFFFF);
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}
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return ret;
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}
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hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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{
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MIPSCPU *cpu = MIPS_CPU(cs);
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CPUMIPSState *env = &cpu->env;
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hwaddr phys_addr;
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int prot;
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if (get_physical_address(env, &phys_addr, &prot, addr, MMU_DATA_LOAD,
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cpu_mmu_index(env, false)) != 0) {
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return -1;
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}
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return phys_addr;
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}
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