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qemu/hw/microblaze/xlnx-zynqmp-pmu.c

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xlnx-zynqmp-pmu: Initial commit of the ZynqMP PMU The Xilinx ZynqMP SoC has two main processing systems in it. The ARM processing system (which is already modeled in QEMU) and the MicroBlaze Power Management Unit (PMU). This is the inital work for adding support for the PMU. The PMU susbsystem runs along side the ARM system on hardware, but due to architecture limitations in QEMU the two instances are seperate for the time being. Let's follow the same setup we do with the ARM system, where there is an SoC device and a ZCU102 board. Although the PMU is less board specific we are still going to follow the same split as maybe in future we can connect the PMU device to the ARM ZCU102 board. As the machine will be fairly small let's keep them both together in one file. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:20 +03:00
/*
* Xilinx Zynq MPSoC PMU (Power Management Unit) emulation
*
* Copyright (C) 2017 Xilinx Inc
* Written by Alistair Francis <alistair.francis@xilinx.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu-common.h"
xlnx-zynqmp-pmu: Add the CPU and memory Connect the MicroBlaze CPU and the ROM and RAM memory regions. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:25 +03:00
#include "exec/address-spaces.h"
xlnx-zynqmp-pmu: Initial commit of the ZynqMP PMU The Xilinx ZynqMP SoC has two main processing systems in it. The ARM processing system (which is already modeled in QEMU) and the MicroBlaze Power Management Unit (PMU). This is the inital work for adding support for the PMU. The PMU susbsystem runs along side the ARM system on hardware, but due to architecture limitations in QEMU the two instances are seperate for the time being. Let's follow the same setup we do with the ARM system, where there is an SoC device and a ZCU102 board. Although the PMU is less board specific we are still going to follow the same split as maybe in future we can connect the PMU device to the ARM ZCU102 board. As the machine will be fairly small let's keep them both together in one file. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:20 +03:00
#include "hw/boards.h"
xlnx-zynqmp-pmu: Add the CPU and memory Connect the MicroBlaze CPU and the ROM and RAM memory regions. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:25 +03:00
#include "hw/qdev-properties.h"
xlnx-zynqmp-pmu: Initial commit of the ZynqMP PMU The Xilinx ZynqMP SoC has two main processing systems in it. The ARM processing system (which is already modeled in QEMU) and the MicroBlaze Power Management Unit (PMU). This is the inital work for adding support for the PMU. The PMU susbsystem runs along side the ARM system on hardware, but due to architecture limitations in QEMU the two instances are seperate for the time being. Let's follow the same setup we do with the ARM system, where there is an SoC device and a ZCU102 board. Although the PMU is less board specific we are still going to follow the same split as maybe in future we can connect the PMU device to the ARM ZCU102 board. As the machine will be fairly small let's keep them both together in one file. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:20 +03:00
#include "cpu.h"
xlnx-zynqmp-pmu: Add the CPU and memory Connect the MicroBlaze CPU and the ROM and RAM memory regions. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:25 +03:00
#include "boot.h"
xlnx-zynqmp-pmu: Initial commit of the ZynqMP PMU The Xilinx ZynqMP SoC has two main processing systems in it. The ARM processing system (which is already modeled in QEMU) and the MicroBlaze Power Management Unit (PMU). This is the inital work for adding support for the PMU. The PMU susbsystem runs along side the ARM system on hardware, but due to architecture limitations in QEMU the two instances are seperate for the time being. Let's follow the same setup we do with the ARM system, where there is an SoC device and a ZCU102 board. Although the PMU is less board specific we are still going to follow the same split as maybe in future we can connect the PMU device to the ARM ZCU102 board. As the machine will be fairly small let's keep them both together in one file. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:20 +03:00
xlnx-zynqmp-pmu: Connect the IPI device to the PMU Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:48 +03:00
#include "hw/intc/xlnx-zynqmp-ipi.h"
xlnx-zynqmp-pmu: Connect the PMU interrupt controller Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:38 +03:00
#include "hw/intc/xlnx-pmu-iomod-intc.h"
xlnx-zynqmp-pmu: Initial commit of the ZynqMP PMU The Xilinx ZynqMP SoC has two main processing systems in it. The ARM processing system (which is already modeled in QEMU) and the MicroBlaze Power Management Unit (PMU). This is the inital work for adding support for the PMU. The PMU susbsystem runs along side the ARM system on hardware, but due to architecture limitations in QEMU the two instances are seperate for the time being. Let's follow the same setup we do with the ARM system, where there is an SoC device and a ZCU102 board. Although the PMU is less board specific we are still going to follow the same split as maybe in future we can connect the PMU device to the ARM ZCU102 board. As the machine will be fairly small let's keep them both together in one file. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:20 +03:00
/* Define the PMU device */
#define TYPE_XLNX_ZYNQMP_PMU_SOC "xlnx,zynqmp-pmu-soc"
#define XLNX_ZYNQMP_PMU_SOC(obj) OBJECT_CHECK(XlnxZynqMPPMUSoCState, (obj), \
TYPE_XLNX_ZYNQMP_PMU_SOC)
xlnx-zynqmp-pmu: Add the CPU and memory Connect the MicroBlaze CPU and the ROM and RAM memory regions. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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#define XLNX_ZYNQMP_PMU_ROM_SIZE 0x8000
#define XLNX_ZYNQMP_PMU_ROM_ADDR 0xFFD00000
#define XLNX_ZYNQMP_PMU_RAM_ADDR 0xFFDC0000
xlnx-zynqmp-pmu: Connect the PMU interrupt controller Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:38 +03:00
#define XLNX_ZYNQMP_PMU_INTC_ADDR 0xFFD40000
xlnx-zynqmp-pmu: Connect the IPI device to the PMU Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:48 +03:00
#define XLNX_ZYNQMP_PMU_NUM_IPIS 4
static const uint64_t ipi_addr[XLNX_ZYNQMP_PMU_NUM_IPIS] = {
0xFF340000, 0xFF350000, 0xFF360000, 0xFF370000,
};
static const uint64_t ipi_irq[XLNX_ZYNQMP_PMU_NUM_IPIS] = {
19, 20, 21, 22,
};
xlnx-zynqmp-pmu: Initial commit of the ZynqMP PMU The Xilinx ZynqMP SoC has two main processing systems in it. The ARM processing system (which is already modeled in QEMU) and the MicroBlaze Power Management Unit (PMU). This is the inital work for adding support for the PMU. The PMU susbsystem runs along side the ARM system on hardware, but due to architecture limitations in QEMU the two instances are seperate for the time being. Let's follow the same setup we do with the ARM system, where there is an SoC device and a ZCU102 board. Although the PMU is less board specific we are still going to follow the same split as maybe in future we can connect the PMU device to the ARM ZCU102 board. As the machine will be fairly small let's keep them both together in one file. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:20 +03:00
typedef struct XlnxZynqMPPMUSoCState {
/*< private >*/
DeviceState parent_obj;
/*< public >*/
xlnx-zynqmp-pmu: Add the CPU and memory Connect the MicroBlaze CPU and the ROM and RAM memory regions. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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MicroBlazeCPU cpu;
xlnx-zynqmp-pmu: Connect the PMU interrupt controller Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:38 +03:00
XlnxPMUIOIntc intc;
xlnx-zynqmp-pmu: Initial commit of the ZynqMP PMU The Xilinx ZynqMP SoC has two main processing systems in it. The ARM processing system (which is already modeled in QEMU) and the MicroBlaze Power Management Unit (PMU). This is the inital work for adding support for the PMU. The PMU susbsystem runs along side the ARM system on hardware, but due to architecture limitations in QEMU the two instances are seperate for the time being. Let's follow the same setup we do with the ARM system, where there is an SoC device and a ZCU102 board. Although the PMU is less board specific we are still going to follow the same split as maybe in future we can connect the PMU device to the ARM ZCU102 board. As the machine will be fairly small let's keep them both together in one file. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:20 +03:00
} XlnxZynqMPPMUSoCState;
xlnx-zynqmp-pmu: Connect the PMU interrupt controller Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:38 +03:00
xlnx-zynqmp-pmu: Initial commit of the ZynqMP PMU The Xilinx ZynqMP SoC has two main processing systems in it. The ARM processing system (which is already modeled in QEMU) and the MicroBlaze Power Management Unit (PMU). This is the inital work for adding support for the PMU. The PMU susbsystem runs along side the ARM system on hardware, but due to architecture limitations in QEMU the two instances are seperate for the time being. Let's follow the same setup we do with the ARM system, where there is an SoC device and a ZCU102 board. Although the PMU is less board specific we are still going to follow the same split as maybe in future we can connect the PMU device to the ARM ZCU102 board. As the machine will be fairly small let's keep them both together in one file. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:20 +03:00
static void xlnx_zynqmp_pmu_soc_init(Object *obj)
{
xlnx-zynqmp-pmu: Add the CPU and memory Connect the MicroBlaze CPU and the ROM and RAM memory regions. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:25 +03:00
XlnxZynqMPPMUSoCState *s = XLNX_ZYNQMP_PMU_SOC(obj);
xlnx-zynqmp-pmu: Initial commit of the ZynqMP PMU The Xilinx ZynqMP SoC has two main processing systems in it. The ARM processing system (which is already modeled in QEMU) and the MicroBlaze Power Management Unit (PMU). This is the inital work for adding support for the PMU. The PMU susbsystem runs along side the ARM system on hardware, but due to architecture limitations in QEMU the two instances are seperate for the time being. Let's follow the same setup we do with the ARM system, where there is an SoC device and a ZCU102 board. Although the PMU is less board specific we are still going to follow the same split as maybe in future we can connect the PMU device to the ARM ZCU102 board. As the machine will be fairly small let's keep them both together in one file. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:20 +03:00
xlnx-zynqmp-pmu: Add the CPU and memory Connect the MicroBlaze CPU and the ROM and RAM memory regions. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:25 +03:00
object_initialize(&s->cpu, sizeof(s->cpu),
TYPE_MICROBLAZE_CPU);
object_property_add_child(obj, "pmu-cpu", OBJECT(&s->cpu),
&error_abort);
xlnx-zynqmp-pmu: Connect the PMU interrupt controller Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:38 +03:00
object_initialize(&s->intc, sizeof(s->intc), TYPE_XLNX_PMU_IO_INTC);
qdev_set_parent_bus(DEVICE(&s->intc), sysbus_get_default());
xlnx-zynqmp-pmu: Initial commit of the ZynqMP PMU The Xilinx ZynqMP SoC has two main processing systems in it. The ARM processing system (which is already modeled in QEMU) and the MicroBlaze Power Management Unit (PMU). This is the inital work for adding support for the PMU. The PMU susbsystem runs along side the ARM system on hardware, but due to architecture limitations in QEMU the two instances are seperate for the time being. Let's follow the same setup we do with the ARM system, where there is an SoC device and a ZCU102 board. Although the PMU is less board specific we are still going to follow the same split as maybe in future we can connect the PMU device to the ARM ZCU102 board. As the machine will be fairly small let's keep them both together in one file. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:20 +03:00
}
static void xlnx_zynqmp_pmu_soc_realize(DeviceState *dev, Error **errp)
{
xlnx-zynqmp-pmu: Add the CPU and memory Connect the MicroBlaze CPU and the ROM and RAM memory regions. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:25 +03:00
XlnxZynqMPPMUSoCState *s = XLNX_ZYNQMP_PMU_SOC(dev);
Error *err = NULL;
object_property_set_uint(OBJECT(&s->cpu), XLNX_ZYNQMP_PMU_ROM_ADDR,
"base-vectors", &error_abort);
object_property_set_bool(OBJECT(&s->cpu), true, "use-stack-protection",
&error_abort);
object_property_set_uint(OBJECT(&s->cpu), 0, "use-fpu", &error_abort);
object_property_set_uint(OBJECT(&s->cpu), 0, "use-hw-mul", &error_abort);
object_property_set_bool(OBJECT(&s->cpu), true, "use-barrel",
&error_abort);
object_property_set_bool(OBJECT(&s->cpu), true, "use-msr-instr",
&error_abort);
object_property_set_bool(OBJECT(&s->cpu), true, "use-pcmp-instr",
&error_abort);
object_property_set_bool(OBJECT(&s->cpu), false, "use-mmu", &error_abort);
object_property_set_bool(OBJECT(&s->cpu), true, "endianness",
&error_abort);
object_property_set_str(OBJECT(&s->cpu), "8.40.b", "version",
&error_abort);
object_property_set_uint(OBJECT(&s->cpu), 0, "pvr", &error_abort);
object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
xlnx-zynqmp-pmu: Connect the PMU interrupt controller Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:38 +03:00
object_property_set_uint(OBJECT(&s->intc), 0x10, "intc-intr-size",
&error_abort);
object_property_set_uint(OBJECT(&s->intc), 0x0, "intc-level-edge",
&error_abort);
object_property_set_uint(OBJECT(&s->intc), 0xffff, "intc-positive",
&error_abort);
object_property_set_bool(OBJECT(&s->intc), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->intc), 0, XLNX_ZYNQMP_PMU_INTC_ADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->intc), 0,
qdev_get_gpio_in(DEVICE(&s->cpu), MB_CPU_IRQ));
xlnx-zynqmp-pmu: Initial commit of the ZynqMP PMU The Xilinx ZynqMP SoC has two main processing systems in it. The ARM processing system (which is already modeled in QEMU) and the MicroBlaze Power Management Unit (PMU). This is the inital work for adding support for the PMU. The PMU susbsystem runs along side the ARM system on hardware, but due to architecture limitations in QEMU the two instances are seperate for the time being. Let's follow the same setup we do with the ARM system, where there is an SoC device and a ZCU102 board. Although the PMU is less board specific we are still going to follow the same split as maybe in future we can connect the PMU device to the ARM ZCU102 board. As the machine will be fairly small let's keep them both together in one file. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:20 +03:00
}
static void xlnx_zynqmp_pmu_soc_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
dc->realize = xlnx_zynqmp_pmu_soc_realize;
}
static const TypeInfo xlnx_zynqmp_pmu_soc_type_info = {
.name = TYPE_XLNX_ZYNQMP_PMU_SOC,
.parent = TYPE_DEVICE,
.instance_size = sizeof(XlnxZynqMPPMUSoCState),
.instance_init = xlnx_zynqmp_pmu_soc_init,
.class_init = xlnx_zynqmp_pmu_soc_class_init,
};
static void xlnx_zynqmp_pmu_soc_register_types(void)
{
type_register_static(&xlnx_zynqmp_pmu_soc_type_info);
}
type_init(xlnx_zynqmp_pmu_soc_register_types)
/* Define the PMU Machine */
static void xlnx_zynqmp_pmu_init(MachineState *machine)
{
xlnx-zynqmp-pmu: Add the CPU and memory Connect the MicroBlaze CPU and the ROM and RAM memory regions. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:25 +03:00
XlnxZynqMPPMUSoCState *pmu = g_new0(XlnxZynqMPPMUSoCState, 1);
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *pmu_rom = g_new(MemoryRegion, 1);
MemoryRegion *pmu_ram = g_new(MemoryRegion, 1);
xlnx-zynqmp-pmu: Connect the IPI device to the PMU Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:48 +03:00
XlnxZynqMPIPI *ipi[XLNX_ZYNQMP_PMU_NUM_IPIS];
qemu_irq irq[32];
int i;
xlnx-zynqmp-pmu: Add the CPU and memory Connect the MicroBlaze CPU and the ROM and RAM memory regions. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:25 +03:00
/* Create the ROM */
memory_region_init_rom(pmu_rom, NULL, "xlnx-zynqmp-pmu.rom",
XLNX_ZYNQMP_PMU_ROM_SIZE, &error_fatal);
memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_ROM_ADDR,
pmu_rom);
/* Create the RAM */
memory_region_init_ram(pmu_ram, NULL, "xlnx-zynqmp-pmu.ram",
machine->ram_size, &error_fatal);
memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_RAM_ADDR,
pmu_ram);
/* Create the PMU device */
object_initialize(pmu, sizeof(XlnxZynqMPPMUSoCState), TYPE_XLNX_ZYNQMP_PMU_SOC);
object_property_add_child(OBJECT(machine), "pmu", OBJECT(pmu),
&error_abort);
object_property_set_bool(OBJECT(pmu), true, "realized", &error_fatal);
xlnx-zynqmp-pmu: Connect the IPI device to the PMU Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:48 +03:00
for (i = 0; i < 32; i++) {
irq[i] = qdev_get_gpio_in(DEVICE(&pmu->intc), i);
}
/* Create and connect the IPI device */
for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {
ipi[i] = g_new0(XlnxZynqMPIPI, 1);
object_initialize(ipi[i], sizeof(XlnxZynqMPIPI), TYPE_XLNX_ZYNQMP_IPI);
qdev_set_parent_bus(DEVICE(ipi[i]), sysbus_get_default());
}
for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {
object_property_set_bool(OBJECT(ipi[i]), true, "realized",
&error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(ipi[i]), 0, ipi_addr[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(ipi[i]), 0, irq[ipi_irq[i]]);
}
xlnx-zynqmp-pmu: Add the CPU and memory Connect the MicroBlaze CPU and the ROM and RAM memory regions. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:25 +03:00
/* Load the kernel */
microblaze_load_kernel(&pmu->cpu, XLNX_ZYNQMP_PMU_RAM_ADDR,
machine->ram_size,
machine->initrd_filename,
machine->dtb,
NULL);
xlnx-zynqmp-pmu: Initial commit of the ZynqMP PMU The Xilinx ZynqMP SoC has two main processing systems in it. The ARM processing system (which is already modeled in QEMU) and the MicroBlaze Power Management Unit (PMU). This is the inital work for adding support for the PMU. The PMU susbsystem runs along side the ARM system on hardware, but due to architecture limitations in QEMU the two instances are seperate for the time being. Let's follow the same setup we do with the ARM system, where there is an SoC device and a ZCU102 board. Although the PMU is less board specific we are still going to follow the same split as maybe in future we can connect the PMU device to the ARM ZCU102 board. As the machine will be fairly small let's keep them both together in one file. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-22 22:43:20 +03:00
}
static void xlnx_zynqmp_pmu_machine_init(MachineClass *mc)
{
mc->desc = "Xilinx ZynqMP PMU machine";
mc->init = xlnx_zynqmp_pmu_init;
}
DEFINE_MACHINE("xlnx-zynqmp-pmu", xlnx_zynqmp_pmu_machine_init)
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