111 lines
3.5 KiB
C
111 lines
3.5 KiB
C
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/*
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* QEMU lowRISC Ibex UART device
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*
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* Copyright (c) 2020 Western Digital
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef HW_IBEX_UART_H
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#define HW_IBEX_UART_H
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#include "hw/sysbus.h"
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#include "chardev/char-fe.h"
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#include "qemu/timer.h"
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#define IBEX_UART_INTR_STATE 0x00
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#define INTR_STATE_TX_WATERMARK (1 << 0)
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#define INTR_STATE_RX_WATERMARK (1 << 1)
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#define INTR_STATE_TX_EMPTY (1 << 2)
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#define INTR_STATE_RX_OVERFLOW (1 << 3)
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#define IBEX_UART_INTR_ENABLE 0x04
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#define IBEX_UART_INTR_TEST 0x08
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#define IBEX_UART_CTRL 0x0c
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#define UART_CTRL_TX_ENABLE (1 << 0)
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#define UART_CTRL_RX_ENABLE (1 << 1)
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#define UART_CTRL_NF (1 << 2)
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#define UART_CTRL_SLPBK (1 << 4)
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#define UART_CTRL_LLPBK (1 << 5)
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#define UART_CTRL_PARITY_EN (1 << 6)
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#define UART_CTRL_PARITY_ODD (1 << 7)
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#define UART_CTRL_RXBLVL (3 << 8)
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#define UART_CTRL_NCO (0xFFFF << 16)
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#define IBEX_UART_STATUS 0x10
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#define UART_STATUS_TXFULL (1 << 0)
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#define UART_STATUS_RXFULL (1 << 1)
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#define UART_STATUS_TXEMPTY (1 << 2)
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#define UART_STATUS_RXIDLE (1 << 4)
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#define UART_STATUS_RXEMPTY (1 << 5)
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#define IBEX_UART_RDATA 0x14
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#define IBEX_UART_WDATA 0x18
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#define IBEX_UART_FIFO_CTRL 0x1c
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#define FIFO_CTRL_RXRST (1 << 0)
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#define FIFO_CTRL_TXRST (1 << 1)
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#define FIFO_CTRL_RXILVL (7 << 2)
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#define FIFO_CTRL_RXILVL_SHIFT (2)
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#define FIFO_CTRL_TXILVL (3 << 5)
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#define FIFO_CTRL_TXILVL_SHIFT (5)
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#define IBEX_UART_FIFO_STATUS 0x20
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#define IBEX_UART_OVRD 0x24
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#define IBEX_UART_VAL 0x28
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#define IBEX_UART_TIMEOUT_CTRL 0x2c
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#define IBEX_UART_TX_FIFO_SIZE 16
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#define TYPE_IBEX_UART "ibex-uart"
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#define IBEX_UART(obj) \
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OBJECT_CHECK(IbexUartState, (obj), TYPE_IBEX_UART)
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typedef struct {
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/* <private> */
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SysBusDevice parent_obj;
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/* <public> */
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MemoryRegion mmio;
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uint8_t tx_fifo[IBEX_UART_TX_FIFO_SIZE];
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uint32_t tx_level;
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QEMUTimer *fifo_trigger_handle;
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uint64_t char_tx_time;
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uint32_t uart_intr_state;
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uint32_t uart_intr_enable;
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uint32_t uart_ctrl;
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uint32_t uart_status;
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uint32_t uart_rdata;
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uint32_t uart_fifo_ctrl;
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uint32_t uart_fifo_status;
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uint32_t uart_ovrd;
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uint32_t uart_val;
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uint32_t uart_timeout_ctrl;
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CharBackend chr;
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qemu_irq tx_watermark;
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qemu_irq rx_watermark;
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qemu_irq tx_empty;
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qemu_irq rx_overflow;
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} IbexUartState;
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#endif /* HW_IBEX_UART_H */
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