2012-11-15 00:54:06 +04:00
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/*
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* QEMU MCH/ICH9 PCI Bridge Emulation
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*
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* Copyright (c) 2006 Fabrice Bellard
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* Copyright (c) 2009, 2010, 2011
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* Isaku Yamahata <yamahata at valinux co jp>
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* VA Linux Systems Japan K.K.
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* Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
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*
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2014-08-11 12:10:25 +04:00
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* This is based on piix.c, but heavily modified.
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2012-11-15 00:54:06 +04:00
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2013-02-04 18:40:22 +04:00
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#include "hw/hw.h"
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2013-02-05 20:06:20 +04:00
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#include "hw/pci-host/q35.h"
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2013-07-29 18:47:57 +04:00
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#include "qapi/visitor.h"
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2012-11-15 00:54:06 +04:00
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/****************************************************************************
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* Q35 host
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*/
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2013-07-01 14:18:23 +04:00
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static void q35_host_realize(DeviceState *dev, Error **errp)
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2012-11-15 00:54:06 +04:00
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{
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2013-07-01 14:18:22 +04:00
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PCIHostState *pci = PCI_HOST_BRIDGE(dev);
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Q35PCIHost *s = Q35_HOST_DEVICE(dev);
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2013-07-01 14:18:23 +04:00
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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2012-11-15 00:54:06 +04:00
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2013-07-01 14:18:23 +04:00
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sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem);
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sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4);
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2012-11-15 00:54:06 +04:00
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2013-07-01 14:18:23 +04:00
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sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem);
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sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4);
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2012-11-15 00:54:06 +04:00
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2013-07-01 14:18:22 +04:00
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pci->bus = pci_bus_new(DEVICE(s), "pcie.0",
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s->mch.pci_address_space, s->mch.address_space_io,
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0, TYPE_PCIE_BUS);
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qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus));
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2012-11-15 00:54:06 +04:00
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qdev_init_nofail(DEVICE(&s->mch));
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}
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2013-06-06 12:48:49 +04:00
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static const char *q35_host_root_bus_path(PCIHostState *host_bridge,
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PCIBus *rootbus)
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{
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2013-11-06 03:46:27 +04:00
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Q35PCIHost *s = Q35_HOST_DEVICE(host_bridge);
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/* For backwards compat with old device paths */
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if (s->mch.short_root_bus) {
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return "0000";
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}
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return "0000:00";
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2013-06-06 12:48:49 +04:00
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}
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2013-07-29 18:47:57 +04:00
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static void q35_host_get_pci_hole_start(Object *obj, Visitor *v,
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void *opaque, const char *name,
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Error **errp)
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{
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Q35PCIHost *s = Q35_HOST_DEVICE(obj);
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uint32_t value = s->mch.pci_info.w32.begin;
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visit_type_uint32(v, &value, name, errp);
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}
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static void q35_host_get_pci_hole_end(Object *obj, Visitor *v,
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void *opaque, const char *name,
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Error **errp)
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{
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Q35PCIHost *s = Q35_HOST_DEVICE(obj);
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uint32_t value = s->mch.pci_info.w32.end;
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visit_type_uint32(v, &value, name, errp);
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}
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static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v,
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void *opaque, const char *name,
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Error **errp)
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{
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2013-09-02 13:57:36 +04:00
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PCIHostState *h = PCI_HOST_BRIDGE(obj);
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Range w64;
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pci_bus_get_w64_range(h->bus, &w64);
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2013-07-29 18:47:57 +04:00
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2013-09-02 13:57:36 +04:00
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visit_type_uint64(v, &w64.begin, name, errp);
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2013-07-29 18:47:57 +04:00
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}
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static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v,
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void *opaque, const char *name,
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Error **errp)
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{
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2013-09-02 13:57:36 +04:00
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PCIHostState *h = PCI_HOST_BRIDGE(obj);
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Range w64;
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2013-07-29 18:47:57 +04:00
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2013-09-02 13:57:36 +04:00
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pci_bus_get_w64_range(h->bus, &w64);
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2013-07-29 18:47:57 +04:00
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2013-09-02 13:57:36 +04:00
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visit_type_uint64(v, &w64.end, name, errp);
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2013-07-29 18:47:57 +04:00
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}
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2013-09-10 11:16:02 +04:00
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static void q35_host_get_mmcfg_size(Object *obj, Visitor *v,
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void *opaque, const char *name,
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Error **errp)
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{
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PCIExpressHost *e = PCIE_HOST_BRIDGE(obj);
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uint32_t value = e->size;
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visit_type_uint32(v, &value, name, errp);
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}
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2012-11-15 00:54:06 +04:00
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static Property mch_props[] = {
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2013-09-02 18:59:38 +04:00
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DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr,
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2012-11-15 00:54:06 +04:00
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MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),
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2013-07-29 18:47:57 +04:00
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DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost,
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mch.pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE),
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2013-11-06 03:46:27 +04:00
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DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 0),
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2012-11-15 00:54:06 +04:00
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DEFINE_PROP_END_OF_LIST(),
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};
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static void q35_host_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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2013-06-06 12:48:49 +04:00
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PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
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2012-11-15 00:54:06 +04:00
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2013-06-06 12:48:49 +04:00
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hc->root_bus_path = q35_host_root_bus_path;
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2013-07-01 14:18:23 +04:00
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dc->realize = q35_host_realize;
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2012-11-15 00:54:06 +04:00
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dc->props = mch_props;
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2013-07-29 18:17:45 +04:00
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set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
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2013-05-30 12:35:23 +04:00
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dc->fw_name = "pci";
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2012-11-15 00:54:06 +04:00
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}
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static void q35_host_initfn(Object *obj)
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{
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Q35PCIHost *s = Q35_HOST_DEVICE(obj);
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2013-07-01 14:18:23 +04:00
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PCIHostState *phb = PCI_HOST_BRIDGE(obj);
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memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb,
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"pci-conf-idx", 4);
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memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb,
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"pci-conf-data", 4);
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2012-11-15 00:54:06 +04:00
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2013-08-23 21:37:12 +04:00
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object_initialize(&s->mch, sizeof(s->mch), TYPE_MCH_PCI_DEVICE);
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2012-11-15 00:54:06 +04:00
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object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL);
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qdev_prop_set_uint32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0));
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qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false);
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2013-07-29 18:47:57 +04:00
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object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "int",
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q35_host_get_pci_hole_start,
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NULL, NULL, NULL, NULL);
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object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "int",
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q35_host_get_pci_hole_end,
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NULL, NULL, NULL, NULL);
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object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "int",
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q35_host_get_pci_hole64_start,
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NULL, NULL, NULL, NULL);
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object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "int",
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q35_host_get_pci_hole64_end,
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NULL, NULL, NULL, NULL);
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2013-09-10 11:16:02 +04:00
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object_property_add(obj, PCIE_HOST_MCFG_SIZE, "int",
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q35_host_get_mmcfg_size,
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NULL, NULL, NULL, NULL);
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2013-07-29 18:47:57 +04:00
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/* Leave enough space for the biggest MCFG BAR */
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/* TODO: this matches current bios behaviour, but
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* it's not a power of two, which means an MTRR
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* can't cover it exactly.
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*/
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s->mch.pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT +
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MCH_HOST_BRIDGE_PCIEXBAR_MAX;
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s->mch.pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS;
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2012-11-15 00:54:06 +04:00
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}
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static const TypeInfo q35_host_info = {
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.name = TYPE_Q35_HOST_DEVICE,
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.parent = TYPE_PCIE_HOST_BRIDGE,
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.instance_size = sizeof(Q35PCIHost),
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.instance_init = q35_host_initfn,
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.class_init = q35_host_class_init,
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};
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/****************************************************************************
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* MCH D0:F0
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*/
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/* PCIe MMCFG */
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static void mch_update_pciexbar(MCHPCIState *mch)
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{
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2013-07-01 14:18:22 +04:00
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PCIDevice *pci_dev = PCI_DEVICE(mch);
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BusState *bus = qdev_get_parent_bus(DEVICE(mch));
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PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent);
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2012-11-15 00:54:06 +04:00
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uint64_t pciexbar;
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int enable;
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uint64_t addr;
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uint64_t addr_mask;
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uint32_t length;
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pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR);
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enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN;
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addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK;
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switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) {
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case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M:
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length = 256 * 1024 * 1024;
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break;
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case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M:
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length = 128 * 1024 * 1024;
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addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK |
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MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
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break;
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case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M:
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length = 64 * 1024 * 1024;
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addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
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break;
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case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD:
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default:
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enable = 0;
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length = 0;
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abort();
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break;
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}
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addr = pciexbar & addr_mask;
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2013-07-01 14:18:22 +04:00
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pcie_host_mmcfg_update(pehb, enable, addr, length);
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2013-09-01 14:26:03 +04:00
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/* Leave enough space for the MCFG BAR */
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/*
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* TODO: this matches current bios behaviour, but it's not a power of two,
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* which means an MTRR can't cover it exactly.
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*/
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if (enable) {
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mch->pci_info.w32.begin = addr + length;
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} else {
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mch->pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT;
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}
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2012-11-15 00:54:06 +04:00
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}
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/* PAM */
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static void mch_update_pam(MCHPCIState *mch)
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{
|
2013-07-01 14:18:22 +04:00
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PCIDevice *pd = PCI_DEVICE(mch);
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2012-11-15 00:54:06 +04:00
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int i;
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memory_region_transaction_begin();
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for (i = 0; i < 13; i++) {
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pam_update(&mch->pam_regions[i], i,
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2013-07-01 14:18:22 +04:00
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pd->config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]);
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2012-11-15 00:54:06 +04:00
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}
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memory_region_transaction_commit();
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}
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/* SMRAM */
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static void mch_update_smram(MCHPCIState *mch)
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{
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2013-07-01 14:18:22 +04:00
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PCIDevice *pd = PCI_DEVICE(mch);
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2012-11-15 00:54:06 +04:00
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memory_region_transaction_begin();
|
2014-02-28 14:28:03 +04:00
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smram_update(&mch->smram_region, pd->config[MCH_HOST_BRIDGE_SMRAM],
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2012-11-15 00:54:06 +04:00
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mch->smm_enabled);
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memory_region_transaction_commit();
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}
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static void mch_set_smm(int smm, void *arg)
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{
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MCHPCIState *mch = arg;
|
2013-07-01 14:18:22 +04:00
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PCIDevice *pd = PCI_DEVICE(mch);
|
2012-11-15 00:54:06 +04:00
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memory_region_transaction_begin();
|
2014-02-28 14:28:03 +04:00
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smram_set_smm(&mch->smm_enabled, smm, pd->config[MCH_HOST_BRIDGE_SMRAM],
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2012-11-15 00:54:06 +04:00
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&mch->smram_region);
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memory_region_transaction_commit();
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}
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static void mch_write_config(PCIDevice *d,
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uint32_t address, uint32_t val, int len)
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{
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MCHPCIState *mch = MCH_PCI_DEVICE(d);
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/* XXX: implement SMRAM.D_LOCK */
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pci_default_write_config(d, address, val, len);
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|
|
|
|
|
|
|
if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0,
|
|
|
|
MCH_HOST_BRIDGE_PAM_SIZE)) {
|
|
|
|
mch_update_pam(mch);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR,
|
|
|
|
MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) {
|
|
|
|
mch_update_pciexbar(mch);
|
|
|
|
}
|
|
|
|
|
2014-02-28 14:28:03 +04:00
|
|
|
if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM,
|
|
|
|
MCH_HOST_BRIDGE_SMRAM_SIZE)) {
|
2012-11-15 00:54:06 +04:00
|
|
|
mch_update_smram(mch);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mch_update(MCHPCIState *mch)
|
|
|
|
{
|
|
|
|
mch_update_pciexbar(mch);
|
|
|
|
mch_update_pam(mch);
|
|
|
|
mch_update_smram(mch);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mch_post_load(void *opaque, int version_id)
|
|
|
|
{
|
|
|
|
MCHPCIState *mch = opaque;
|
|
|
|
mch_update(mch);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const VMStateDescription vmstate_mch = {
|
|
|
|
.name = "mch",
|
|
|
|
.version_id = 1,
|
|
|
|
.minimum_version_id = 1,
|
|
|
|
.post_load = mch_post_load,
|
2014-04-16 17:32:32 +04:00
|
|
|
.fields = (VMStateField[]) {
|
2013-07-01 14:18:22 +04:00
|
|
|
VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState),
|
2012-11-15 00:54:06 +04:00
|
|
|
VMSTATE_UINT8(smm_enabled, MCHPCIState),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
static void mch_reset(DeviceState *qdev)
|
|
|
|
{
|
|
|
|
PCIDevice *d = PCI_DEVICE(qdev);
|
|
|
|
MCHPCIState *mch = MCH_PCI_DEVICE(d);
|
|
|
|
|
|
|
|
pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR,
|
|
|
|
MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT);
|
|
|
|
|
2014-02-28 14:28:03 +04:00
|
|
|
d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT;
|
2012-11-15 00:54:06 +04:00
|
|
|
|
|
|
|
mch_update(mch);
|
|
|
|
}
|
|
|
|
|
2014-08-16 09:55:40 +04:00
|
|
|
static AddressSpace *q35_host_dma_iommu(PCIBus *bus, void *opaque, int devfn)
|
|
|
|
{
|
|
|
|
IntelIOMMUState *s = opaque;
|
|
|
|
VTDAddressSpace **pvtd_as;
|
|
|
|
int bus_num = pci_bus_num(bus);
|
|
|
|
|
|
|
|
assert(0 <= bus_num && bus_num <= VTD_PCI_BUS_MAX);
|
|
|
|
assert(0 <= devfn && devfn <= VTD_PCI_DEVFN_MAX);
|
|
|
|
|
|
|
|
pvtd_as = s->address_spaces[bus_num];
|
|
|
|
if (!pvtd_as) {
|
|
|
|
/* No corresponding free() */
|
|
|
|
pvtd_as = g_malloc0(sizeof(VTDAddressSpace *) * VTD_PCI_DEVFN_MAX);
|
|
|
|
s->address_spaces[bus_num] = pvtd_as;
|
|
|
|
}
|
|
|
|
if (!pvtd_as[devfn]) {
|
|
|
|
pvtd_as[devfn] = g_malloc0(sizeof(VTDAddressSpace));
|
|
|
|
|
|
|
|
pvtd_as[devfn]->bus_num = (uint8_t)bus_num;
|
|
|
|
pvtd_as[devfn]->devfn = (uint8_t)devfn;
|
|
|
|
pvtd_as[devfn]->iommu_state = s;
|
2014-08-16 09:55:43 +04:00
|
|
|
pvtd_as[devfn]->context_cache_entry.context_cache_gen = 0;
|
2014-08-16 09:55:40 +04:00
|
|
|
memory_region_init_iommu(&pvtd_as[devfn]->iommu, OBJECT(s),
|
|
|
|
&s->iommu_ops, "intel_iommu", UINT64_MAX);
|
|
|
|
address_space_init(&pvtd_as[devfn]->as,
|
|
|
|
&pvtd_as[devfn]->iommu, "intel_iommu");
|
|
|
|
}
|
|
|
|
return &pvtd_as[devfn]->as;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mch_init_dmar(MCHPCIState *mch)
|
|
|
|
{
|
|
|
|
PCIBus *pci_bus = PCI_BUS(qdev_get_parent_bus(DEVICE(mch)));
|
|
|
|
|
|
|
|
mch->iommu = INTEL_IOMMU_DEVICE(qdev_create(NULL, TYPE_INTEL_IOMMU_DEVICE));
|
|
|
|
object_property_add_child(OBJECT(mch), "intel-iommu",
|
|
|
|
OBJECT(mch->iommu), NULL);
|
|
|
|
qdev_init_nofail(DEVICE(mch->iommu));
|
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(mch->iommu), 0, Q35_HOST_BRIDGE_IOMMU_ADDR);
|
|
|
|
|
|
|
|
pci_setup_iommu(pci_bus, q35_host_dma_iommu, mch->iommu);
|
|
|
|
}
|
|
|
|
|
2015-01-19 17:52:30 +03:00
|
|
|
static void mch_realize(PCIDevice *d, Error **errp)
|
2012-11-15 00:54:06 +04:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
MCHPCIState *mch = MCH_PCI_DEVICE(d);
|
2013-10-29 16:57:34 +04:00
|
|
|
|
|
|
|
/* setup pci memory mapping */
|
|
|
|
pc_pci_as_mapping_init(OBJECT(mch), mch->system_memory,
|
|
|
|
mch->pci_address_space);
|
|
|
|
|
2012-11-15 00:54:06 +04:00
|
|
|
/* smram */
|
|
|
|
cpu_smm_register(&mch_set_smm, mch);
|
2013-06-07 05:25:08 +04:00
|
|
|
memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region",
|
2012-11-15 00:54:06 +04:00
|
|
|
mch->pci_address_space, 0xa0000, 0x20000);
|
|
|
|
memory_region_add_subregion_overlap(mch->system_memory, 0xa0000,
|
|
|
|
&mch->smram_region, 1);
|
|
|
|
memory_region_set_enabled(&mch->smram_region, false);
|
2014-08-16 09:55:41 +04:00
|
|
|
init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory,
|
|
|
|
mch->pci_address_space, &mch->pam_regions[0],
|
|
|
|
PAM_BIOS_BASE, PAM_BIOS_SIZE);
|
2012-11-15 00:54:06 +04:00
|
|
|
for (i = 0; i < 12; ++i) {
|
2014-08-16 09:55:41 +04:00
|
|
|
init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory,
|
|
|
|
mch->pci_address_space, &mch->pam_regions[i+1],
|
|
|
|
PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE);
|
2012-11-15 00:54:06 +04:00
|
|
|
}
|
2014-08-16 09:55:40 +04:00
|
|
|
/* Intel IOMMU (VT-d) */
|
2015-02-04 18:43:48 +03:00
|
|
|
if (machine_iommu(current_machine)) {
|
2014-08-16 09:55:40 +04:00
|
|
|
mch_init_dmar(mch);
|
|
|
|
}
|
2012-11-15 00:54:06 +04:00
|
|
|
}
|
|
|
|
|
2013-07-24 19:56:10 +04:00
|
|
|
uint64_t mch_mcfg_base(void)
|
|
|
|
{
|
|
|
|
bool ambiguous;
|
|
|
|
Object *o = object_resolve_path_type("", TYPE_MCH_PCI_DEVICE, &ambiguous);
|
|
|
|
if (!o) {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT;
|
|
|
|
}
|
|
|
|
|
2012-11-15 00:54:06 +04:00
|
|
|
static void mch_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
|
2015-01-19 17:52:30 +03:00
|
|
|
k->realize = mch_realize;
|
2012-11-15 00:54:06 +04:00
|
|
|
k->config_write = mch_write_config;
|
|
|
|
dc->reset = mch_reset;
|
2013-07-29 18:17:45 +04:00
|
|
|
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
|
2012-11-15 00:54:06 +04:00
|
|
|
dc->desc = "Host bridge";
|
|
|
|
dc->vmsd = &vmstate_mch;
|
|
|
|
k->vendor_id = PCI_VENDOR_ID_INTEL;
|
|
|
|
k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH;
|
2013-09-02 17:43:36 +04:00
|
|
|
k->revision = MCH_HOST_BRIDGE_REVISION_DEFAULT;
|
2012-11-15 00:54:06 +04:00
|
|
|
k->class_id = PCI_CLASS_BRIDGE_HOST;
|
pci-host: Consistently set cannot_instantiate_with_device_add_yet
Many PCI host bridges consist of a sysbus device and a PCI device.
You need both for the thing to work. Arguably, these bridges should
be modelled as a single, composite devices instead of pairs of
seemingly independent devices you can only use together, but we're not
there, yet.
Since the sysbus part can't be instantiated with device_add, yet,
permitting it with the PCI part is useless. We shouldn't offer
useless options to the user, so let's set
cannot_instantiate_with_device_add_yet for them.
It's already set for Bonito, Grackle, i440FX and Raven. Document why.
Set it for the others: dec-21154, e500-host-bridge, gt64120_pci, mch,
pbm-pci, ppc4xx-host-bridge, sh_pci_host, u3-agp, uni-north-agp,
uni-north-internal-pci, uni-north-pci, and versatile_pci_host.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Marcel Apfelbaum <marcel.a@redhat.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-11-28 20:26:58 +04:00
|
|
|
/*
|
|
|
|
* PCI-facing part of the host bridge, not usable without the
|
|
|
|
* host-facing part, which can't be device_add'ed, yet.
|
|
|
|
*/
|
|
|
|
dc->cannot_instantiate_with_device_add_yet = true;
|
2012-11-15 00:54:06 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo mch_info = {
|
|
|
|
.name = TYPE_MCH_PCI_DEVICE,
|
|
|
|
.parent = TYPE_PCI_DEVICE,
|
|
|
|
.instance_size = sizeof(MCHPCIState),
|
|
|
|
.class_init = mch_class_init,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void q35_register(void)
|
|
|
|
{
|
|
|
|
type_register_static(&mch_info);
|
|
|
|
type_register_static(&q35_host_info);
|
|
|
|
}
|
|
|
|
|
|
|
|
type_init(q35_register);
|