2011-03-08 01:32:34 +03:00
|
|
|
/*
|
|
|
|
* QEMU model of the Milkymist SD Card Controller.
|
|
|
|
*
|
|
|
|
* Copyright (c) 2010 Michael Walle <michael@walle.cc>
|
|
|
|
*
|
|
|
|
* This library is free software; you can redistribute it and/or
|
|
|
|
* modify it under the terms of the GNU Lesser General Public
|
|
|
|
* License as published by the Free Software Foundation; either
|
|
|
|
* version 2 of the License, or (at your option) any later version.
|
|
|
|
*
|
|
|
|
* This library is distributed in the hope that it will be useful,
|
|
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|
|
|
* Lesser General Public License for more details.
|
|
|
|
*
|
|
|
|
* You should have received a copy of the GNU Lesser General Public
|
|
|
|
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
|
|
|
*
|
|
|
|
*
|
|
|
|
* Specification available at:
|
2016-06-20 19:08:41 +03:00
|
|
|
* http://milkymist.walle.cc/socdoc/memcard.pdf
|
2011-03-08 01:32:34 +03:00
|
|
|
*/
|
|
|
|
|
2016-01-26 21:16:57 +03:00
|
|
|
#include "qemu/osdep.h"
|
2018-02-22 18:12:51 +03:00
|
|
|
#include "qemu/log.h"
|
2019-05-23 17:35:07 +03:00
|
|
|
#include "qemu/module.h"
|
2013-02-04 18:40:22 +04:00
|
|
|
#include "hw/sysbus.h"
|
2019-08-12 08:23:45 +03:00
|
|
|
#include "migration/vmstate.h"
|
2011-03-08 01:32:34 +03:00
|
|
|
#include "trace.h"
|
2018-05-03 22:50:46 +03:00
|
|
|
#include "qapi/error.h"
|
2014-10-07 15:59:13 +04:00
|
|
|
#include "sysemu/block-backend.h"
|
2012-12-17 21:20:04 +04:00
|
|
|
#include "sysemu/blockdev.h"
|
2019-08-12 08:23:51 +03:00
|
|
|
#include "hw/qdev-properties.h"
|
2015-10-08 16:21:01 +03:00
|
|
|
#include "hw/sd/sd.h"
|
2011-03-08 01:32:34 +03:00
|
|
|
|
|
|
|
enum {
|
|
|
|
ENABLE_CMD_TX = (1<<0),
|
|
|
|
ENABLE_CMD_RX = (1<<1),
|
|
|
|
ENABLE_DAT_TX = (1<<2),
|
|
|
|
ENABLE_DAT_RX = (1<<3),
|
|
|
|
};
|
|
|
|
|
|
|
|
enum {
|
|
|
|
PENDING_CMD_TX = (1<<0),
|
|
|
|
PENDING_CMD_RX = (1<<1),
|
|
|
|
PENDING_DAT_TX = (1<<2),
|
|
|
|
PENDING_DAT_RX = (1<<3),
|
|
|
|
};
|
|
|
|
|
|
|
|
enum {
|
|
|
|
START_CMD_TX = (1<<0),
|
|
|
|
START_DAT_RX = (1<<1),
|
|
|
|
};
|
|
|
|
|
|
|
|
enum {
|
|
|
|
R_CLK2XDIV = 0,
|
|
|
|
R_ENABLE,
|
|
|
|
R_PENDING,
|
|
|
|
R_START,
|
|
|
|
R_CMD,
|
|
|
|
R_DAT,
|
|
|
|
R_MAX
|
|
|
|
};
|
|
|
|
|
2013-07-27 15:18:50 +04:00
|
|
|
#define TYPE_MILKYMIST_MEMCARD "milkymist-memcard"
|
|
|
|
#define MILKYMIST_MEMCARD(obj) \
|
|
|
|
OBJECT_CHECK(MilkymistMemcardState, (obj), TYPE_MILKYMIST_MEMCARD)
|
|
|
|
|
2011-03-08 01:32:34 +03:00
|
|
|
struct MilkymistMemcardState {
|
2013-07-27 15:18:50 +04:00
|
|
|
SysBusDevice parent_obj;
|
|
|
|
|
2011-08-31 18:48:41 +04:00
|
|
|
MemoryRegion regs_region;
|
2018-02-22 18:12:52 +03:00
|
|
|
SDBus sdbus;
|
2011-03-08 01:32:34 +03:00
|
|
|
|
|
|
|
int command_write_ptr;
|
|
|
|
int response_read_ptr;
|
|
|
|
int response_len;
|
|
|
|
int ignore_next_cmd;
|
|
|
|
int enabled;
|
|
|
|
uint8_t command[6];
|
|
|
|
uint8_t response[17];
|
|
|
|
uint32_t regs[R_MAX];
|
|
|
|
};
|
|
|
|
typedef struct MilkymistMemcardState MilkymistMemcardState;
|
|
|
|
|
|
|
|
static void update_pending_bits(MilkymistMemcardState *s)
|
|
|
|
{
|
|
|
|
/* transmits are instantaneous, thus tx pending bits are never set */
|
|
|
|
s->regs[R_PENDING] = 0;
|
|
|
|
/* if rx is enabled the corresponding pending bits are always set */
|
|
|
|
if (s->regs[R_ENABLE] & ENABLE_CMD_RX) {
|
|
|
|
s->regs[R_PENDING] |= PENDING_CMD_RX;
|
|
|
|
}
|
|
|
|
if (s->regs[R_ENABLE] & ENABLE_DAT_RX) {
|
|
|
|
s->regs[R_PENDING] |= PENDING_DAT_RX;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void memcard_sd_command(MilkymistMemcardState *s)
|
|
|
|
{
|
|
|
|
SDRequest req;
|
|
|
|
|
|
|
|
req.cmd = s->command[0] & 0x3f;
|
2018-06-29 17:11:20 +03:00
|
|
|
req.arg = ldl_be_p(s->command + 1);
|
2011-03-08 01:32:34 +03:00
|
|
|
req.crc = s->command[5];
|
|
|
|
|
|
|
|
s->response[0] = req.cmd;
|
2018-02-22 18:12:52 +03:00
|
|
|
s->response_len = sdbus_do_command(&s->sdbus, &req, s->response + 1);
|
2011-03-08 01:32:34 +03:00
|
|
|
s->response_read_ptr = 0;
|
|
|
|
|
|
|
|
if (s->response_len == 16) {
|
|
|
|
/* R2 response */
|
|
|
|
s->response[0] = 0x3f;
|
|
|
|
s->response_len += 1;
|
|
|
|
} else if (s->response_len == 4) {
|
|
|
|
/* no crc calculation, insert dummy byte */
|
|
|
|
s->response[5] = 0;
|
|
|
|
s->response_len += 2;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (req.cmd == 0) {
|
|
|
|
/* next write is a dummy byte to clock the initialization of the sd
|
|
|
|
* card */
|
|
|
|
s->ignore_next_cmd = 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-10-23 14:30:10 +04:00
|
|
|
static uint64_t memcard_read(void *opaque, hwaddr addr,
|
2011-08-31 18:48:41 +04:00
|
|
|
unsigned size)
|
2011-03-08 01:32:34 +03:00
|
|
|
{
|
|
|
|
MilkymistMemcardState *s = opaque;
|
|
|
|
uint32_t r = 0;
|
|
|
|
|
|
|
|
addr >>= 2;
|
|
|
|
switch (addr) {
|
|
|
|
case R_CMD:
|
|
|
|
if (!s->enabled) {
|
|
|
|
r = 0xff;
|
|
|
|
} else {
|
|
|
|
r = s->response[s->response_read_ptr++];
|
|
|
|
if (s->response_read_ptr > s->response_len) {
|
2018-02-22 18:12:51 +03:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "milkymist_memcard: "
|
2018-06-08 15:15:33 +03:00
|
|
|
"read more cmd bytes than available: clipping\n");
|
2011-03-08 01:32:34 +03:00
|
|
|
s->response_read_ptr = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case R_DAT:
|
|
|
|
if (!s->enabled) {
|
|
|
|
r = 0xffffffff;
|
|
|
|
} else {
|
|
|
|
r = 0;
|
2018-02-22 18:12:52 +03:00
|
|
|
r |= sdbus_read_data(&s->sdbus) << 24;
|
|
|
|
r |= sdbus_read_data(&s->sdbus) << 16;
|
|
|
|
r |= sdbus_read_data(&s->sdbus) << 8;
|
|
|
|
r |= sdbus_read_data(&s->sdbus);
|
2011-03-08 01:32:34 +03:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case R_CLK2XDIV:
|
|
|
|
case R_ENABLE:
|
|
|
|
case R_PENDING:
|
|
|
|
case R_START:
|
|
|
|
r = s->regs[addr];
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
2018-02-22 18:12:51 +03:00
|
|
|
qemu_log_mask(LOG_UNIMP, "milkymist_memcard: "
|
|
|
|
"read access to unknown register 0x%" HWADDR_PRIx "\n",
|
|
|
|
addr << 2);
|
2011-03-08 01:32:34 +03:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
trace_milkymist_memcard_memory_read(addr << 2, r);
|
|
|
|
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
2012-10-23 14:30:10 +04:00
|
|
|
static void memcard_write(void *opaque, hwaddr addr, uint64_t value,
|
2011-08-31 18:48:41 +04:00
|
|
|
unsigned size)
|
2011-03-08 01:32:34 +03:00
|
|
|
{
|
|
|
|
MilkymistMemcardState *s = opaque;
|
|
|
|
|
|
|
|
trace_milkymist_memcard_memory_write(addr, value);
|
|
|
|
|
|
|
|
addr >>= 2;
|
|
|
|
switch (addr) {
|
|
|
|
case R_PENDING:
|
|
|
|
/* clear rx pending bits */
|
|
|
|
s->regs[R_PENDING] &= ~(value & (PENDING_CMD_RX | PENDING_DAT_RX));
|
|
|
|
update_pending_bits(s);
|
|
|
|
break;
|
|
|
|
case R_CMD:
|
|
|
|
if (!s->enabled) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (s->ignore_next_cmd) {
|
|
|
|
s->ignore_next_cmd = 0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
s->command[s->command_write_ptr] = value & 0xff;
|
|
|
|
s->command_write_ptr = (s->command_write_ptr + 1) % 6;
|
|
|
|
if (s->command_write_ptr == 0) {
|
|
|
|
memcard_sd_command(s);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case R_DAT:
|
|
|
|
if (!s->enabled) {
|
|
|
|
break;
|
|
|
|
}
|
2018-02-22 18:12:52 +03:00
|
|
|
sdbus_write_data(&s->sdbus, (value >> 24) & 0xff);
|
|
|
|
sdbus_write_data(&s->sdbus, (value >> 16) & 0xff);
|
|
|
|
sdbus_write_data(&s->sdbus, (value >> 8) & 0xff);
|
|
|
|
sdbus_write_data(&s->sdbus, value & 0xff);
|
2011-03-08 01:32:34 +03:00
|
|
|
break;
|
|
|
|
case R_ENABLE:
|
|
|
|
s->regs[addr] = value;
|
|
|
|
update_pending_bits(s);
|
|
|
|
break;
|
|
|
|
case R_CLK2XDIV:
|
|
|
|
case R_START:
|
|
|
|
s->regs[addr] = value;
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
2018-02-22 18:12:51 +03:00
|
|
|
qemu_log_mask(LOG_UNIMP, "milkymist_memcard: "
|
|
|
|
"write access to unknown register 0x%" HWADDR_PRIx " "
|
|
|
|
"(value 0x%" PRIx64 ")\n", addr << 2, value);
|
2011-03-08 01:32:34 +03:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-08-31 18:48:41 +04:00
|
|
|
static const MemoryRegionOps memcard_mmio_ops = {
|
|
|
|
.read = memcard_read,
|
|
|
|
.write = memcard_write,
|
|
|
|
.valid = {
|
|
|
|
.min_access_size = 4,
|
|
|
|
.max_access_size = 4,
|
|
|
|
},
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
2011-03-08 01:32:34 +03:00
|
|
|
};
|
|
|
|
|
|
|
|
static void milkymist_memcard_reset(DeviceState *d)
|
|
|
|
{
|
2013-07-27 15:18:50 +04:00
|
|
|
MilkymistMemcardState *s = MILKYMIST_MEMCARD(d);
|
2011-03-08 01:32:34 +03:00
|
|
|
int i;
|
|
|
|
|
|
|
|
s->command_write_ptr = 0;
|
|
|
|
s->response_read_ptr = 0;
|
|
|
|
s->response_len = 0;
|
|
|
|
|
|
|
|
for (i = 0; i < R_MAX; i++) {
|
|
|
|
s->regs[i] = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-02-22 18:12:51 +03:00
|
|
|
static void milkymist_memcard_init(Object *obj)
|
|
|
|
{
|
|
|
|
MilkymistMemcardState *s = MILKYMIST_MEMCARD(obj);
|
|
|
|
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
|
|
|
|
|
|
|
|
memory_region_init_io(&s->regs_region, OBJECT(s), &memcard_mmio_ops, s,
|
|
|
|
"milkymist-memcard", R_MAX * 4);
|
|
|
|
sysbus_init_mmio(dev, &s->regs_region);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void milkymist_memcard_realize(DeviceState *dev, Error **errp)
|
2011-03-08 01:32:34 +03:00
|
|
|
{
|
2013-07-27 15:18:50 +04:00
|
|
|
MilkymistMemcardState *s = MILKYMIST_MEMCARD(dev);
|
2018-02-22 18:12:52 +03:00
|
|
|
DeviceState *carddev;
|
2014-10-07 15:59:18 +04:00
|
|
|
BlockBackend *blk;
|
2018-02-22 18:12:51 +03:00
|
|
|
DriveInfo *dinfo;
|
2018-02-22 18:12:52 +03:00
|
|
|
Error *err = NULL;
|
2011-03-08 01:32:34 +03:00
|
|
|
|
2018-02-22 18:12:52 +03:00
|
|
|
qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS,
|
|
|
|
dev, "sd-bus");
|
|
|
|
|
|
|
|
/* Create and plug in the sd card */
|
2015-03-23 21:03:13 +03:00
|
|
|
/* FIXME use a qdev drive property instead of drive_get_next() */
|
2011-03-08 01:32:34 +03:00
|
|
|
dinfo = drive_get_next(IF_SD);
|
2014-10-07 15:59:18 +04:00
|
|
|
blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
|
qdev: Convert uses of qdev_create() with Coccinelle
This is the transformation explained in the commit before previous.
Takes care of just one pattern that needs conversion. More to come in
this series.
Coccinelle script:
@ depends on !(file in "hw/arm/highbank.c")@
expression bus, type_name, dev, expr;
@@
- dev = qdev_create(bus, type_name);
+ dev = qdev_new(type_name);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
@@
expression bus, type_name, dev, expr;
identifier DOWN;
@@
- dev = DOWN(qdev_create(bus, type_name));
+ dev = DOWN(qdev_new(type_name));
... when != dev = expr
- qdev_init_nofail(DEVICE(dev));
+ qdev_realize_and_unref(DEVICE(dev), bus, &error_fatal);
@@
expression bus, type_name, expr;
identifier dev;
@@
- DeviceState *dev = qdev_create(bus, type_name);
+ DeviceState *dev = qdev_new(type_name);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
@@
expression bus, type_name, dev, expr, errp;
symbol true;
@@
- dev = qdev_create(bus, type_name);
+ dev = qdev_new(type_name);
... when != dev = expr
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize_and_unref(dev, bus, errp);
@@
expression bus, type_name, expr, errp;
identifier dev;
symbol true;
@@
- DeviceState *dev = qdev_create(bus, type_name);
+ DeviceState *dev = qdev_new(type_name);
... when != dev = expr
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize_and_unref(dev, bus, errp);
The first rule exempts hw/arm/highbank.c, because it matches along two
control flow paths there, with different @type_name. Covered by the
next commit's manual conversions.
Missing #include "qapi/error.h" added manually.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-10-armbru@redhat.com>
[Conflicts in hw/misc/empty_slot.c and hw/sparc/leon3.c resolved]
2020-06-10 08:31:58 +03:00
|
|
|
carddev = qdev_new(TYPE_SD_CARD);
|
2020-06-22 12:42:27 +03:00
|
|
|
qdev_prop_set_drive(carddev, "drive", blk);
|
2020-06-30 12:03:34 +03:00
|
|
|
if (!qdev_realize_and_unref(carddev, BUS(&s->sdbus), &err)) {
|
|
|
|
error_propagate_prepend(errp, err, "failed to init SD card: %s");
|
2018-02-22 18:12:51 +03:00
|
|
|
return;
|
2013-09-13 17:51:47 +04:00
|
|
|
}
|
2014-10-07 15:59:18 +04:00
|
|
|
s->enabled = blk && blk_is_inserted(blk);
|
2011-03-08 01:32:34 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static const VMStateDescription vmstate_milkymist_memcard = {
|
|
|
|
.name = "milkymist-memcard",
|
|
|
|
.version_id = 1,
|
|
|
|
.minimum_version_id = 1,
|
2014-04-16 18:01:33 +04:00
|
|
|
.fields = (VMStateField[]) {
|
2011-03-08 01:32:34 +03:00
|
|
|
VMSTATE_INT32(command_write_ptr, MilkymistMemcardState),
|
|
|
|
VMSTATE_INT32(response_read_ptr, MilkymistMemcardState),
|
|
|
|
VMSTATE_INT32(response_len, MilkymistMemcardState),
|
|
|
|
VMSTATE_INT32(ignore_next_cmd, MilkymistMemcardState),
|
|
|
|
VMSTATE_INT32(enabled, MilkymistMemcardState),
|
|
|
|
VMSTATE_UINT8_ARRAY(command, MilkymistMemcardState, 6),
|
|
|
|
VMSTATE_UINT8_ARRAY(response, MilkymistMemcardState, 17),
|
|
|
|
VMSTATE_UINT32_ARRAY(regs, MilkymistMemcardState, R_MAX),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2012-01-24 23:12:29 +04:00
|
|
|
static void milkymist_memcard_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
2011-12-08 07:34:16 +04:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2012-01-24 23:12:29 +04:00
|
|
|
|
2018-02-22 18:12:51 +03:00
|
|
|
dc->realize = milkymist_memcard_realize;
|
2011-12-08 07:34:16 +04:00
|
|
|
dc->reset = milkymist_memcard_reset;
|
|
|
|
dc->vmsd = &vmstate_milkymist_memcard;
|
sysbus: Make devices picking up backends unavailable with -device
Device models aren't supposed to go on fishing expeditions for
backends. They should expose suitable properties for the user to set.
For onboard devices, board code sets them.
A number of sysbus devices pick up block backends in their init() /
instance_init() methods with drive_get_next() instead: sl-nand,
milkymist-memcard, pl181, generic-sdhci.
Likewise, a number of sysbus devices pick up character backends in
their init() / realize() methods with qemu_char_get_next_serial():
cadence_uart, digic-uart, etraxfs,serial, lm32-juart, lm32-uart,
milkymist-uart, pl011, stm32f2xx-usart, xlnx.xps-uartlite.
All these mistakes are already marked FIXME. See the commit that
added these FIXMEs for a more detailed explanation of what's wrong.
Fortunately, only machines ppce500 and pseries-* support -device with
sysbus devices, and none of the devices above is supported with these
machines.
Set cannot_instantiate_with_device_add_yet to preserve our luck.
Cc: Andrzej Zaborowski <balrogg@gmail.com>
Cc: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Cc: Antony Pavlov <antonynpavlov@gmail.com>
Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
Cc: Michael Walle <michael@walle.cc>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
2015-03-23 21:34:40 +03:00
|
|
|
/* Reason: init() method uses drive_get_next() */
|
2017-05-03 23:35:44 +03:00
|
|
|
dc->user_creatable = false;
|
2012-01-24 23:12:29 +04:00
|
|
|
}
|
|
|
|
|
2013-01-10 19:19:07 +04:00
|
|
|
static const TypeInfo milkymist_memcard_info = {
|
2013-07-27 15:18:50 +04:00
|
|
|
.name = TYPE_MILKYMIST_MEMCARD,
|
2011-12-08 07:34:16 +04:00
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
|
|
.instance_size = sizeof(MilkymistMemcardState),
|
2018-02-22 18:12:51 +03:00
|
|
|
.instance_init = milkymist_memcard_init,
|
2011-12-08 07:34:16 +04:00
|
|
|
.class_init = milkymist_memcard_class_init,
|
2011-03-08 01:32:34 +03:00
|
|
|
};
|
|
|
|
|
2012-02-09 18:20:55 +04:00
|
|
|
static void milkymist_memcard_register_types(void)
|
2011-03-08 01:32:34 +03:00
|
|
|
{
|
2011-12-08 07:34:16 +04:00
|
|
|
type_register_static(&milkymist_memcard_info);
|
2011-03-08 01:32:34 +03:00
|
|
|
}
|
|
|
|
|
2012-02-09 18:20:55 +04:00
|
|
|
type_init(milkymist_memcard_register_types)
|