60 lines
1.8 KiB
C
60 lines
1.8 KiB
C
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/*
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* ARM CMSDK APB watchdog emulation
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*
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* Copyright (c) 2018 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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/*
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* This is a model of the "APB watchdog" which is part of the Cortex-M
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* System Design Kit (CMSDK) and documented in the Cortex-M System
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* Design Kit Technical Reference Manual (ARM DDI0479C):
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* https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
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*
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* QEMU interface:
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* + QOM property "wdogclk-frq": frequency at which the watchdog is clocked
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* + sysbus MMIO region 0: the register bank
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* + sysbus IRQ 0: watchdog interrupt
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*
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* In real hardware the watchdog's reset output is just a GPIO line
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* which can then be masked by the board or treated as a simple interrupt.
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* (For instance the IoTKit does this with the non-secure watchdog, so that
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* secure code can control whether non-secure code can perform a system
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* reset via its watchdog.) In QEMU, we just wire up the watchdog reset
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* to watchdog_perform_action(), at least for the moment.
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*/
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#ifndef CMSDK_APB_WATCHDOG_H
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#define CMSDK_APB_WATCHDOG_H
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#include "hw/sysbus.h"
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#include "hw/ptimer.h"
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#define TYPE_CMSDK_APB_WATCHDOG "cmsdk-apb-watchdog"
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#define CMSDK_APB_WATCHDOG(obj) OBJECT_CHECK(CMSDKAPBWatchdog, (obj), \
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TYPE_CMSDK_APB_WATCHDOG)
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typedef struct CMSDKAPBWatchdog {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion iomem;
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qemu_irq wdogint;
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uint32_t wdogclk_frq;
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struct ptimer_state *timer;
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uint32_t control;
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uint32_t intstatus;
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uint32_t lock;
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uint32_t itcr;
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uint32_t itop;
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uint32_t resetstatus;
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} CMSDKAPBWatchdog;
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#endif
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