2012-04-29 21:48:05 +04:00
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/*
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* x86 SMM helpers
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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2016-01-26 21:17:03 +03:00
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#include "qemu/osdep.h"
|
tcg: drop global lock during TCG code execution
This finally allows TCG to benefit from the iothread introduction: Drop
the global mutex while running pure TCG CPU code. Reacquire the lock
when entering MMIO or PIO emulation, or when leaving the TCG loop.
We have to revert a few optimization for the current TCG threading
model, namely kicking the TCG thread in qemu_mutex_lock_iothread and not
kicking it in qemu_cpu_kick. We also need to disable RAM block
reordering until we have a more efficient locking mechanism at hand.
Still, a Linux x86 UP guest and my Musicpal ARM model boot fine here.
These numbers demonstrate where we gain something:
20338 jan 20 0 331m 75m 6904 R 99 0.9 0:50.95 qemu-system-arm
20337 jan 20 0 331m 75m 6904 S 20 0.9 0:26.50 qemu-system-arm
The guest CPU was fully loaded, but the iothread could still run mostly
independent on a second core. Without the patch we don't get beyond
32206 jan 20 0 330m 73m 7036 R 82 0.9 1:06.00 qemu-system-arm
32204 jan 20 0 330m 73m 7036 S 21 0.9 0:17.03 qemu-system-arm
We don't benefit significantly, though, when the guest is not fully
loading a host CPU.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Message-Id: <1439220437-23957-10-git-send-email-fred.konrad@greensocs.com>
[FK: Rebase, fix qemu_devices_reset deadlock, rm address_space_* mutex]
Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
[EGC: fixed iothread lock for cpu-exec IRQ handling]
Signed-off-by: Emilio G. Cota <cota@braap.org>
[AJB: -smp single-threaded fix, clean commit msg, BQL fixes]
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Pranith Kumar <bobby.prani@gmail.com>
[PM: target-arm changes]
Acked-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-23 21:29:11 +03:00
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#include "qemu/main-loop.h"
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2012-04-29 21:48:05 +04:00
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#include "cpu.h"
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2014-04-08 09:31:41 +04:00
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#include "exec/helper-proto.h"
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2016-01-07 16:55:28 +03:00
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#include "exec/log.h"
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2012-04-29 21:48:05 +04:00
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/* SMM support */
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#if defined(CONFIG_USER_ONLY)
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2013-07-03 04:45:17 +04:00
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void do_smm_enter(X86CPU *cpu)
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2012-04-29 21:48:05 +04:00
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{
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}
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2012-04-29 21:54:21 +04:00
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void helper_rsm(CPUX86State *env)
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2012-04-29 21:48:05 +04:00
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{
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}
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#else
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#ifdef TARGET_X86_64
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#define SMM_REVISION_ID 0x00020064
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#else
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#define SMM_REVISION_ID 0x00020000
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#endif
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|
|
|
tcg: drop global lock during TCG code execution
This finally allows TCG to benefit from the iothread introduction: Drop
the global mutex while running pure TCG CPU code. Reacquire the lock
when entering MMIO or PIO emulation, or when leaving the TCG loop.
We have to revert a few optimization for the current TCG threading
model, namely kicking the TCG thread in qemu_mutex_lock_iothread and not
kicking it in qemu_cpu_kick. We also need to disable RAM block
reordering until we have a more efficient locking mechanism at hand.
Still, a Linux x86 UP guest and my Musicpal ARM model boot fine here.
These numbers demonstrate where we gain something:
20338 jan 20 0 331m 75m 6904 R 99 0.9 0:50.95 qemu-system-arm
20337 jan 20 0 331m 75m 6904 S 20 0.9 0:26.50 qemu-system-arm
The guest CPU was fully loaded, but the iothread could still run mostly
independent on a second core. Without the patch we don't get beyond
32206 jan 20 0 330m 73m 7036 R 82 0.9 1:06.00 qemu-system-arm
32204 jan 20 0 330m 73m 7036 S 21 0.9 0:17.03 qemu-system-arm
We don't benefit significantly, though, when the guest is not fully
loading a host CPU.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Message-Id: <1439220437-23957-10-git-send-email-fred.konrad@greensocs.com>
[FK: Rebase, fix qemu_devices_reset deadlock, rm address_space_* mutex]
Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
[EGC: fixed iothread lock for cpu-exec IRQ handling]
Signed-off-by: Emilio G. Cota <cota@braap.org>
[AJB: -smp single-threaded fix, clean commit msg, BQL fixes]
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Pranith Kumar <bobby.prani@gmail.com>
[PM: target-arm changes]
Acked-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-23 21:29:11 +03:00
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/* Called with iothread lock taken */
|
2015-03-31 15:12:25 +03:00
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void cpu_smm_update(X86CPU *cpu)
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{
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CPUX86State *env = &cpu->env;
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bool smm_enabled = (env->hflags & HF_SMM_MASK);
|
|
|
|
|
tcg: drop global lock during TCG code execution
This finally allows TCG to benefit from the iothread introduction: Drop
the global mutex while running pure TCG CPU code. Reacquire the lock
when entering MMIO or PIO emulation, or when leaving the TCG loop.
We have to revert a few optimization for the current TCG threading
model, namely kicking the TCG thread in qemu_mutex_lock_iothread and not
kicking it in qemu_cpu_kick. We also need to disable RAM block
reordering until we have a more efficient locking mechanism at hand.
Still, a Linux x86 UP guest and my Musicpal ARM model boot fine here.
These numbers demonstrate where we gain something:
20338 jan 20 0 331m 75m 6904 R 99 0.9 0:50.95 qemu-system-arm
20337 jan 20 0 331m 75m 6904 S 20 0.9 0:26.50 qemu-system-arm
The guest CPU was fully loaded, but the iothread could still run mostly
independent on a second core. Without the patch we don't get beyond
32206 jan 20 0 330m 73m 7036 R 82 0.9 1:06.00 qemu-system-arm
32204 jan 20 0 330m 73m 7036 S 21 0.9 0:17.03 qemu-system-arm
We don't benefit significantly, though, when the guest is not fully
loading a host CPU.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Message-Id: <1439220437-23957-10-git-send-email-fred.konrad@greensocs.com>
[FK: Rebase, fix qemu_devices_reset deadlock, rm address_space_* mutex]
Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
[EGC: fixed iothread lock for cpu-exec IRQ handling]
Signed-off-by: Emilio G. Cota <cota@braap.org>
[AJB: -smp single-threaded fix, clean commit msg, BQL fixes]
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Pranith Kumar <bobby.prani@gmail.com>
[PM: target-arm changes]
Acked-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-23 21:29:11 +03:00
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g_assert(qemu_mutex_iothread_locked());
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2015-03-31 15:12:25 +03:00
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if (cpu->smram) {
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memory_region_set_enabled(cpu->smram, smm_enabled);
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}
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}
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2013-07-03 04:45:17 +04:00
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void do_smm_enter(X86CPU *cpu)
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2012-04-29 21:48:05 +04:00
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{
|
2013-07-03 04:45:17 +04:00
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CPUX86State *env = &cpu->env;
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2013-11-28 03:11:44 +04:00
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CPUState *cs = CPU(cpu);
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2012-04-29 21:48:05 +04:00
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target_ulong sm_state;
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SegmentCache *dt;
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int i, offset;
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qemu_log_mask(CPU_LOG_INT, "SMM: enter\n");
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2013-06-16 09:28:50 +04:00
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log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP);
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2012-04-29 21:48:05 +04:00
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env->hflags |= HF_SMM_MASK;
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2015-04-22 12:40:41 +03:00
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if (env->hflags2 & HF2_NMI_MASK) {
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env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
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} else {
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env->hflags2 |= HF2_NMI_MASK;
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}
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2015-03-31 15:12:25 +03:00
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cpu_smm_update(cpu);
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2012-04-29 21:48:05 +04:00
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sm_state = env->smbase + 0x8000;
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#ifdef TARGET_X86_64
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for (i = 0; i < 6; i++) {
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dt = &env->segs[i];
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offset = 0x7e00 + i * 16;
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2015-04-08 14:39:37 +03:00
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x86_stw_phys(cs, sm_state + offset, dt->selector);
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x86_stw_phys(cs, sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff);
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x86_stl_phys(cs, sm_state + offset + 4, dt->limit);
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x86_stq_phys(cs, sm_state + offset + 8, dt->base);
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2012-04-29 21:48:05 +04:00
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}
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2015-04-08 14:39:37 +03:00
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x86_stq_phys(cs, sm_state + 0x7e68, env->gdt.base);
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x86_stl_phys(cs, sm_state + 0x7e64, env->gdt.limit);
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2012-04-29 21:48:05 +04:00
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2015-04-08 14:39:37 +03:00
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x86_stw_phys(cs, sm_state + 0x7e70, env->ldt.selector);
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x86_stq_phys(cs, sm_state + 0x7e78, env->ldt.base);
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x86_stl_phys(cs, sm_state + 0x7e74, env->ldt.limit);
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x86_stw_phys(cs, sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff);
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2012-04-29 21:48:05 +04:00
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2015-04-08 14:39:37 +03:00
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x86_stq_phys(cs, sm_state + 0x7e88, env->idt.base);
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x86_stl_phys(cs, sm_state + 0x7e84, env->idt.limit);
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2012-04-29 21:48:05 +04:00
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2015-04-08 14:39:37 +03:00
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x86_stw_phys(cs, sm_state + 0x7e90, env->tr.selector);
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x86_stq_phys(cs, sm_state + 0x7e98, env->tr.base);
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x86_stl_phys(cs, sm_state + 0x7e94, env->tr.limit);
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x86_stw_phys(cs, sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff);
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2012-04-29 21:48:05 +04:00
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2015-07-02 17:57:14 +03:00
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/* ??? Vol 1, 16.5.6 Intel MPX and SMM says that IA32_BNDCFGS
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is saved at offset 7ED0. Vol 3, 34.4.1.1, Table 32-2, has
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7EA0-7ED7 as "reserved". What's this, and what's really
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supposed to happen? */
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2015-04-08 14:39:37 +03:00
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x86_stq_phys(cs, sm_state + 0x7ed0, env->efer);
|
2012-04-29 21:48:05 +04:00
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2015-04-08 14:39:37 +03:00
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x86_stq_phys(cs, sm_state + 0x7ff8, env->regs[R_EAX]);
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x86_stq_phys(cs, sm_state + 0x7ff0, env->regs[R_ECX]);
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x86_stq_phys(cs, sm_state + 0x7fe8, env->regs[R_EDX]);
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x86_stq_phys(cs, sm_state + 0x7fe0, env->regs[R_EBX]);
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x86_stq_phys(cs, sm_state + 0x7fd8, env->regs[R_ESP]);
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x86_stq_phys(cs, sm_state + 0x7fd0, env->regs[R_EBP]);
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x86_stq_phys(cs, sm_state + 0x7fc8, env->regs[R_ESI]);
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x86_stq_phys(cs, sm_state + 0x7fc0, env->regs[R_EDI]);
|
2012-04-29 21:48:05 +04:00
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for (i = 8; i < 16; i++) {
|
2015-04-08 14:39:37 +03:00
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x86_stq_phys(cs, sm_state + 0x7ff8 - i * 8, env->regs[i]);
|
2012-04-29 21:48:05 +04:00
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}
|
2015-04-08 14:39:37 +03:00
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x86_stq_phys(cs, sm_state + 0x7f78, env->eip);
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x86_stl_phys(cs, sm_state + 0x7f70, cpu_compute_eflags(env));
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x86_stl_phys(cs, sm_state + 0x7f68, env->dr[6]);
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x86_stl_phys(cs, sm_state + 0x7f60, env->dr[7]);
|
2012-04-29 21:48:05 +04:00
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|
2015-04-08 14:39:37 +03:00
|
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x86_stl_phys(cs, sm_state + 0x7f48, env->cr[4]);
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x86_stq_phys(cs, sm_state + 0x7f50, env->cr[3]);
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x86_stl_phys(cs, sm_state + 0x7f58, env->cr[0]);
|
2012-04-29 21:48:05 +04:00
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|
2015-04-08 14:39:37 +03:00
|
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x86_stl_phys(cs, sm_state + 0x7efc, SMM_REVISION_ID);
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x86_stl_phys(cs, sm_state + 0x7f00, env->smbase);
|
2012-04-29 21:48:05 +04:00
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#else
|
2015-04-08 14:39:37 +03:00
|
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x86_stl_phys(cs, sm_state + 0x7ffc, env->cr[0]);
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|
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|
x86_stl_phys(cs, sm_state + 0x7ff8, env->cr[3]);
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|
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|
x86_stl_phys(cs, sm_state + 0x7ff4, cpu_compute_eflags(env));
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|
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x86_stl_phys(cs, sm_state + 0x7ff0, env->eip);
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|
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x86_stl_phys(cs, sm_state + 0x7fec, env->regs[R_EDI]);
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|
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|
x86_stl_phys(cs, sm_state + 0x7fe8, env->regs[R_ESI]);
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|
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|
x86_stl_phys(cs, sm_state + 0x7fe4, env->regs[R_EBP]);
|
|
|
|
x86_stl_phys(cs, sm_state + 0x7fe0, env->regs[R_ESP]);
|
|
|
|
x86_stl_phys(cs, sm_state + 0x7fdc, env->regs[R_EBX]);
|
|
|
|
x86_stl_phys(cs, sm_state + 0x7fd8, env->regs[R_EDX]);
|
|
|
|
x86_stl_phys(cs, sm_state + 0x7fd4, env->regs[R_ECX]);
|
|
|
|
x86_stl_phys(cs, sm_state + 0x7fd0, env->regs[R_EAX]);
|
|
|
|
x86_stl_phys(cs, sm_state + 0x7fcc, env->dr[6]);
|
|
|
|
x86_stl_phys(cs, sm_state + 0x7fc8, env->dr[7]);
|
|
|
|
|
|
|
|
x86_stl_phys(cs, sm_state + 0x7fc4, env->tr.selector);
|
|
|
|
x86_stl_phys(cs, sm_state + 0x7f64, env->tr.base);
|
|
|
|
x86_stl_phys(cs, sm_state + 0x7f60, env->tr.limit);
|
|
|
|
x86_stl_phys(cs, sm_state + 0x7f5c, (env->tr.flags >> 8) & 0xf0ff);
|
|
|
|
|
|
|
|
x86_stl_phys(cs, sm_state + 0x7fc0, env->ldt.selector);
|
|
|
|
x86_stl_phys(cs, sm_state + 0x7f80, env->ldt.base);
|
|
|
|
x86_stl_phys(cs, sm_state + 0x7f7c, env->ldt.limit);
|
|
|
|
x86_stl_phys(cs, sm_state + 0x7f78, (env->ldt.flags >> 8) & 0xf0ff);
|
|
|
|
|
|
|
|
x86_stl_phys(cs, sm_state + 0x7f74, env->gdt.base);
|
|
|
|
x86_stl_phys(cs, sm_state + 0x7f70, env->gdt.limit);
|
|
|
|
|
|
|
|
x86_stl_phys(cs, sm_state + 0x7f58, env->idt.base);
|
|
|
|
x86_stl_phys(cs, sm_state + 0x7f54, env->idt.limit);
|
2012-04-29 21:48:05 +04:00
|
|
|
|
|
|
|
for (i = 0; i < 6; i++) {
|
|
|
|
dt = &env->segs[i];
|
|
|
|
if (i < 3) {
|
|
|
|
offset = 0x7f84 + i * 12;
|
|
|
|
} else {
|
|
|
|
offset = 0x7f2c + (i - 3) * 12;
|
|
|
|
}
|
2015-04-08 14:39:37 +03:00
|
|
|
x86_stl_phys(cs, sm_state + 0x7fa8 + i * 4, dt->selector);
|
|
|
|
x86_stl_phys(cs, sm_state + offset + 8, dt->base);
|
|
|
|
x86_stl_phys(cs, sm_state + offset + 4, dt->limit);
|
|
|
|
x86_stl_phys(cs, sm_state + offset, (dt->flags >> 8) & 0xf0ff);
|
2012-04-29 21:48:05 +04:00
|
|
|
}
|
2015-04-08 14:39:37 +03:00
|
|
|
x86_stl_phys(cs, sm_state + 0x7f14, env->cr[4]);
|
2012-04-29 21:48:05 +04:00
|
|
|
|
2015-04-08 14:39:37 +03:00
|
|
|
x86_stl_phys(cs, sm_state + 0x7efc, SMM_REVISION_ID);
|
|
|
|
x86_stl_phys(cs, sm_state + 0x7ef8, env->smbase);
|
2012-04-29 21:48:05 +04:00
|
|
|
#endif
|
|
|
|
/* init SMM cpu state */
|
|
|
|
|
|
|
|
#ifdef TARGET_X86_64
|
|
|
|
cpu_load_efer(env, 0);
|
|
|
|
#endif
|
|
|
|
cpu_load_eflags(env, 0, ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C |
|
|
|
|
DF_MASK));
|
|
|
|
env->eip = 0x00008000;
|
2014-04-30 00:38:10 +04:00
|
|
|
cpu_x86_update_cr0(env,
|
|
|
|
env->cr[0] & ~(CR0_PE_MASK | CR0_EM_MASK | CR0_TS_MASK |
|
|
|
|
CR0_PG_MASK));
|
|
|
|
cpu_x86_update_cr4(env, 0);
|
|
|
|
env->dr[7] = 0x00000400;
|
|
|
|
|
2012-04-29 21:48:05 +04:00
|
|
|
cpu_x86_load_seg_cache(env, R_CS, (env->smbase >> 4) & 0xffff, env->smbase,
|
2014-05-15 18:07:04 +04:00
|
|
|
0xffffffff,
|
|
|
|
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
|
2015-04-30 13:02:46 +03:00
|
|
|
DESC_G_MASK | DESC_A_MASK);
|
2014-05-15 18:07:04 +04:00
|
|
|
cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffffffff,
|
|
|
|
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
|
2015-04-30 13:02:46 +03:00
|
|
|
DESC_G_MASK | DESC_A_MASK);
|
2014-05-15 18:07:04 +04:00
|
|
|
cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffffffff,
|
|
|
|
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
|
2015-04-30 13:02:46 +03:00
|
|
|
DESC_G_MASK | DESC_A_MASK);
|
2014-05-15 18:07:04 +04:00
|
|
|
cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffffffff,
|
|
|
|
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
|
2015-04-30 13:02:46 +03:00
|
|
|
DESC_G_MASK | DESC_A_MASK);
|
2014-05-15 18:07:04 +04:00
|
|
|
cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffffffff,
|
|
|
|
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
|
2015-04-30 13:02:46 +03:00
|
|
|
DESC_G_MASK | DESC_A_MASK);
|
2014-05-15 18:07:04 +04:00
|
|
|
cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffffffff,
|
|
|
|
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
|
2015-04-30 13:02:46 +03:00
|
|
|
DESC_G_MASK | DESC_A_MASK);
|
2012-04-29 21:48:05 +04:00
|
|
|
}
|
|
|
|
|
2012-04-29 21:54:21 +04:00
|
|
|
void helper_rsm(CPUX86State *env)
|
2012-04-29 21:48:05 +04:00
|
|
|
{
|
2013-06-16 09:28:50 +04:00
|
|
|
X86CPU *cpu = x86_env_get_cpu(env);
|
2014-03-09 22:15:27 +04:00
|
|
|
CPUState *cs = CPU(cpu);
|
2012-04-29 21:48:05 +04:00
|
|
|
target_ulong sm_state;
|
|
|
|
int i, offset;
|
|
|
|
uint32_t val;
|
|
|
|
|
|
|
|
sm_state = env->smbase + 0x8000;
|
|
|
|
#ifdef TARGET_X86_64
|
2015-04-08 14:39:37 +03:00
|
|
|
cpu_load_efer(env, x86_ldq_phys(cs, sm_state + 0x7ed0));
|
|
|
|
|
|
|
|
env->gdt.base = x86_ldq_phys(cs, sm_state + 0x7e68);
|
|
|
|
env->gdt.limit = x86_ldl_phys(cs, sm_state + 0x7e64);
|
|
|
|
|
|
|
|
env->ldt.selector = x86_lduw_phys(cs, sm_state + 0x7e70);
|
|
|
|
env->ldt.base = x86_ldq_phys(cs, sm_state + 0x7e78);
|
|
|
|
env->ldt.limit = x86_ldl_phys(cs, sm_state + 0x7e74);
|
|
|
|
env->ldt.flags = (x86_lduw_phys(cs, sm_state + 0x7e72) & 0xf0ff) << 8;
|
|
|
|
|
|
|
|
env->idt.base = x86_ldq_phys(cs, sm_state + 0x7e88);
|
|
|
|
env->idt.limit = x86_ldl_phys(cs, sm_state + 0x7e84);
|
|
|
|
|
|
|
|
env->tr.selector = x86_lduw_phys(cs, sm_state + 0x7e90);
|
|
|
|
env->tr.base = x86_ldq_phys(cs, sm_state + 0x7e98);
|
|
|
|
env->tr.limit = x86_ldl_phys(cs, sm_state + 0x7e94);
|
|
|
|
env->tr.flags = (x86_lduw_phys(cs, sm_state + 0x7e92) & 0xf0ff) << 8;
|
|
|
|
|
|
|
|
env->regs[R_EAX] = x86_ldq_phys(cs, sm_state + 0x7ff8);
|
|
|
|
env->regs[R_ECX] = x86_ldq_phys(cs, sm_state + 0x7ff0);
|
|
|
|
env->regs[R_EDX] = x86_ldq_phys(cs, sm_state + 0x7fe8);
|
|
|
|
env->regs[R_EBX] = x86_ldq_phys(cs, sm_state + 0x7fe0);
|
|
|
|
env->regs[R_ESP] = x86_ldq_phys(cs, sm_state + 0x7fd8);
|
|
|
|
env->regs[R_EBP] = x86_ldq_phys(cs, sm_state + 0x7fd0);
|
|
|
|
env->regs[R_ESI] = x86_ldq_phys(cs, sm_state + 0x7fc8);
|
|
|
|
env->regs[R_EDI] = x86_ldq_phys(cs, sm_state + 0x7fc0);
|
2012-04-29 21:48:05 +04:00
|
|
|
for (i = 8; i < 16; i++) {
|
2015-04-08 14:39:37 +03:00
|
|
|
env->regs[i] = x86_ldq_phys(cs, sm_state + 0x7ff8 - i * 8);
|
2012-04-29 21:48:05 +04:00
|
|
|
}
|
2015-04-08 14:39:37 +03:00
|
|
|
env->eip = x86_ldq_phys(cs, sm_state + 0x7f78);
|
|
|
|
cpu_load_eflags(env, x86_ldl_phys(cs, sm_state + 0x7f70),
|
2012-04-29 21:48:05 +04:00
|
|
|
~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
|
2015-04-08 14:39:37 +03:00
|
|
|
env->dr[6] = x86_ldl_phys(cs, sm_state + 0x7f68);
|
|
|
|
env->dr[7] = x86_ldl_phys(cs, sm_state + 0x7f60);
|
2012-04-29 21:48:05 +04:00
|
|
|
|
2015-04-08 14:39:37 +03:00
|
|
|
cpu_x86_update_cr4(env, x86_ldl_phys(cs, sm_state + 0x7f48));
|
|
|
|
cpu_x86_update_cr3(env, x86_ldq_phys(cs, sm_state + 0x7f50));
|
|
|
|
cpu_x86_update_cr0(env, x86_ldl_phys(cs, sm_state + 0x7f58));
|
2012-04-29 21:48:05 +04:00
|
|
|
|
2014-04-30 00:38:10 +04:00
|
|
|
for (i = 0; i < 6; i++) {
|
|
|
|
offset = 0x7e00 + i * 16;
|
|
|
|
cpu_x86_load_seg_cache(env, i,
|
2015-04-08 14:39:37 +03:00
|
|
|
x86_lduw_phys(cs, sm_state + offset),
|
|
|
|
x86_ldq_phys(cs, sm_state + offset + 8),
|
|
|
|
x86_ldl_phys(cs, sm_state + offset + 4),
|
|
|
|
(x86_lduw_phys(cs, sm_state + offset + 2) &
|
2014-04-30 00:38:10 +04:00
|
|
|
0xf0ff) << 8);
|
|
|
|
}
|
|
|
|
|
2015-04-08 14:39:37 +03:00
|
|
|
val = x86_ldl_phys(cs, sm_state + 0x7efc); /* revision ID */
|
2012-04-29 21:48:05 +04:00
|
|
|
if (val & 0x20000) {
|
2015-10-12 19:25:40 +03:00
|
|
|
env->smbase = x86_ldl_phys(cs, sm_state + 0x7f00);
|
2012-04-29 21:48:05 +04:00
|
|
|
}
|
|
|
|
#else
|
2015-04-08 14:39:37 +03:00
|
|
|
cpu_x86_update_cr0(env, x86_ldl_phys(cs, sm_state + 0x7ffc));
|
|
|
|
cpu_x86_update_cr3(env, x86_ldl_phys(cs, sm_state + 0x7ff8));
|
|
|
|
cpu_load_eflags(env, x86_ldl_phys(cs, sm_state + 0x7ff4),
|
2012-04-29 21:48:05 +04:00
|
|
|
~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
|
2015-04-08 14:39:37 +03:00
|
|
|
env->eip = x86_ldl_phys(cs, sm_state + 0x7ff0);
|
|
|
|
env->regs[R_EDI] = x86_ldl_phys(cs, sm_state + 0x7fec);
|
|
|
|
env->regs[R_ESI] = x86_ldl_phys(cs, sm_state + 0x7fe8);
|
|
|
|
env->regs[R_EBP] = x86_ldl_phys(cs, sm_state + 0x7fe4);
|
|
|
|
env->regs[R_ESP] = x86_ldl_phys(cs, sm_state + 0x7fe0);
|
|
|
|
env->regs[R_EBX] = x86_ldl_phys(cs, sm_state + 0x7fdc);
|
|
|
|
env->regs[R_EDX] = x86_ldl_phys(cs, sm_state + 0x7fd8);
|
|
|
|
env->regs[R_ECX] = x86_ldl_phys(cs, sm_state + 0x7fd4);
|
|
|
|
env->regs[R_EAX] = x86_ldl_phys(cs, sm_state + 0x7fd0);
|
|
|
|
env->dr[6] = x86_ldl_phys(cs, sm_state + 0x7fcc);
|
|
|
|
env->dr[7] = x86_ldl_phys(cs, sm_state + 0x7fc8);
|
|
|
|
|
|
|
|
env->tr.selector = x86_ldl_phys(cs, sm_state + 0x7fc4) & 0xffff;
|
|
|
|
env->tr.base = x86_ldl_phys(cs, sm_state + 0x7f64);
|
|
|
|
env->tr.limit = x86_ldl_phys(cs, sm_state + 0x7f60);
|
|
|
|
env->tr.flags = (x86_ldl_phys(cs, sm_state + 0x7f5c) & 0xf0ff) << 8;
|
|
|
|
|
|
|
|
env->ldt.selector = x86_ldl_phys(cs, sm_state + 0x7fc0) & 0xffff;
|
|
|
|
env->ldt.base = x86_ldl_phys(cs, sm_state + 0x7f80);
|
|
|
|
env->ldt.limit = x86_ldl_phys(cs, sm_state + 0x7f7c);
|
|
|
|
env->ldt.flags = (x86_ldl_phys(cs, sm_state + 0x7f78) & 0xf0ff) << 8;
|
|
|
|
|
|
|
|
env->gdt.base = x86_ldl_phys(cs, sm_state + 0x7f74);
|
|
|
|
env->gdt.limit = x86_ldl_phys(cs, sm_state + 0x7f70);
|
|
|
|
|
|
|
|
env->idt.base = x86_ldl_phys(cs, sm_state + 0x7f58);
|
|
|
|
env->idt.limit = x86_ldl_phys(cs, sm_state + 0x7f54);
|
2012-04-29 21:48:05 +04:00
|
|
|
|
|
|
|
for (i = 0; i < 6; i++) {
|
|
|
|
if (i < 3) {
|
|
|
|
offset = 0x7f84 + i * 12;
|
|
|
|
} else {
|
|
|
|
offset = 0x7f2c + (i - 3) * 12;
|
|
|
|
}
|
|
|
|
cpu_x86_load_seg_cache(env, i,
|
2015-04-08 14:39:37 +03:00
|
|
|
x86_ldl_phys(cs,
|
2013-11-15 17:46:38 +04:00
|
|
|
sm_state + 0x7fa8 + i * 4) & 0xffff,
|
2015-04-08 14:39:37 +03:00
|
|
|
x86_ldl_phys(cs, sm_state + offset + 8),
|
|
|
|
x86_ldl_phys(cs, sm_state + offset + 4),
|
|
|
|
(x86_ldl_phys(cs,
|
2013-11-15 17:46:38 +04:00
|
|
|
sm_state + offset) & 0xf0ff) << 8);
|
2012-04-29 21:48:05 +04:00
|
|
|
}
|
2015-04-08 14:39:37 +03:00
|
|
|
cpu_x86_update_cr4(env, x86_ldl_phys(cs, sm_state + 0x7f14));
|
2012-04-29 21:48:05 +04:00
|
|
|
|
2015-04-08 14:39:37 +03:00
|
|
|
val = x86_ldl_phys(cs, sm_state + 0x7efc); /* revision ID */
|
2012-04-29 21:48:05 +04:00
|
|
|
if (val & 0x20000) {
|
2015-10-12 19:25:40 +03:00
|
|
|
env->smbase = x86_ldl_phys(cs, sm_state + 0x7ef8);
|
2012-04-29 21:48:05 +04:00
|
|
|
}
|
|
|
|
#endif
|
2015-04-22 12:40:41 +03:00
|
|
|
if ((env->hflags2 & HF2_SMM_INSIDE_NMI_MASK) == 0) {
|
|
|
|
env->hflags2 &= ~HF2_NMI_MASK;
|
|
|
|
}
|
|
|
|
env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
|
2012-04-29 21:48:05 +04:00
|
|
|
env->hflags &= ~HF_SMM_MASK;
|
tcg: drop global lock during TCG code execution
This finally allows TCG to benefit from the iothread introduction: Drop
the global mutex while running pure TCG CPU code. Reacquire the lock
when entering MMIO or PIO emulation, or when leaving the TCG loop.
We have to revert a few optimization for the current TCG threading
model, namely kicking the TCG thread in qemu_mutex_lock_iothread and not
kicking it in qemu_cpu_kick. We also need to disable RAM block
reordering until we have a more efficient locking mechanism at hand.
Still, a Linux x86 UP guest and my Musicpal ARM model boot fine here.
These numbers demonstrate where we gain something:
20338 jan 20 0 331m 75m 6904 R 99 0.9 0:50.95 qemu-system-arm
20337 jan 20 0 331m 75m 6904 S 20 0.9 0:26.50 qemu-system-arm
The guest CPU was fully loaded, but the iothread could still run mostly
independent on a second core. Without the patch we don't get beyond
32206 jan 20 0 330m 73m 7036 R 82 0.9 1:06.00 qemu-system-arm
32204 jan 20 0 330m 73m 7036 S 21 0.9 0:17.03 qemu-system-arm
We don't benefit significantly, though, when the guest is not fully
loading a host CPU.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Message-Id: <1439220437-23957-10-git-send-email-fred.konrad@greensocs.com>
[FK: Rebase, fix qemu_devices_reset deadlock, rm address_space_* mutex]
Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
[EGC: fixed iothread lock for cpu-exec IRQ handling]
Signed-off-by: Emilio G. Cota <cota@braap.org>
[AJB: -smp single-threaded fix, clean commit msg, BQL fixes]
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Pranith Kumar <bobby.prani@gmail.com>
[PM: target-arm changes]
Acked-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-23 21:29:11 +03:00
|
|
|
|
|
|
|
qemu_mutex_lock_iothread();
|
2015-03-31 15:12:25 +03:00
|
|
|
cpu_smm_update(cpu);
|
tcg: drop global lock during TCG code execution
This finally allows TCG to benefit from the iothread introduction: Drop
the global mutex while running pure TCG CPU code. Reacquire the lock
when entering MMIO or PIO emulation, or when leaving the TCG loop.
We have to revert a few optimization for the current TCG threading
model, namely kicking the TCG thread in qemu_mutex_lock_iothread and not
kicking it in qemu_cpu_kick. We also need to disable RAM block
reordering until we have a more efficient locking mechanism at hand.
Still, a Linux x86 UP guest and my Musicpal ARM model boot fine here.
These numbers demonstrate where we gain something:
20338 jan 20 0 331m 75m 6904 R 99 0.9 0:50.95 qemu-system-arm
20337 jan 20 0 331m 75m 6904 S 20 0.9 0:26.50 qemu-system-arm
The guest CPU was fully loaded, but the iothread could still run mostly
independent on a second core. Without the patch we don't get beyond
32206 jan 20 0 330m 73m 7036 R 82 0.9 1:06.00 qemu-system-arm
32204 jan 20 0 330m 73m 7036 S 21 0.9 0:17.03 qemu-system-arm
We don't benefit significantly, though, when the guest is not fully
loading a host CPU.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Message-Id: <1439220437-23957-10-git-send-email-fred.konrad@greensocs.com>
[FK: Rebase, fix qemu_devices_reset deadlock, rm address_space_* mutex]
Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
[EGC: fixed iothread lock for cpu-exec IRQ handling]
Signed-off-by: Emilio G. Cota <cota@braap.org>
[AJB: -smp single-threaded fix, clean commit msg, BQL fixes]
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Pranith Kumar <bobby.prani@gmail.com>
[PM: target-arm changes]
Acked-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-23 21:29:11 +03:00
|
|
|
qemu_mutex_unlock_iothread();
|
2012-04-29 21:48:05 +04:00
|
|
|
|
|
|
|
qemu_log_mask(CPU_LOG_INT, "SMM: after RSM\n");
|
2013-06-16 09:28:50 +04:00
|
|
|
log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP);
|
2012-04-29 21:48:05 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
#endif /* !CONFIG_USER_ONLY */
|