2018-05-18 19:48:07 +03:00
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/*
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* AArch64 translation, common definitions.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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2020-10-23 15:29:13 +03:00
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* version 2.1 of the License, or (at your option) any later version.
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2018-05-18 19:48:07 +03:00
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef TARGET_ARM_TRANSLATE_A64_H
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#define TARGET_ARM_TRANSLATE_A64_H
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TCGv_i64 cpu_reg(DisasContext *s, int reg);
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TCGv_i64 cpu_reg_sp(DisasContext *s, int reg);
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TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf);
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TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf);
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void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v);
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bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
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unsigned int imms, unsigned int immr);
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bool sve_access_check(DisasContext *s);
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2022-07-08 18:15:10 +03:00
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bool sme_enabled_check(DisasContext *s);
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bool sme_enabled_check_with_svcr(DisasContext *s, unsigned);
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/* This function corresponds to CheckStreamingSVEEnabled. */
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static inline bool sme_sm_enabled_check(DisasContext *s)
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{
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return sme_enabled_check_with_svcr(s, R_SVCR_SM_MASK);
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}
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/* This function corresponds to CheckSMEAndZAEnabled. */
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static inline bool sme_za_enabled_check(DisasContext *s)
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{
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return sme_enabled_check_with_svcr(s, R_SVCR_ZA_MASK);
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}
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/* Note that this function corresponds to CheckStreamingSVEAndZAEnabled. */
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static inline bool sme_smza_enabled_check(DisasContext *s)
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{
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return sme_enabled_check_with_svcr(s, R_SVCR_SM_MASK | R_SVCR_ZA_MASK);
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}
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2020-06-26 06:31:34 +03:00
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TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr);
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2020-06-26 06:31:21 +03:00
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TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write,
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bool tag_checked, int log2_size);
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2020-06-26 06:31:22 +03:00
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TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write,
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2021-04-16 21:31:06 +03:00
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bool tag_checked, int size);
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2018-05-18 19:48:07 +03:00
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/* We should have at some point before trying to access an FP register
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* done the necessary access check, so assert that
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* (a) we did the check and
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* (b) we didn't then just plough ahead anyway if it failed.
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* Print the instruction pattern in the abort message so we can figure
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* out what we need to fix if a user encounters this problem in the wild.
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*/
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static inline void assert_fp_access_checked(DisasContext *s)
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{
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#ifdef CONFIG_DEBUG_TCG
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if (unlikely(!s->fp_access_checked || s->fp_excp_el)) {
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fprintf(stderr, "target-arm: FP access check missing for "
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"instruction 0x%08x\n", s->insn);
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abort();
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}
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#endif
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}
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/* Return the offset into CPUARMState of an element of specified
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* size, 'element' places in from the least significant end of
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* the FP/vector register Qn.
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*/
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static inline int vec_reg_offset(DisasContext *s, int regno,
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2019-08-23 21:10:58 +03:00
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int element, MemOp size)
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2018-05-18 19:48:07 +03:00
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{
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2018-06-15 16:57:14 +03:00
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int element_size = 1 << size;
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int offs = element * element_size;
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2022-03-23 18:57:17 +03:00
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#if HOST_BIG_ENDIAN
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2018-05-18 19:48:07 +03:00
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/* This is complicated slightly because vfp.zregs[n].d[0] is
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2018-06-15 16:57:14 +03:00
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* still the lowest and vfp.zregs[n].d[15] the highest of the
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* 256 byte vector, even on big endian systems.
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*
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* Calculate the offset assuming fully little-endian,
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* then XOR to account for the order of the 8-byte units.
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*
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* For 16 byte elements, the two 8 byte halves will not form a
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* host int128 if the host is bigendian, since they're in the
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* wrong order. However the only 16 byte operation we have is
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* a move, so we can ignore this for the moment. More complicated
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* operations will have to special case loading and storing from
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* the zregs array.
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2018-05-18 19:48:07 +03:00
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*/
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2018-06-15 16:57:14 +03:00
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if (element_size < 8) {
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offs ^= 8 - element_size;
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}
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2018-05-18 19:48:07 +03:00
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#endif
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offs += offsetof(CPUARMState, vfp.zregs[regno]);
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assert_fp_access_checked(s);
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return offs;
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}
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/* Return the offset info CPUARMState of the "whole" vector register Qn. */
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static inline int vec_full_reg_offset(DisasContext *s, int regno)
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{
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assert_fp_access_checked(s);
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return offsetof(CPUARMState, vfp.zregs[regno]);
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}
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/* Return a newly allocated pointer to the vector register. */
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static inline TCGv_ptr vec_full_reg_ptr(DisasContext *s, int regno)
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{
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TCGv_ptr ret = tcg_temp_new_ptr();
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tcg_gen_addi_ptr(ret, cpu_env, vec_full_reg_offset(s, regno));
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return ret;
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}
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/* Return the byte size of the "whole" vector register, VL / 8. */
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static inline int vec_full_reg_size(DisasContext *s)
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{
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2022-06-08 21:38:54 +03:00
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return s->vl;
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2018-05-18 19:48:07 +03:00
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}
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2022-07-08 18:15:12 +03:00
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/* Return the byte size of the vector register, SVL / 8. */
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static inline int streaming_vec_reg_size(DisasContext *s)
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{
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return s->svl;
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}
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2022-06-20 20:52:04 +03:00
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/*
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* Return the offset info CPUARMState of the predicate vector register Pn.
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* Note for this purpose, FFR is P16.
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*/
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static inline int pred_full_reg_offset(DisasContext *s, int regno)
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{
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return offsetof(CPUARMState, vfp.pregs[regno]);
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}
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/* Return the byte size of the whole predicate register, VL / 64. */
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static inline int pred_full_reg_size(DisasContext *s)
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{
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return s->vl >> 3;
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}
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2022-07-08 18:15:12 +03:00
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/* Return the byte size of the predicate register, SVL / 64. */
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static inline int streaming_pred_reg_size(DisasContext *s)
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{
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return s->svl >> 3;
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}
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2022-06-20 20:52:04 +03:00
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/*
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* Round up the size of a register to a size allowed by
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* the tcg vector infrastructure. Any operation which uses this
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* size may assume that the bits above pred_full_reg_size are zero,
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* and must leave them the same way.
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*
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* Note that this is not needed for the vector registers as they
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* are always properly sized for tcg vectors.
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*/
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static inline int size_for_gvec(int size)
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{
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if (size <= 8) {
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return 8;
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} else {
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return QEMU_ALIGN_UP(size, 16);
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}
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}
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static inline int pred_gvec_reg_size(DisasContext *s)
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{
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return size_for_gvec(pred_full_reg_size(s));
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}
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2022-07-08 18:15:14 +03:00
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/* Return a newly allocated pointer to the predicate register. */
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static inline TCGv_ptr pred_full_reg_ptr(DisasContext *s, int regno)
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{
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TCGv_ptr ret = tcg_temp_new_ptr();
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tcg_gen_addi_ptr(ret, cpu_env, pred_full_reg_offset(s, regno));
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return ret;
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}
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2018-05-18 19:48:07 +03:00
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bool disas_sve(DisasContext *, uint32_t);
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2022-07-08 18:14:57 +03:00
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bool disas_sme(DisasContext *, uint32_t);
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2018-05-18 19:48:07 +03:00
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2020-05-15 00:28:27 +03:00
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void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
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uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
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2021-05-25 04:03:09 +03:00
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void gen_gvec_xar(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
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uint32_t rm_ofs, int64_t shift,
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uint32_t opr_sz, uint32_t max_sz);
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2020-05-15 00:28:27 +03:00
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2022-07-08 18:15:16 +03:00
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void gen_sve_ldr(DisasContext *s, TCGv_ptr, int vofs, int len, int rn, int imm);
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void gen_sve_str(DisasContext *s, TCGv_ptr, int vofs, int len, int rn, int imm);
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2018-05-18 19:48:07 +03:00
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#endif /* TARGET_ARM_TRANSLATE_A64_H */
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