404 lines
12 KiB
C
404 lines
12 KiB
C
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/*
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* ARM hflags
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*
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* This code is licensed under the GNU GPL v2 or later.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "internals.h"
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#include "exec/helper-proto.h"
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#include "cpregs.h"
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static inline bool fgt_svc(CPUARMState *env, int el)
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{
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/*
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* Assuming fine-grained-traps are active, return true if we
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* should be trapping on SVC instructions. Only AArch64 can
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* trap on an SVC at EL1, but we don't need to special-case this
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* because if this is AArch32 EL1 then arm_fgt_active() is false.
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* We also know el is 0 or 1.
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*/
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return el == 0 ?
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FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL0) :
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FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL1);
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}
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static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el,
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ARMMMUIdx mmu_idx,
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CPUARMTBFlags flags)
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{
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DP_TBFLAG_ANY(flags, FPEXC_EL, fp_el);
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DP_TBFLAG_ANY(flags, MMUIDX, arm_to_core_mmu_idx(mmu_idx));
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if (arm_singlestep_active(env)) {
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DP_TBFLAG_ANY(flags, SS_ACTIVE, 1);
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}
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return flags;
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}
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static CPUARMTBFlags rebuild_hflags_common_32(CPUARMState *env, int fp_el,
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ARMMMUIdx mmu_idx,
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CPUARMTBFlags flags)
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{
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bool sctlr_b = arm_sctlr_b(env);
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if (sctlr_b) {
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DP_TBFLAG_A32(flags, SCTLR__B, 1);
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}
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if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) {
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DP_TBFLAG_ANY(flags, BE_DATA, 1);
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}
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DP_TBFLAG_A32(flags, NS, !access_secure_reg(env));
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return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
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}
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static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el,
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ARMMMUIdx mmu_idx)
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{
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CPUARMTBFlags flags = {};
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uint32_t ccr = env->v7m.ccr[env->v7m.secure];
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/* Without HaveMainExt, CCR.UNALIGN_TRP is RES1. */
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if (ccr & R_V7M_CCR_UNALIGN_TRP_MASK) {
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DP_TBFLAG_ANY(flags, ALIGN_MEM, 1);
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}
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if (arm_v7m_is_handler_mode(env)) {
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DP_TBFLAG_M32(flags, HANDLER, 1);
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}
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/*
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* v8M always applies stack limit checks unless CCR.STKOFHFNMIGN
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* is suppressing them because the requested execution priority
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* is less than 0.
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*/
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if (arm_feature(env, ARM_FEATURE_V8) &&
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!((mmu_idx & ARM_MMU_IDX_M_NEGPRI) &&
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(ccr & R_V7M_CCR_STKOFHFNMIGN_MASK))) {
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DP_TBFLAG_M32(flags, STACKCHECK, 1);
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}
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if (arm_feature(env, ARM_FEATURE_M_SECURITY) && env->v7m.secure) {
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DP_TBFLAG_M32(flags, SECURE, 1);
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}
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return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
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}
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/* This corresponds to the ARM pseudocode function IsFullA64Enabled(). */
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static bool sme_fa64(CPUARMState *env, int el)
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{
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if (!cpu_isar_feature(aa64_sme_fa64, env_archcpu(env))) {
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return false;
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}
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if (el <= 1 && !el_is_in_host(env, el)) {
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if (!FIELD_EX64(env->vfp.smcr_el[1], SMCR, FA64)) {
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return false;
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}
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}
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if (el <= 2 && arm_is_el2_enabled(env)) {
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if (!FIELD_EX64(env->vfp.smcr_el[2], SMCR, FA64)) {
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return false;
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}
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}
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if (arm_feature(env, ARM_FEATURE_EL3)) {
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if (!FIELD_EX64(env->vfp.smcr_el[3], SMCR, FA64)) {
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return false;
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}
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}
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return true;
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}
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static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
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ARMMMUIdx mmu_idx)
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{
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CPUARMTBFlags flags = {};
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int el = arm_current_el(env);
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if (arm_sctlr(env, el) & SCTLR_A) {
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DP_TBFLAG_ANY(flags, ALIGN_MEM, 1);
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}
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if (arm_el_is_aa64(env, 1)) {
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DP_TBFLAG_A32(flags, VFPEN, 1);
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}
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if (el < 2 && env->cp15.hstr_el2 && arm_is_el2_enabled(env) &&
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(arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
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DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1);
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}
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if (arm_fgt_active(env, el)) {
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DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
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if (fgt_svc(env, el)) {
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DP_TBFLAG_ANY(flags, FGT_SVC, 1);
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}
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}
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if (env->uncached_cpsr & CPSR_IL) {
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DP_TBFLAG_ANY(flags, PSTATE__IL, 1);
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}
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/*
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* The SME exception we are testing for is raised via
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* AArch64.CheckFPAdvSIMDEnabled(), as called from
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* AArch32.CheckAdvSIMDOrFPEnabled().
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*/
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if (el == 0
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&& FIELD_EX64(env->svcr, SVCR, SM)
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&& (!arm_is_el2_enabled(env)
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|| (arm_el_is_aa64(env, 2) && !(env->cp15.hcr_el2 & HCR_TGE)))
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&& arm_el_is_aa64(env, 1)
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&& !sme_fa64(env, el)) {
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DP_TBFLAG_A32(flags, SME_TRAP_NONSTREAMING, 1);
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}
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return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
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}
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static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
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ARMMMUIdx mmu_idx)
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{
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CPUARMTBFlags flags = {};
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ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx);
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uint64_t tcr = regime_tcr(env, mmu_idx);
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uint64_t sctlr;
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int tbii, tbid;
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DP_TBFLAG_ANY(flags, AARCH64_STATE, 1);
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/* Get control bits for tagged addresses. */
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tbid = aa64_va_parameter_tbi(tcr, mmu_idx);
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tbii = tbid & ~aa64_va_parameter_tbid(tcr, mmu_idx);
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DP_TBFLAG_A64(flags, TBII, tbii);
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DP_TBFLAG_A64(flags, TBID, tbid);
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if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
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int sve_el = sve_exception_el(env, el);
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/*
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* If either FP or SVE are disabled, translator does not need len.
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* If SVE EL > FP EL, FP exception has precedence, and translator
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* does not need SVE EL. Save potential re-translations by forcing
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* the unneeded data to zero.
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*/
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if (fp_el != 0) {
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if (sve_el > fp_el) {
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sve_el = 0;
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}
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} else if (sve_el == 0) {
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DP_TBFLAG_A64(flags, VL, sve_vqm1_for_el(env, el));
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}
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DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el);
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}
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if (cpu_isar_feature(aa64_sme, env_archcpu(env))) {
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int sme_el = sme_exception_el(env, el);
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bool sm = FIELD_EX64(env->svcr, SVCR, SM);
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DP_TBFLAG_A64(flags, SMEEXC_EL, sme_el);
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if (sme_el == 0) {
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/* Similarly, do not compute SVL if SME is disabled. */
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int svl = sve_vqm1_for_el_sm(env, el, true);
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DP_TBFLAG_A64(flags, SVL, svl);
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if (sm) {
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/* If SVE is disabled, we will not have set VL above. */
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DP_TBFLAG_A64(flags, VL, svl);
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}
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}
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if (sm) {
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DP_TBFLAG_A64(flags, PSTATE_SM, 1);
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DP_TBFLAG_A64(flags, SME_TRAP_NONSTREAMING, !sme_fa64(env, el));
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}
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DP_TBFLAG_A64(flags, PSTATE_ZA, FIELD_EX64(env->svcr, SVCR, ZA));
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}
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sctlr = regime_sctlr(env, stage1);
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if (sctlr & SCTLR_A) {
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DP_TBFLAG_ANY(flags, ALIGN_MEM, 1);
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}
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if (arm_cpu_data_is_big_endian_a64(el, sctlr)) {
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DP_TBFLAG_ANY(flags, BE_DATA, 1);
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}
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if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) {
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/*
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* In order to save space in flags, we record only whether
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* pauth is "inactive", meaning all insns are implemented as
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* a nop, or "active" when some action must be performed.
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* The decision of which action to take is left to a helper.
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*/
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if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) {
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DP_TBFLAG_A64(flags, PAUTH_ACTIVE, 1);
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}
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}
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if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
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/* Note that SCTLR_EL[23].BT == SCTLR_BT1. */
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if (sctlr & (el == 0 ? SCTLR_BT0 : SCTLR_BT1)) {
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DP_TBFLAG_A64(flags, BT, 1);
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}
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}
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/* Compute the condition for using AccType_UNPRIV for LDTR et al. */
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if (!(env->pstate & PSTATE_UAO)) {
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switch (mmu_idx) {
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case ARMMMUIdx_E10_1:
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case ARMMMUIdx_E10_1_PAN:
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/* TODO: ARMv8.3-NV */
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DP_TBFLAG_A64(flags, UNPRIV, 1);
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break;
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case ARMMMUIdx_E20_2:
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case ARMMMUIdx_E20_2_PAN:
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/*
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* Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is
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* gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR.
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*/
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if (env->cp15.hcr_el2 & HCR_TGE) {
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DP_TBFLAG_A64(flags, UNPRIV, 1);
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}
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break;
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default:
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break;
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}
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}
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if (env->pstate & PSTATE_IL) {
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DP_TBFLAG_ANY(flags, PSTATE__IL, 1);
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}
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if (arm_fgt_active(env, el)) {
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DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
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if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET)) {
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DP_TBFLAG_A64(flags, FGT_ERET, 1);
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}
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if (fgt_svc(env, el)) {
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DP_TBFLAG_ANY(flags, FGT_SVC, 1);
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}
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}
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if (cpu_isar_feature(aa64_mte, env_archcpu(env))) {
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/*
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* Set MTE_ACTIVE if any access may be Checked, and leave clear
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* if all accesses must be Unchecked:
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* 1) If no TBI, then there are no tags in the address to check,
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* 2) If Tag Check Override, then all accesses are Unchecked,
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* 3) If Tag Check Fail == 0, then Checked access have no effect,
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* 4) If no Allocation Tag Access, then all accesses are Unchecked.
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*/
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if (allocation_tag_access_enabled(env, el, sctlr)) {
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DP_TBFLAG_A64(flags, ATA, 1);
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if (tbid
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&& !(env->pstate & PSTATE_TCO)
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&& (sctlr & (el == 0 ? SCTLR_TCF0 : SCTLR_TCF))) {
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DP_TBFLAG_A64(flags, MTE_ACTIVE, 1);
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}
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}
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/* And again for unprivileged accesses, if required. */
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if (EX_TBFLAG_A64(flags, UNPRIV)
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&& tbid
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&& !(env->pstate & PSTATE_TCO)
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&& (sctlr & SCTLR_TCF0)
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&& allocation_tag_access_enabled(env, 0, sctlr)) {
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DP_TBFLAG_A64(flags, MTE0_ACTIVE, 1);
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}
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/* Cache TCMA as well as TBI. */
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DP_TBFLAG_A64(flags, TCMA, aa64_va_parameter_tcma(tcr, mmu_idx));
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}
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return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
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}
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static CPUARMTBFlags rebuild_hflags_internal(CPUARMState *env)
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{
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int el = arm_current_el(env);
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int fp_el = fp_exception_el(env, el);
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ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
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if (is_a64(env)) {
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return rebuild_hflags_a64(env, el, fp_el, mmu_idx);
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} else if (arm_feature(env, ARM_FEATURE_M)) {
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return rebuild_hflags_m32(env, fp_el, mmu_idx);
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} else {
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return rebuild_hflags_a32(env, fp_el, mmu_idx);
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}
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}
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void arm_rebuild_hflags(CPUARMState *env)
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{
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env->hflags = rebuild_hflags_internal(env);
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}
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/*
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* If we have triggered a EL state change we can't rely on the
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* translator having passed it to us, we need to recompute.
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*/
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void HELPER(rebuild_hflags_m32_newel)(CPUARMState *env)
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{
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int el = arm_current_el(env);
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int fp_el = fp_exception_el(env, el);
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ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
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env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx);
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}
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void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el)
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{
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int fp_el = fp_exception_el(env, el);
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ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
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env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx);
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}
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/*
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* If we have triggered a EL state change we can't rely on the
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* translator having passed it to us, we need to recompute.
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*/
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void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env)
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{
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int el = arm_current_el(env);
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int fp_el = fp_exception_el(env, el);
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ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
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env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx);
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}
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void HELPER(rebuild_hflags_a32)(CPUARMState *env, int el)
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{
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int fp_el = fp_exception_el(env, el);
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ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
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env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx);
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}
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void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el)
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{
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int fp_el = fp_exception_el(env, el);
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ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
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|
|
||
|
env->hflags = rebuild_hflags_a64(env, el, fp_el, mmu_idx);
|
||
|
}
|
||
|
|
||
|
void assert_hflags_rebuild_correctly(CPUARMState *env)
|
||
|
{
|
||
|
#ifdef CONFIG_DEBUG_TCG
|
||
|
CPUARMTBFlags c = env->hflags;
|
||
|
CPUARMTBFlags r = rebuild_hflags_internal(env);
|
||
|
|
||
|
if (unlikely(c.flags != r.flags || c.flags2 != r.flags2)) {
|
||
|
fprintf(stderr, "TCG hflags mismatch "
|
||
|
"(current:(0x%08x,0x" TARGET_FMT_lx ")"
|
||
|
" rebuilt:(0x%08x,0x" TARGET_FMT_lx ")\n",
|
||
|
c.flags, c.flags2, r.flags, r.flags2);
|
||
|
abort();
|
||
|
}
|
||
|
#endif
|
||
|
}
|