2006-05-13 20:11:23 +04:00
|
|
|
/*
|
|
|
|
* QEMU PREP PCI host
|
|
|
|
*
|
|
|
|
* Copyright (c) 2006 Fabrice Bellard
|
2007-09-17 01:08:06 +04:00
|
|
|
*
|
2006-05-13 20:11:23 +04:00
|
|
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
|
|
|
* of this software and associated documentation files (the "Software"), to deal
|
|
|
|
* in the Software without restriction, including without limitation the rights
|
|
|
|
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
|
|
|
* copies of the Software, and to permit persons to whom the Software is
|
|
|
|
* furnished to do so, subject to the following conditions:
|
|
|
|
*
|
|
|
|
* The above copyright notice and this permission notice shall be included in
|
|
|
|
* all copies or substantial portions of the Software.
|
|
|
|
*
|
|
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
|
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
|
|
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
|
|
|
* THE SOFTWARE.
|
|
|
|
*/
|
|
|
|
|
2007-11-17 20:14:51 +03:00
|
|
|
#include "hw.h"
|
|
|
|
#include "pci.h"
|
2006-05-13 20:11:23 +04:00
|
|
|
#include "pci_host.h"
|
2009-11-11 15:59:56 +03:00
|
|
|
#include "prep_pci.h"
|
2006-05-13 20:11:23 +04:00
|
|
|
|
|
|
|
typedef PCIHostState PREPPCIState;
|
|
|
|
|
2009-10-02 01:12:16 +04:00
|
|
|
static inline uint32_t PPC_PCIIO_config(target_phys_addr_t addr)
|
2006-05-13 20:11:23 +04:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for(i = 0; i < 11; i++) {
|
|
|
|
if ((addr & (1 << (11 + i))) != 0)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return (addr & 0x7ff) | (i << 11);
|
|
|
|
}
|
|
|
|
|
2009-10-02 01:12:16 +04:00
|
|
|
static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
|
2006-05-13 20:11:23 +04:00
|
|
|
{
|
|
|
|
PREPPCIState *s = opaque;
|
|
|
|
pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 1);
|
|
|
|
}
|
|
|
|
|
2009-10-02 01:12:16 +04:00
|
|
|
static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
|
2006-05-13 20:11:23 +04:00
|
|
|
{
|
|
|
|
PREPPCIState *s = opaque;
|
|
|
|
val = bswap16(val);
|
|
|
|
pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 2);
|
|
|
|
}
|
|
|
|
|
2009-10-02 01:12:16 +04:00
|
|
|
static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
|
2006-05-13 20:11:23 +04:00
|
|
|
{
|
|
|
|
PREPPCIState *s = opaque;
|
|
|
|
val = bswap32(val);
|
|
|
|
pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 4);
|
|
|
|
}
|
|
|
|
|
2009-10-02 01:12:16 +04:00
|
|
|
static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr)
|
2006-05-13 20:11:23 +04:00
|
|
|
{
|
|
|
|
PREPPCIState *s = opaque;
|
|
|
|
uint32_t val;
|
|
|
|
val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 1);
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
2009-10-02 01:12:16 +04:00
|
|
|
static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr)
|
2006-05-13 20:11:23 +04:00
|
|
|
{
|
|
|
|
PREPPCIState *s = opaque;
|
|
|
|
uint32_t val;
|
|
|
|
val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 2);
|
|
|
|
val = bswap16(val);
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
2009-10-02 01:12:16 +04:00
|
|
|
static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr)
|
2006-05-13 20:11:23 +04:00
|
|
|
{
|
|
|
|
PREPPCIState *s = opaque;
|
|
|
|
uint32_t val;
|
|
|
|
val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 4);
|
|
|
|
val = bswap32(val);
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
2009-08-25 22:29:31 +04:00
|
|
|
static CPUWriteMemoryFunc * const PPC_PCIIO_write[] = {
|
2006-05-13 20:11:23 +04:00
|
|
|
&PPC_PCIIO_writeb,
|
|
|
|
&PPC_PCIIO_writew,
|
|
|
|
&PPC_PCIIO_writel,
|
|
|
|
};
|
|
|
|
|
2009-08-25 22:29:31 +04:00
|
|
|
static CPUReadMemoryFunc * const PPC_PCIIO_read[] = {
|
2006-05-13 20:11:23 +04:00
|
|
|
&PPC_PCIIO_readb,
|
|
|
|
&PPC_PCIIO_readw,
|
|
|
|
&PPC_PCIIO_readl,
|
|
|
|
};
|
|
|
|
|
2006-09-24 04:16:34 +04:00
|
|
|
static int prep_map_irq(PCIDevice *pci_dev, int irq_num)
|
2006-05-13 20:11:23 +04:00
|
|
|
{
|
2006-09-24 21:01:44 +04:00
|
|
|
return (irq_num + (pci_dev->devfn >> 3)) & 1;
|
2006-09-24 04:16:34 +04:00
|
|
|
}
|
|
|
|
|
2009-08-28 17:28:17 +04:00
|
|
|
static void prep_set_irq(void *opaque, int irq_num, int level)
|
2006-09-24 04:16:34 +04:00
|
|
|
{
|
2009-08-28 17:28:17 +04:00
|
|
|
qemu_irq *pic = opaque;
|
|
|
|
|
2007-10-29 13:24:59 +03:00
|
|
|
qemu_set_irq(pic[(irq_num & 1) ? 11 : 9] , level);
|
2006-05-13 20:11:23 +04:00
|
|
|
}
|
|
|
|
|
2011-08-08 17:09:04 +04:00
|
|
|
PCIBus *pci_prep_init(qemu_irq *pic,
|
|
|
|
MemoryRegion *address_space_mem,
|
|
|
|
MemoryRegion *address_space_io)
|
2006-05-13 20:11:23 +04:00
|
|
|
{
|
|
|
|
PREPPCIState *s;
|
|
|
|
PCIDevice *d;
|
|
|
|
int PPC_io_memory;
|
|
|
|
|
2011-08-21 07:09:37 +04:00
|
|
|
s = g_malloc0(sizeof(PREPPCIState));
|
2009-05-23 03:05:19 +04:00
|
|
|
s->bus = pci_register_bus(NULL, "pci",
|
2011-07-26 15:26:19 +04:00
|
|
|
prep_set_irq, prep_map_irq, pic,
|
2011-08-08 17:09:04 +04:00
|
|
|
address_space_mem,
|
|
|
|
address_space_io,
|
|
|
|
0, 4);
|
2006-05-13 20:11:23 +04:00
|
|
|
|
2011-07-24 18:47:18 +04:00
|
|
|
memory_region_init_io(&s->conf_mem, &pci_host_conf_be_ops, s,
|
|
|
|
"pci-conf-idx", 1);
|
|
|
|
memory_region_add_subregion(address_space_io, 0xcf8, &s->conf_mem);
|
|
|
|
sysbus_init_ioports(&s->busdev, 0xcf8, 1);
|
|
|
|
|
2011-09-25 18:15:43 +04:00
|
|
|
memory_region_init_io(&s->data_mem, &pci_host_data_be_ops, s,
|
2011-07-24 18:47:18 +04:00
|
|
|
"pci-conf-data", 1);
|
|
|
|
memory_region_add_subregion(address_space_io, 0xcfc, &s->data_mem);
|
|
|
|
sysbus_init_ioports(&s->busdev, 0xcfc, 1);
|
2006-05-13 20:11:23 +04:00
|
|
|
|
2009-06-14 12:38:51 +04:00
|
|
|
PPC_io_memory = cpu_register_io_memory(PPC_PCIIO_read,
|
2010-12-08 14:05:37 +03:00
|
|
|
PPC_PCIIO_write, s,
|
|
|
|
DEVICE_NATIVE_ENDIAN);
|
2006-05-13 20:11:23 +04:00
|
|
|
cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory);
|
|
|
|
|
2007-09-17 01:08:06 +04:00
|
|
|
/* PCI host bridge */
|
|
|
|
d = pci_register_device(s->bus, "PREP Host Bridge - Motorola Raven",
|
2006-05-13 20:11:23 +04:00
|
|
|
sizeof(PCIDevice), 0, NULL, NULL);
|
2009-01-26 18:37:35 +03:00
|
|
|
pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MOTOROLA);
|
|
|
|
pci_config_set_device_id(d->config, PCI_DEVICE_ID_MOTOROLA_RAVEN);
|
2006-05-13 20:11:23 +04:00
|
|
|
d->config[0x08] = 0x00; // revision
|
2009-02-01 22:26:20 +03:00
|
|
|
pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
|
2006-05-13 20:11:23 +04:00
|
|
|
d->config[0x0C] = 0x08; // cache_line_size
|
|
|
|
d->config[0x0D] = 0x10; // latency_timer
|
|
|
|
d->config[0x34] = 0x00; // capabilities_pointer
|
|
|
|
|
|
|
|
return s->bus;
|
|
|
|
}
|