2023-03-10 09:11:25 +03:00
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/*
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* libqos driver framework
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*
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* Copyright (c) 2022-2023 Red Hat, Inc.
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* Copyright (c) 2018 Emanuele Giuseppe Esposito <e.emanuelegiuseppe@gmail.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License version 2.1 as published by the Free Software Foundation.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>
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*/
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#include "qemu/osdep.h"
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#include "hw/net/igb_regs.h"
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#include "hw/net/mii.h"
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#include "hw/pci/pci_ids.h"
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#include "../libqtest.h"
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#include "pci-pc.h"
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#include "qemu/sockets.h"
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#include "qemu/iov.h"
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#include "qemu/module.h"
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#include "qemu/bitops.h"
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#include "libqos-malloc.h"
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#include "qgraph.h"
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#include "e1000e.h"
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#define IGB_IVAR_TEST_CFG \
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((E1000E_RX0_MSG_ID | E1000_IVAR_VALID) << (igb_ivar_entry_rx(0) * 8) | \
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((E1000E_TX0_MSG_ID | E1000_IVAR_VALID) << (igb_ivar_entry_tx(0) * 8)))
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#define E1000E_RING_LEN (0x1000)
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static void e1000e_foreach_callback(QPCIDevice *dev, int devfn, void *data)
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{
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QPCIDevice *res = data;
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memcpy(res, dev, sizeof(QPCIDevice));
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g_free(dev);
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}
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static void e1000e_pci_destructor(QOSGraphObject *obj)
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{
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QE1000E_PCI *epci = (QE1000E_PCI *) obj;
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qpci_iounmap(&epci->pci_dev, epci->mac_regs);
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qpci_msix_disable(&epci->pci_dev);
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}
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static void igb_pci_start_hw(QOSGraphObject *obj)
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{
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static const uint8_t address[] = E1000E_ADDRESS;
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QE1000E_PCI *d = (QE1000E_PCI *) obj;
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uint32_t val;
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/* Enable the device */
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qpci_device_enable(&d->pci_dev);
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/* Reset the device */
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val = e1000e_macreg_read(&d->e1000e, E1000_CTRL);
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e1000e_macreg_write(&d->e1000e, E1000_CTRL, val | E1000_CTRL_RST | E1000_CTRL_SLU);
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/* Setup link */
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e1000e_macreg_write(&d->e1000e, E1000_MDIC,
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MII_BMCR_AUTOEN | MII_BMCR_ANRESTART |
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(MII_BMCR << E1000_MDIC_REG_SHIFT) |
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(1 << E1000_MDIC_PHY_SHIFT) |
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E1000_MDIC_OP_WRITE);
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qtest_clock_step(d->pci_dev.bus->qts, 900000000);
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/* Enable and configure MSI-X */
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qpci_msix_enable(&d->pci_dev);
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e1000e_macreg_write(&d->e1000e, E1000_IVAR0, IGB_IVAR_TEST_CFG);
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/* Check the device link status */
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val = e1000e_macreg_read(&d->e1000e, E1000_STATUS);
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g_assert_cmphex(val & E1000_STATUS_LU, ==, E1000_STATUS_LU);
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/* Initialize TX/RX logic */
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e1000e_macreg_write(&d->e1000e, E1000_RCTL, 0);
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e1000e_macreg_write(&d->e1000e, E1000_TCTL, 0);
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e1000e_macreg_write(&d->e1000e, E1000_TDBAL(0),
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(uint32_t) d->e1000e.tx_ring);
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e1000e_macreg_write(&d->e1000e, E1000_TDBAH(0),
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(uint32_t) (d->e1000e.tx_ring >> 32));
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e1000e_macreg_write(&d->e1000e, E1000_TDLEN(0), E1000E_RING_LEN);
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e1000e_macreg_write(&d->e1000e, E1000_TDT(0), 0);
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e1000e_macreg_write(&d->e1000e, E1000_TDH(0), 0);
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/* Enable transmit */
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e1000e_macreg_write(&d->e1000e, E1000_TCTL, E1000_TCTL_EN);
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e1000e_macreg_write(&d->e1000e, E1000_RDBAL(0),
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(uint32_t)d->e1000e.rx_ring);
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e1000e_macreg_write(&d->e1000e, E1000_RDBAH(0),
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(uint32_t)(d->e1000e.rx_ring >> 32));
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e1000e_macreg_write(&d->e1000e, E1000_RDLEN(0), E1000E_RING_LEN);
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e1000e_macreg_write(&d->e1000e, E1000_RDT(0), 0);
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e1000e_macreg_write(&d->e1000e, E1000_RDH(0), 0);
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e1000e_macreg_write(&d->e1000e, E1000_RA,
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le32_to_cpu(*(uint32_t *)address));
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e1000e_macreg_write(&d->e1000e, E1000_RA + 4,
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E1000_RAH_AV | E1000_RAH_POOL_1 |
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le16_to_cpu(*(uint16_t *)(address + 4)));
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/* Enable receive */
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e1000e_macreg_write(&d->e1000e, E1000_RFCTL, E1000_RFCTL_EXTEN);
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e1000e_macreg_write(&d->e1000e, E1000_RCTL, E1000_RCTL_EN);
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/* Enable all interrupts */
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2023-05-23 05:43:24 +03:00
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e1000e_macreg_write(&d->e1000e, E1000_GPIE, E1000_GPIE_MSIX_MODE);
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2023-03-10 09:11:25 +03:00
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e1000e_macreg_write(&d->e1000e, E1000_IMS, 0xFFFFFFFF);
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e1000e_macreg_write(&d->e1000e, E1000_EIMS, 0xFFFFFFFF);
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}
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static void *igb_pci_get_driver(void *obj, const char *interface)
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{
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QE1000E_PCI *epci = obj;
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if (!g_strcmp0(interface, "igb-if")) {
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return &epci->e1000e;
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}
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/* implicit contains */
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if (!g_strcmp0(interface, "pci-device")) {
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return &epci->pci_dev;
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}
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fprintf(stderr, "%s not present in igb\n", interface);
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g_assert_not_reached();
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}
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static void *igb_pci_create(void *pci_bus, QGuestAllocator *alloc, void *addr)
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{
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QE1000E_PCI *d = g_new0(QE1000E_PCI, 1);
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QPCIBus *bus = pci_bus;
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QPCIAddress *address = addr;
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qpci_device_foreach(bus, address->vendor_id, address->device_id,
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e1000e_foreach_callback, &d->pci_dev);
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/* Map BAR0 (mac registers) */
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d->mac_regs = qpci_iomap(&d->pci_dev, 0, NULL);
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/* Allocate and setup TX ring */
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d->e1000e.tx_ring = guest_alloc(alloc, E1000E_RING_LEN);
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g_assert(d->e1000e.tx_ring != 0);
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/* Allocate and setup RX ring */
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d->e1000e.rx_ring = guest_alloc(alloc, E1000E_RING_LEN);
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g_assert(d->e1000e.rx_ring != 0);
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d->obj.get_driver = igb_pci_get_driver;
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d->obj.start_hw = igb_pci_start_hw;
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d->obj.destructor = e1000e_pci_destructor;
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return &d->obj;
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}
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static void igb_register_nodes(void)
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{
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QPCIAddress addr = {
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.vendor_id = PCI_VENDOR_ID_INTEL,
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.device_id = E1000_DEV_ID_82576,
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};
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/*
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* FIXME: every test using this node needs to setup a -netdev socket,id=hs0
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* otherwise QEMU is not going to start
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*/
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QOSGraphEdgeOptions opts = {
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.extra_device_opts = "netdev=hs0",
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};
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add_qpci_address(&opts, &addr);
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qos_node_create_driver("igb", igb_pci_create);
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qos_node_consumes("igb", "pci-bus", &opts);
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}
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libqos_init(igb_register_nodes);
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