2009-08-31 18:07:18 +04:00
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/*
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2021-12-07 01:45:25 +03:00
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* QEMU MMIO VGA Emulator.
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2009-08-31 18:07:18 +04:00
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2019-08-12 08:23:45 +03:00
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2016-01-26 21:17:13 +03:00
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#include "qemu/osdep.h"
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2021-12-07 01:45:27 +03:00
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#include "qapi/error.h"
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#include "hw/sysbus.h"
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#include "hw/display/vga.h"
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#include "hw/qdev-properties.h"
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2013-03-18 20:36:02 +04:00
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#include "vga_int.h"
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2009-08-31 18:07:18 +04:00
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2021-12-07 01:45:27 +03:00
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/*
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* QEMU interface:
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* + sysbus MMIO region 0: VGA I/O registers
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* + sysbus MMIO region 1: VGA MMIO registers
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* + sysbus MMIO region 2: VGA memory
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*/
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OBJECT_DECLARE_SIMPLE_TYPE(VGAMmioState, VGA_MMIO)
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2012-05-24 11:59:44 +04:00
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2021-12-07 01:45:27 +03:00
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struct VGAMmioState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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2009-08-31 18:07:18 +04:00
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VGACommonState vga;
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2021-12-07 01:45:27 +03:00
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MemoryRegion iomem;
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MemoryRegion lowmem;
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uint8_t it_shift;
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};
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2009-08-31 18:07:18 +04:00
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2018-08-02 18:51:46 +03:00
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static uint64_t vga_mm_read(void *opaque, hwaddr addr, unsigned size)
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2009-08-31 18:07:18 +04:00
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{
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2021-12-07 01:45:25 +03:00
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VGAMmioState *s = opaque;
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2009-08-31 18:07:18 +04:00
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2018-08-02 18:51:46 +03:00
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return vga_ioport_read(&s->vga, addr >> s->it_shift) &
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MAKE_64BIT_MASK(0, size * 8);
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2009-08-31 18:07:18 +04:00
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}
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2018-08-02 18:51:46 +03:00
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static void vga_mm_write(void *opaque, hwaddr addr, uint64_t value,
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unsigned size)
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2009-08-31 18:07:18 +04:00
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{
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2021-12-07 01:45:25 +03:00
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VGAMmioState *s = opaque;
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2009-08-31 18:07:18 +04:00
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2018-08-02 18:51:46 +03:00
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vga_ioport_write(&s->vga, addr >> s->it_shift,
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value & MAKE_64BIT_MASK(0, size * 8));
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2009-08-31 18:07:18 +04:00
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}
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2011-08-08 17:08:57 +04:00
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static const MemoryRegionOps vga_mm_ctrl_ops = {
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2018-08-02 18:51:46 +03:00
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.read = vga_mm_read,
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.write = vga_mm_write,
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.valid.min_access_size = 1,
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.valid.max_access_size = 4,
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.impl.min_access_size = 1,
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.impl.max_access_size = 4,
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2011-08-08 17:08:57 +04:00
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.endianness = DEVICE_NATIVE_ENDIAN,
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2009-08-31 18:07:18 +04:00
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};
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2021-12-07 01:45:27 +03:00
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static void vga_mmio_reset(DeviceState *dev)
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{
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VGAMmioState *s = VGA_MMIO(dev);
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vga_common_reset(&s->vga);
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}
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static void vga_mmio_realizefn(DeviceState *dev, Error **errp)
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{
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VGAMmioState *s = VGA_MMIO(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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memory_region_init_io(&s->iomem, OBJECT(dev), &vga_mm_ctrl_ops, s,
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"vga-mmio", 0x100000);
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memory_region_set_flush_coalesced(&s->iomem);
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sysbus_init_mmio(sbd, &s->iomem);
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2009-08-31 18:07:18 +04:00
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2021-12-07 01:45:27 +03:00
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/* XXX: endianness? */
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memory_region_init_io(&s->lowmem, OBJECT(dev), &vga_mem_ops, &s->vga,
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"vga-lowmem", 0x20000);
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memory_region_set_coalescing(&s->lowmem);
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sysbus_init_mmio(sbd, &s->lowmem);
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2009-08-31 18:07:18 +04:00
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s->vga.bank_offset = 0;
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2021-12-07 01:45:27 +03:00
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s->vga.global_vmstate = true;
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2022-03-17 11:30:25 +03:00
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if (!vga_common_init(&s->vga, OBJECT(dev), errp)) {
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return;
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}
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2021-12-07 01:45:27 +03:00
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sysbus_init_mmio(sbd, &s->vga.vram);
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s->vga.con = graphic_console_init(dev, 0, s->vga.hw_ops, &s->vga);
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}
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static Property vga_mmio_properties[] = {
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DEFINE_PROP_UINT8("it_shift", VGAMmioState, it_shift, 0),
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DEFINE_PROP_UINT32("vgamem_mb", VGAMmioState, vga.vram_size_mb, 8),
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DEFINE_PROP_END_OF_LIST(),
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};
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2009-08-31 18:07:18 +04:00
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2021-12-07 01:45:27 +03:00
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static void vga_mmio_class_initfn(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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2009-08-31 18:07:18 +04:00
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2021-12-07 01:45:27 +03:00
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dc->realize = vga_mmio_realizefn;
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dc->reset = vga_mmio_reset;
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dc->vmsd = &vmstate_vga_common;
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device_class_set_props(dc, vga_mmio_properties);
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set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
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}
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2019-12-09 16:30:08 +03:00
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2021-12-07 01:45:27 +03:00
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static const TypeInfo vga_mmio_info = {
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.name = TYPE_VGA_MMIO,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(VGAMmioState),
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.class_init = vga_mmio_class_initfn,
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};
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static void vga_mmio_register_types(void)
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{
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type_register_static(&vga_mmio_info);
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2009-08-31 18:07:18 +04:00
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}
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2021-12-07 01:45:27 +03:00
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type_init(vga_mmio_register_types)
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