qemu/tcg/riscv/tcg-target-con-set.h

/* SPDX-License-Identifier: MIT */
/*
 * Define RISC-V target-specific constraint sets.
 * Copyright (c) 2021 Linaro
 */

/*
 * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
 * Each operand should be a sequence of constraint letters as defined by
 * tcg-target-con-str.h; the constraint combination is inclusive or.
 */
C_O0_I1(r)
C_O0_I2(rZ, r)
C_O0_I2(rZ, rZ)
C_O1_I1(r, r)
C_O1_I2(r, r, ri)
C_O1_I2(r, r, rI)
C_O1_I2(r, r, rJ)
C_O1_I2(r, rZ, rN)
C_O1_I2(r, rZ, rZ)
C_N1_I2(r, r, rM)
C_O1_I4(r, r, rI, rM, rM)
C_O2_I4(r, r, rZ, rZ, rM, rM)
tcg/riscv: Split out constraint sets to tcg-target-con-set.h Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2020-10-17 11:08:21 -07:00			`/* SPDX-License-Identifier: MIT */`
			`/*`
			`* Define RISC-V target-specific constraint sets.`
			`* Copyright (c) 2021 Linaro`
			`*/`

			`/*`
			`* C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.`
			`* Each operand should be a sequence of constraint letters as defined by`
			`* tcg-target-con-str.h; the constraint combination is inclusive or.`
			`*/`
			`C_O0_I1(r)`
			`C_O0_I2(rZ, r)`
			`C_O0_I2(rZ, rZ)`
			`C_O1_I1(r, r)`
			`C_O1_I2(r, r, ri)`
			`C_O1_I2(r, r, rI)`
tcg/riscv: Support ANDN, ORN, XNOR from Zbb Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2023-04-25 15:47:34 +01:00			`C_O1_I2(r, r, rJ)`
tcg/riscv: Split out constraint sets to tcg-target-con-set.h Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2020-10-17 11:08:21 -07:00			`C_O1_I2(r, rZ, rN)`
			`C_O1_I2(r, rZ, rZ)`
tcg/riscv: Support CTZ, CLZ from Zbb Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2023-04-26 14:21:55 +01:00			`C_N1_I2(r, r, rM)`
tcg/riscv: Implement movcond Implement with and without Zicond. Without Zicond, we were letting the middle-end expand to a 5 insn sequence; better to use a branch over a single insn. Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2023-04-26 11:59:55 +01:00			`C_O1_I4(r, r, rI, rM, rM)`
tcg/riscv: Split out constraint sets to tcg-target-con-set.h Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2020-10-17 11:08:21 -07:00			`C_O2_I4(r, r, rZ, rZ, rM, rM)`