2021-03-15 21:45:59 +03:00
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/*
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* PowerPC emulation special registers manipulation helpers for qemu.
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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2021-03-23 21:43:32 +03:00
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#include "cpu.h"
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2021-03-15 21:45:59 +03:00
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#include "qemu/main-loop.h"
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#include "exec/exec-all.h"
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#include "sysemu/kvm.h"
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2022-11-18 06:11:26 +03:00
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#include "sysemu/tcg.h"
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2021-03-15 21:45:59 +03:00
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#include "helper_regs.h"
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2021-12-17 19:57:18 +03:00
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#include "power8-pmu.h"
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2022-02-18 10:34:15 +03:00
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#include "cpu-models.h"
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#include "spr_common.h"
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2021-03-15 21:45:59 +03:00
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/* Swap temporary saved registers with GPRs */
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void hreg_swap_gpr_tgpr(CPUPPCState *env)
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{
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target_ulong tmp;
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tmp = env->gpr[0];
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env->gpr[0] = env->tgpr[0];
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env->tgpr[0] = tmp;
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tmp = env->gpr[1];
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env->gpr[1] = env->tgpr[1];
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env->tgpr[1] = tmp;
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tmp = env->gpr[2];
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env->gpr[2] = env->tgpr[2];
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env->tgpr[2] = tmp;
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tmp = env->gpr[3];
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env->gpr[3] = env->tgpr[3];
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env->tgpr[3] = tmp;
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}
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2024-03-28 13:41:29 +03:00
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#if defined(TARGET_PPC64)
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static bool hreg_check_bhrb_enable(CPUPPCState *env)
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{
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bool pr = !!(env->msr & (1 << MSR_PR));
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target_long mmcr0;
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bool fcp;
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bool hv;
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/* ISA 3.1 adds the PMCRA[BRHBRD] and problem state checks */
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if ((env->insns_flags2 & PPC2_ISA310) &&
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((env->spr[SPR_POWER_MMCRA] & MMCRA_BHRBRD) || !pr)) {
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return false;
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}
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/* Check for BHRB "frozen" conditions */
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mmcr0 = env->spr[SPR_POWER_MMCR0];
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fcp = !!(mmcr0 & MMCR0_FCP);
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if (mmcr0 & MMCR0_FCPC) {
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hv = !!(env->msr & (1ull << MSR_HV));
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if (fcp) {
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if (hv && pr) {
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return false;
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}
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} else if (!hv && pr) {
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return false;
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}
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} else if (fcp && pr) {
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return false;
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}
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return true;
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}
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#endif
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2023-05-30 16:04:47 +03:00
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static uint32_t hreg_compute_pmu_hflags_value(CPUPPCState *env)
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{
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uint32_t hflags = 0;
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#if defined(TARGET_PPC64)
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if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMCC0) {
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hflags |= 1 << HFLAGS_PMCC0;
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}
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if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMCC1) {
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hflags |= 1 << HFLAGS_PMCC1;
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}
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if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMCjCE) {
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hflags |= 1 << HFLAGS_PMCJCE;
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}
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2024-03-28 13:41:29 +03:00
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if (hreg_check_bhrb_enable(env)) {
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hflags |= 1 << HFLAGS_BHRB_ENABLE;
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}
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2023-05-30 16:04:47 +03:00
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#ifndef CONFIG_USER_ONLY
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if (env->pmc_ins_cnt) {
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hflags |= 1 << HFLAGS_INSN_CNT;
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}
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if (env->pmc_ins_cnt & 0x1e) {
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hflags |= 1 << HFLAGS_PMC_OTHER;
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}
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#endif
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#endif
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return hflags;
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}
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/* Mask of all PMU hflags */
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static uint32_t hreg_compute_pmu_hflags_mask(CPUPPCState *env)
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{
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uint32_t hflags_mask = 0;
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#if defined(TARGET_PPC64)
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hflags_mask |= 1 << HFLAGS_PMCC0;
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hflags_mask |= 1 << HFLAGS_PMCC1;
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hflags_mask |= 1 << HFLAGS_PMCJCE;
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hflags_mask |= 1 << HFLAGS_INSN_CNT;
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hflags_mask |= 1 << HFLAGS_PMC_OTHER;
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2024-03-28 13:41:29 +03:00
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hflags_mask |= 1 << HFLAGS_BHRB_ENABLE;
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2023-05-30 16:04:47 +03:00
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#endif
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return hflags_mask;
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}
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2021-03-23 21:43:40 +03:00
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static uint32_t hreg_compute_hflags_value(CPUPPCState *env)
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2021-03-15 21:45:59 +03:00
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{
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2021-03-23 21:43:32 +03:00
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target_ulong msr = env->msr;
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uint32_t ppc_flags = env->flags;
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uint32_t hflags = 0;
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uint32_t msr_mask;
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2021-03-15 21:45:59 +03:00
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2021-03-23 21:43:32 +03:00
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/* Some bits come straight across from MSR. */
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QEMU_BUILD_BUG_ON(MSR_LE != HFLAGS_LE);
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QEMU_BUILD_BUG_ON(MSR_PR != HFLAGS_PR);
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QEMU_BUILD_BUG_ON(MSR_DR != HFLAGS_DR);
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QEMU_BUILD_BUG_ON(MSR_FP != HFLAGS_FP);
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msr_mask = ((1 << MSR_LE) | (1 << MSR_PR) |
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2021-03-23 21:43:38 +03:00
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(1 << MSR_DR) | (1 << MSR_FP));
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2021-03-15 21:46:00 +03:00
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2021-03-23 21:43:34 +03:00
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if (ppc_flags & POWERPC_FLAG_DE) {
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target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0];
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2022-05-05 00:05:39 +03:00
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if ((dbcr0 & DBCR0_ICMP) && FIELD_EX64(env->msr, MSR, DE)) {
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2021-03-23 21:43:34 +03:00
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hflags |= 1 << HFLAGS_SE;
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}
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2022-05-05 00:05:39 +03:00
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if ((dbcr0 & DBCR0_BRT) && FIELD_EX64(env->msr, MSR, DE)) {
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2021-03-23 21:43:34 +03:00
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hflags |= 1 << HFLAGS_BE;
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}
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} else {
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if (ppc_flags & POWERPC_FLAG_BE) {
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QEMU_BUILD_BUG_ON(MSR_BE != HFLAGS_BE);
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msr_mask |= 1 << MSR_BE;
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}
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if (ppc_flags & POWERPC_FLAG_SE) {
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QEMU_BUILD_BUG_ON(MSR_SE != HFLAGS_SE);
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msr_mask |= 1 << MSR_SE;
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}
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2021-03-23 21:43:32 +03:00
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}
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if (msr_is_64bit(env, msr)) {
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hflags |= 1 << HFLAGS_64;
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}
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if ((ppc_flags & POWERPC_FLAG_SPE) && (msr & (1 << MSR_SPE))) {
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hflags |= 1 << HFLAGS_SPE;
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}
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if (ppc_flags & POWERPC_FLAG_VRE) {
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QEMU_BUILD_BUG_ON(MSR_VR != HFLAGS_VR);
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msr_mask |= 1 << MSR_VR;
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2021-03-15 21:46:00 +03:00
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}
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2021-03-23 21:43:37 +03:00
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if (ppc_flags & POWERPC_FLAG_VSX) {
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QEMU_BUILD_BUG_ON(MSR_VSX != HFLAGS_VSX);
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msr_mask |= 1 << MSR_VSX;
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2021-03-23 21:43:32 +03:00
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}
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if ((ppc_flags & POWERPC_FLAG_TM) && (msr & (1ull << MSR_TM))) {
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hflags |= 1 << HFLAGS_TM;
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}
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2021-03-23 21:43:36 +03:00
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if (env->spr[SPR_LPCR] & LPCR_GTSE) {
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hflags |= 1 << HFLAGS_GTSE;
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}
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2021-09-17 14:47:50 +03:00
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if (env->spr[SPR_LPCR] & LPCR_HR) {
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hflags |= 1 << HFLAGS_HR;
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}
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2021-03-23 21:43:32 +03:00
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#ifndef CONFIG_USER_ONLY
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if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) {
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hflags |= 1 << HFLAGS_HV;
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}
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2021-03-23 21:43:38 +03:00
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/*
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* This is our encoding for server processors. The architecture
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* specifies that there is no such thing as userspace with
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* translation off, however it appears that MacOS does it and some
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* 32-bit CPUs support it. Weird...
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*
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* 0 = Guest User space virtual mode
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* 1 = Guest Kernel space virtual mode
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* 2 = Guest User space real mode
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* 3 = Guest Kernel space real mode
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* 4 = HV User space virtual mode
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* 5 = HV Kernel space virtual mode
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* 6 = HV User space real mode
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* 7 = HV Kernel space real mode
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*
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* For BookE, we need 8 MMU modes as follow:
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*
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* 0 = AS 0 HV User space
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* 1 = AS 0 HV Kernel space
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* 2 = AS 1 HV User space
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* 3 = AS 1 HV Kernel space
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* 4 = AS 0 Guest User space
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* 5 = AS 0 Guest Kernel space
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* 6 = AS 1 Guest User space
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* 7 = AS 1 Guest Kernel space
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*/
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unsigned immu_idx, dmmu_idx;
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dmmu_idx = msr & (1 << MSR_PR) ? 0 : 1;
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2022-01-28 15:15:03 +03:00
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if (env->mmu_model == POWERPC_MMU_BOOKE ||
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env->mmu_model == POWERPC_MMU_BOOKE206) {
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2021-03-23 21:43:38 +03:00
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dmmu_idx |= msr & (1 << MSR_GS) ? 4 : 0;
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immu_idx = dmmu_idx;
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immu_idx |= msr & (1 << MSR_IS) ? 2 : 0;
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dmmu_idx |= msr & (1 << MSR_DS) ? 2 : 0;
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} else {
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dmmu_idx |= msr & (1ull << MSR_HV) ? 4 : 0;
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immu_idx = dmmu_idx;
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immu_idx |= msr & (1 << MSR_IR) ? 0 : 2;
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dmmu_idx |= msr & (1 << MSR_DR) ? 0 : 2;
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}
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hflags |= immu_idx << HFLAGS_IMMU_IDX;
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hflags |= dmmu_idx << HFLAGS_DMMU_IDX;
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2021-03-23 21:43:32 +03:00
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#endif
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2023-05-30 16:04:47 +03:00
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hflags |= hreg_compute_pmu_hflags_value(env);
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2021-03-23 21:43:40 +03:00
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return hflags | (msr & msr_mask);
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}
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void hreg_compute_hflags(CPUPPCState *env)
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{
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env->hflags = hreg_compute_hflags_value(env);
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}
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2023-05-30 16:04:47 +03:00
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/*
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* This can be used as a lighter-weight alternative to hreg_compute_hflags
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* when PMU MMCR0 or pmc_ins_cnt changes. pmc_ins_cnt is changed by
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* pmu_update_summaries.
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*/
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void hreg_update_pmu_hflags(CPUPPCState *env)
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{
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env->hflags &= ~hreg_compute_pmu_hflags_mask(env);
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env->hflags |= hreg_compute_pmu_hflags_value(env);
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}
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2021-03-23 21:43:40 +03:00
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#ifdef CONFIG_DEBUG_TCG
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2023-06-21 16:56:24 +03:00
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void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc,
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uint64_t *cs_base, uint32_t *flags)
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2021-03-23 21:43:40 +03:00
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{
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uint32_t hflags_current = env->hflags;
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uint32_t hflags_rebuilt;
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*pc = env->nip;
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*cs_base = 0;
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*flags = hflags_current;
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hflags_rebuilt = hreg_compute_hflags_value(env);
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if (unlikely(hflags_current != hflags_rebuilt)) {
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cpu_abort(env_cpu(env),
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"TCG hflags mismatch (current:0x%08x rebuilt:0x%08x)\n",
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hflags_current, hflags_rebuilt);
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}
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2021-03-15 21:45:59 +03:00
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}
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2021-03-23 21:43:40 +03:00
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#endif
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2021-03-15 21:45:59 +03:00
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void cpu_interrupt_exittb(CPUState *cs)
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{
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2022-01-28 15:15:02 +03:00
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/*
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* We don't need to worry about translation blocks
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2022-11-18 06:11:26 +03:00
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* unless running with TCG.
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2022-01-28 15:15:02 +03:00
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*/
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2022-11-18 06:11:26 +03:00
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if (tcg_enabled()) {
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2024-01-02 18:35:26 +03:00
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BQL_LOCK_GUARD();
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2021-03-15 21:45:59 +03:00
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cpu_interrupt(cs, CPU_INTERRUPT_EXITTB);
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}
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}
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int hreg_store_msr(CPUPPCState *env, target_ulong value, int alter_hv)
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{
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int excp;
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#if !defined(CONFIG_USER_ONLY)
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CPUState *cs = env_cpu(env);
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#endif
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excp = 0;
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value &= env->msr_mask;
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#if !defined(CONFIG_USER_ONLY)
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/* Neither mtmsr nor guest state can alter HV */
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if (!alter_hv || !(env->msr & MSR_HVB)) {
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value &= ~MSR_HVB;
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value |= env->msr & MSR_HVB;
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}
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2023-06-13 17:16:23 +03:00
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/* Attempt to modify MSR[ME] in guest state is ignored */
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if (is_book3s_arch2x(env) && !(env->msr & MSR_HVB)) {
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value &= ~(1 << MSR_ME);
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value |= env->msr & (1 << MSR_ME);
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}
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2022-05-05 00:05:34 +03:00
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|
|
if ((value ^ env->msr) & (R_MSR_IR_MASK | R_MSR_DR_MASK)) {
|
2021-03-15 21:45:59 +03:00
|
|
|
cpu_interrupt_exittb(cs);
|
|
|
|
}
|
2022-01-28 15:15:03 +03:00
|
|
|
if ((env->mmu_model == POWERPC_MMU_BOOKE ||
|
|
|
|
env->mmu_model == POWERPC_MMU_BOOKE206) &&
|
2022-05-05 00:05:30 +03:00
|
|
|
((value ^ env->msr) & R_MSR_GS_MASK)) {
|
2021-03-15 21:45:59 +03:00
|
|
|
cpu_interrupt_exittb(cs);
|
|
|
|
}
|
|
|
|
if (unlikely((env->flags & POWERPC_FLAG_TGPR) &&
|
|
|
|
((value ^ env->msr) & (1 << MSR_TGPR)))) {
|
|
|
|
/* Swap temporary saved registers with GPRs */
|
|
|
|
hreg_swap_gpr_tgpr(env);
|
|
|
|
}
|
2022-05-05 00:05:35 +03:00
|
|
|
if (unlikely((value ^ env->msr) & R_MSR_EP_MASK)) {
|
|
|
|
env->excp_prefix = FIELD_EX64(value, MSR, EP) * 0xFFF00000;
|
2021-03-15 21:45:59 +03:00
|
|
|
}
|
|
|
|
/*
|
|
|
|
* If PR=1 then EE, IR and DR must be 1
|
|
|
|
*
|
|
|
|
* Note: We only enforce this on 64-bit server processors.
|
|
|
|
* It appears that:
|
|
|
|
* - 32-bit implementations supports PR=1 and EE/DR/IR=0 and MacOS
|
|
|
|
* exploits it.
|
|
|
|
* - 64-bit embedded implementations do not need any operation to be
|
|
|
|
* performed when PR is set.
|
|
|
|
*/
|
|
|
|
if (is_book3s_arch2x(env) && ((value >> MSR_PR) & 1)) {
|
|
|
|
value |= (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
env->msr = value;
|
|
|
|
hreg_compute_hflags(env);
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
2022-10-21 17:21:54 +03:00
|
|
|
ppc_maybe_interrupt(env);
|
|
|
|
|
2022-05-05 00:05:28 +03:00
|
|
|
if (unlikely(FIELD_EX64(env->msr, MSR, POW))) {
|
2021-03-15 21:45:59 +03:00
|
|
|
if (!env->pending_interrupts && (*env->check_pow)(env)) {
|
|
|
|
cs->halted = 1;
|
|
|
|
excp = EXCP_HALTED;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
return excp;
|
|
|
|
}
|
|
|
|
|
2023-06-13 16:33:42 +03:00
|
|
|
#ifndef CONFIG_USER_ONLY
|
2021-07-23 20:56:27 +03:00
|
|
|
void store_40x_sler(CPUPPCState *env, uint32_t val)
|
|
|
|
{
|
|
|
|
/* XXX: TO BE FIXED */
|
|
|
|
if (val != 0x00000000) {
|
|
|
|
cpu_abort(env_cpu(env),
|
|
|
|
"Little-endian regions are not supported by now\n");
|
|
|
|
}
|
|
|
|
env->spr[SPR_405_SLER] = val;
|
|
|
|
}
|
|
|
|
|
2021-03-15 21:45:59 +03:00
|
|
|
void check_tlb_flush(CPUPPCState *env, bool global)
|
|
|
|
{
|
|
|
|
CPUState *cs = env_cpu(env);
|
|
|
|
|
|
|
|
/* Handle global flushes first */
|
|
|
|
if (global && (env->tlb_need_flush & TLB_NEED_GLOBAL_FLUSH)) {
|
|
|
|
env->tlb_need_flush &= ~TLB_NEED_GLOBAL_FLUSH;
|
|
|
|
env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH;
|
2024-03-26 16:20:43 +03:00
|
|
|
tlb_flush_all_cpus_synced(cs);
|
2021-03-15 21:45:59 +03:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Then handle local ones */
|
|
|
|
if (env->tlb_need_flush & TLB_NEED_LOCAL_FLUSH) {
|
|
|
|
env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH;
|
|
|
|
tlb_flush(cs);
|
|
|
|
}
|
|
|
|
}
|
2023-06-13 16:33:42 +03:00
|
|
|
#endif /* !CONFIG_USER_ONLY */
|
2022-02-18 10:34:15 +03:00
|
|
|
|
|
|
|
/**
|
|
|
|
* _spr_register
|
|
|
|
*
|
|
|
|
* Register an SPR with all the callbacks required for tcg,
|
|
|
|
* and the ID number for KVM.
|
|
|
|
*
|
|
|
|
* The reason for the conditional compilation is that the tcg functions
|
|
|
|
* may be compiled out, and the system kvm header may not be available
|
|
|
|
* for supplying the ID numbers. This is ugly, but the best we can do.
|
|
|
|
*/
|
|
|
|
void _spr_register(CPUPPCState *env, int num, const char *name,
|
|
|
|
USR_ARG(spr_callback *uea_read)
|
|
|
|
USR_ARG(spr_callback *uea_write)
|
|
|
|
SYS_ARG(spr_callback *oea_read)
|
|
|
|
SYS_ARG(spr_callback *oea_write)
|
|
|
|
SYS_ARG(spr_callback *hea_read)
|
|
|
|
SYS_ARG(spr_callback *hea_write)
|
|
|
|
KVM_ARG(uint64_t one_reg_id)
|
|
|
|
target_ulong initial_value)
|
|
|
|
{
|
|
|
|
ppc_spr_t *spr = &env->spr_cb[num];
|
|
|
|
|
|
|
|
/* No SPR should be registered twice. */
|
|
|
|
assert(spr->name == NULL);
|
|
|
|
assert(name != NULL);
|
|
|
|
|
|
|
|
spr->name = name;
|
|
|
|
spr->default_value = initial_value;
|
|
|
|
env->spr[num] = initial_value;
|
|
|
|
|
|
|
|
#ifdef CONFIG_TCG
|
|
|
|
spr->uea_read = uea_read;
|
|
|
|
spr->uea_write = uea_write;
|
|
|
|
# ifndef CONFIG_USER_ONLY
|
|
|
|
spr->oea_read = oea_read;
|
|
|
|
spr->oea_write = oea_write;
|
|
|
|
spr->hea_read = hea_read;
|
|
|
|
spr->hea_write = hea_write;
|
|
|
|
# endif
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_KVM
|
|
|
|
spr->one_reg_id = one_reg_id;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Generic PowerPC SPRs */
|
|
|
|
void register_generic_sprs(PowerPCCPU *cpu)
|
|
|
|
{
|
|
|
|
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
|
|
|
|
CPUPPCState *env = &cpu->env;
|
|
|
|
|
|
|
|
/* Integer processing */
|
|
|
|
spr_register(env, SPR_XER, "XER",
|
|
|
|
&spr_read_xer, &spr_write_xer,
|
|
|
|
&spr_read_xer, &spr_write_xer,
|
|
|
|
0x00000000);
|
|
|
|
/* Branch control */
|
|
|
|
spr_register(env, SPR_LR, "LR",
|
|
|
|
&spr_read_lr, &spr_write_lr,
|
|
|
|
&spr_read_lr, &spr_write_lr,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_CTR, "CTR",
|
|
|
|
&spr_read_ctr, &spr_write_ctr,
|
|
|
|
&spr_read_ctr, &spr_write_ctr,
|
|
|
|
0x00000000);
|
|
|
|
/* Interrupt processing */
|
|
|
|
spr_register(env, SPR_SRR0, "SRR0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_SRR1, "SRR1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
/* Processor control */
|
|
|
|
spr_register(env, SPR_SPRG0, "SPRG0",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_SPRG1, "SPRG1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_SPRG2, "SPRG2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_SPRG3, "SPRG3",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
|
|
|
|
spr_register(env, SPR_PVR, "PVR",
|
|
|
|
/* Linux permits userspace to read PVR */
|
|
|
|
#if defined(CONFIG_LINUX_USER)
|
|
|
|
&spr_read_generic,
|
|
|
|
#else
|
|
|
|
SPR_NOACCESS,
|
|
|
|
#endif
|
|
|
|
SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
|
|
|
pcc->pvr);
|
|
|
|
|
|
|
|
/* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
|
|
|
|
if (pcc->svr != POWERPC_SVR_NONE) {
|
|
|
|
if (pcc->svr & POWERPC_SVR_E500) {
|
|
|
|
spr_register(env, SPR_E500_SVR, "SVR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
|
|
|
pcc->svr & ~POWERPC_SVR_E500);
|
|
|
|
} else {
|
|
|
|
spr_register(env, SPR_SVR, "SVR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
|
|
|
pcc->svr);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Time base */
|
2023-11-22 10:08:45 +03:00
|
|
|
#if defined(TARGET_PPC64)
|
2023-09-13 07:24:08 +03:00
|
|
|
spr_register(env, SPR_TBL, "TB",
|
2023-11-22 10:08:45 +03:00
|
|
|
#else
|
2023-09-13 07:24:08 +03:00
|
|
|
spr_register(env, SPR_TBL, "TBL",
|
2023-11-22 10:08:45 +03:00
|
|
|
#endif
|
2022-02-18 10:34:15 +03:00
|
|
|
&spr_read_tbl, SPR_NOACCESS,
|
|
|
|
&spr_read_tbl, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
2023-09-13 07:24:08 +03:00
|
|
|
spr_register(env, SPR_TBU, "TBU",
|
2022-02-18 10:34:15 +03:00
|
|
|
&spr_read_tbu, SPR_NOACCESS,
|
|
|
|
&spr_read_tbu, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
2023-07-29 07:31:36 +03:00
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
|
|
if (env->has_hv_mode) {
|
|
|
|
spr_register_hv(env, SPR_WR_TBL, "TBL",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, &spr_write_tbl,
|
|
|
|
0x00000000);
|
|
|
|
spr_register_hv(env, SPR_WR_TBU, "TBU",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, &spr_write_tbu,
|
|
|
|
0x00000000);
|
|
|
|
} else {
|
|
|
|
spr_register(env, SPR_WR_TBL, "TBL",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, &spr_write_tbl,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_WR_TBU, "TBU",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, &spr_write_tbu,
|
|
|
|
0x00000000);
|
|
|
|
}
|
|
|
|
#endif
|
2022-02-18 10:34:15 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
void register_non_embedded_sprs(CPUPPCState *env)
|
|
|
|
{
|
|
|
|
/* Exception processing */
|
|
|
|
spr_register_kvm(env, SPR_DSISR, "DSISR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
target/ppc: Fix width of some 32-bit SPRs
Some 32-bit SPRs are incorrectly implemented as 64-bits on 64-bit
targets.
This changes VRSAVE, DSISR, HDSISR, DAWRX0, PIDR, LPIDR, DEXCR,
HDEXCR, CTRL, TSCR, MMCRH, and PMC[1-6] from to be 32-bit registers.
This only goes by the 32/64 classification in the architecture, it
does not try to implement finer details of SPR implementation (e.g.,
not all bits implemented as simple read/write storage).
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Message-Id: <20230515092655.171206-2-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-05-15 12:26:47 +03:00
|
|
|
&spr_read_generic, &spr_write_generic32,
|
2022-02-18 10:34:15 +03:00
|
|
|
KVM_REG_PPC_DSISR, 0x00000000);
|
|
|
|
spr_register_kvm(env, SPR_DAR, "DAR",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
KVM_REG_PPC_DAR, 0x00000000);
|
|
|
|
/* Timer */
|
2023-09-13 06:37:57 +03:00
|
|
|
spr_register(env, SPR_DECR, "DEC",
|
2022-02-18 10:34:15 +03:00
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_decr, &spr_write_decr,
|
|
|
|
0x00000000);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Storage Description Register 1 */
|
|
|
|
void register_sdr1_sprs(CPUPPCState *env)
|
|
|
|
{
|
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
|
|
if (env->has_hv_mode) {
|
|
|
|
/*
|
|
|
|
* SDR1 is a hypervisor resource on CPUs which have a
|
|
|
|
* hypervisor mode
|
|
|
|
*/
|
|
|
|
spr_register_hv(env, SPR_SDR1, "SDR1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_sdr1,
|
|
|
|
0x00000000);
|
|
|
|
} else {
|
|
|
|
spr_register(env, SPR_SDR1, "SDR1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_sdr1,
|
|
|
|
0x00000000);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
/* BATs 0-3 */
|
|
|
|
void register_low_BATs(CPUPPCState *env)
|
|
|
|
{
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
spr_register(env, SPR_IBAT0U, "IBAT0U",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_ibat, &spr_write_ibatu,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_IBAT0L, "IBAT0L",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_ibat, &spr_write_ibatl,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_IBAT1U, "IBAT1U",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_ibat, &spr_write_ibatu,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_IBAT1L, "IBAT1L",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_ibat, &spr_write_ibatl,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_IBAT2U, "IBAT2U",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_ibat, &spr_write_ibatu,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_IBAT2L, "IBAT2L",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_ibat, &spr_write_ibatl,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_IBAT3U, "IBAT3U",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_ibat, &spr_write_ibatu,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_IBAT3L, "IBAT3L",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_ibat, &spr_write_ibatl,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_DBAT0U, "DBAT0U",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_dbat, &spr_write_dbatu,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_DBAT0L, "DBAT0L",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_dbat, &spr_write_dbatl,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_DBAT1U, "DBAT1U",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_dbat, &spr_write_dbatu,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_DBAT1L, "DBAT1L",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_dbat, &spr_write_dbatl,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_DBAT2U, "DBAT2U",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_dbat, &spr_write_dbatu,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_DBAT2L, "DBAT2L",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_dbat, &spr_write_dbatl,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_DBAT3U, "DBAT3U",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_dbat, &spr_write_dbatu,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_DBAT3L, "DBAT3L",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_dbat, &spr_write_dbatl,
|
|
|
|
0x00000000);
|
|
|
|
env->nb_BATs += 4;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
/* BATs 4-7 */
|
|
|
|
void register_high_BATs(CPUPPCState *env)
|
|
|
|
{
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
spr_register(env, SPR_IBAT4U, "IBAT4U",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_ibat_h, &spr_write_ibatu_h,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_IBAT4L, "IBAT4L",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_ibat_h, &spr_write_ibatl_h,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_IBAT5U, "IBAT5U",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_ibat_h, &spr_write_ibatu_h,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_IBAT5L, "IBAT5L",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_ibat_h, &spr_write_ibatl_h,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_IBAT6U, "IBAT6U",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_ibat_h, &spr_write_ibatu_h,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_IBAT6L, "IBAT6L",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_ibat_h, &spr_write_ibatl_h,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_IBAT7U, "IBAT7U",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_ibat_h, &spr_write_ibatu_h,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_IBAT7L, "IBAT7L",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_ibat_h, &spr_write_ibatl_h,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_DBAT4U, "DBAT4U",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_dbat_h, &spr_write_dbatu_h,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_DBAT4L, "DBAT4L",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_dbat_h, &spr_write_dbatl_h,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_DBAT5U, "DBAT5U",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_dbat_h, &spr_write_dbatu_h,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_DBAT5L, "DBAT5L",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_dbat_h, &spr_write_dbatl_h,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_DBAT6U, "DBAT6U",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_dbat_h, &spr_write_dbatu_h,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_DBAT6L, "DBAT6L",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_dbat_h, &spr_write_dbatl_h,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_DBAT7U, "DBAT7U",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_dbat_h, &spr_write_dbatu_h,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_DBAT7L, "DBAT7L",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_dbat_h, &spr_write_dbatl_h,
|
|
|
|
0x00000000);
|
|
|
|
env->nb_BATs += 4;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Softare table search registers */
|
|
|
|
void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
|
|
|
|
{
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
env->nb_tlb = nb_tlbs;
|
|
|
|
env->nb_ways = nb_ways;
|
|
|
|
env->tlb_type = TLB_6XX;
|
|
|
|
spr_register(env, SPR_DMISS, "DMISS",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_DCMP, "DCMP",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_HASH1, "HASH1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_HASH2, "HASH2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_IMISS, "IMISS",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_ICMP, "ICMP",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_RPA, "RPA",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_generic, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
void register_thrm_sprs(CPUPPCState *env)
|
|
|
|
{
|
|
|
|
/* Thermal management */
|
|
|
|
spr_register(env, SPR_THRM1, "THRM1",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_thrm, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
|
|
|
|
spr_register(env, SPR_THRM2, "THRM2",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_thrm, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
|
|
|
|
spr_register(env, SPR_THRM3, "THRM3",
|
|
|
|
SPR_NOACCESS, SPR_NOACCESS,
|
|
|
|
&spr_read_thrm, &spr_write_generic,
|
|
|
|
0x00000000);
|
|
|
|
}
|
|
|
|
|
|
|
|
void register_usprgh_sprs(CPUPPCState *env)
|
|
|
|
{
|
|
|
|
spr_register(env, SPR_USPRG4, "USPRG4",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_USPRG5, "USPRG5",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_USPRG6, "USPRG6",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
spr_register(env, SPR_USPRG7, "USPRG7",
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
&spr_read_ureg, SPR_NOACCESS,
|
|
|
|
0x00000000);
|
|
|
|
}
|