2021-05-17 18:16:58 +03:00
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# See docs/devel/tracing.rst for syntax documentation.
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2016-06-16 11:40:17 +03:00
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2019-03-14 21:09:26 +03:00
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# virt-acpi-build.c
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2016-06-16 11:40:17 +03:00
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virt_acpi_setup(void) "No fw cfg or ACPI disabled. Bailing out."
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2018-05-04 20:05:51 +03:00
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2019-03-14 21:09:26 +03:00
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# smmu-common.c
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2018-05-04 20:05:51 +03:00
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smmu_add_mr(const char *name) "%s"
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2023-05-25 12:37:49 +03:00
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smmu_ptw_level(int stage, int level, uint64_t iova, size_t subpage_size, uint64_t baseaddr, uint32_t offset, uint64_t pte) "stage=%d level=%d iova=0x%"PRIx64" subpage_sz=0x%zx baseaddr=0x%"PRIx64" offset=%d => pte=0x%"PRIx64
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2018-05-04 20:05:51 +03:00
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smmu_ptw_invalid_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, uint32_t offset, uint64_t pte) "stage=%d level=%d base@=0x%"PRIx64" pte@=0x%"PRIx64" offset=%d pte=0x%"PRIx64
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smmu_ptw_page_pte(int stage, int level, uint64_t iova, uint64_t baseaddr, uint64_t pteaddr, uint64_t pte, uint64_t address) "stage=%d level=%d iova=0x%"PRIx64" base@=0x%"PRIx64" pte@=0x%"PRIx64" pte=0x%"PRIx64" page address = 0x%"PRIx64
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smmu_ptw_block_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, uint64_t pte, uint64_t iova, uint64_t gpa, int bsize_mb) "stage=%d level=%d base@=0x%"PRIx64" pte@=0x%"PRIx64" pte=0x%"PRIx64" iova=0x%"PRIx64" block address = 0x%"PRIx64" block size = %d MiB"
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smmu_get_pte(uint64_t baseaddr, int index, uint64_t pteaddr, uint64_t pte) "baseaddr=0x%"PRIx64" index=0x%x, pteaddr=0x%"PRIx64", pte=0x%"PRIx64
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2018-06-26 19:50:42 +03:00
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smmu_iotlb_inv_all(void) "IOTLB invalidate all"
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smmu_iotlb_inv_asid(uint16_t asid) "IOTLB invalidate asid=%d"
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2023-05-25 12:37:51 +03:00
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smmu_iotlb_inv_vmid(uint16_t vmid) "IOTLB invalidate vmid=%d"
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2018-06-26 19:50:42 +03:00
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smmu_iotlb_inv_iova(uint16_t asid, uint64_t addr) "IOTLB invalidate asid=%d addr=0x%"PRIx64
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2018-06-26 19:50:42 +03:00
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smmu_inv_notifiers_mr(const char *name) "iommu mr=%s"
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2023-05-25 12:37:50 +03:00
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smmu_iotlb_lookup_hit(uint16_t asid, uint16_t vmid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=%d vmid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"
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smmu_iotlb_lookup_miss(uint16_t asid, uint16_t vmid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache MISS asid=%d vmid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"
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smmu_iotlb_insert(uint16_t asid, uint16_t vmid, uint64_t addr, uint8_t tg, uint8_t level) "IOTLB ++ asid=%d vmid=%d addr=0x%"PRIx64" tg=%d level=%d"
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2018-05-04 20:05:51 +03:00
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2019-03-14 21:09:26 +03:00
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# smmuv3.c
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2018-05-04 20:05:51 +03:00
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smmuv3_read_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r) "addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)"
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2018-05-04 20:05:51 +03:00
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smmuv3_trigger_irq(int irq) "irq=%d"
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smmuv3_write_gerror(uint32_t toggled, uint32_t gerror) "toggled=0x%x, new GERROR=0x%x"
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smmuv3_write_gerrorn(uint32_t acked, uint32_t gerrorn) "acked=0x%x, new GERRORN=0x%x"
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2018-05-04 20:05:51 +03:00
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smmuv3_unhandled_cmd(uint32_t type) "Unhandled command type=%d"
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smmuv3_cmdq_consume(uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap) "prod=%d cons=%d prod.wrap=%d cons.wrap=%d"
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smmuv3_cmdq_opcode(const char *opcode) "<--- %s"
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smmuv3_cmdq_consume_out(uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap) "prod:%d, cons:%d, prod_wrap:%d, cons_wrap:%d "
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smmuv3_cmdq_consume_error(const char *cmd_name, uint8_t cmd_error) "Error on %s command execution: %d"
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2018-05-04 20:05:51 +03:00
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smmuv3_write_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r) "addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)"
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2021-03-09 13:27:42 +03:00
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smmuv3_record_event(const char *type, uint32_t sid) "%s sid=0x%x"
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smmuv3_find_ste(uint16_t sid, uint32_t features, uint16_t sid_split) "sid=0x%x features:0x%x, sid_split:0x%x"
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2018-05-04 20:05:51 +03:00
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smmuv3_find_ste_2lvl(uint64_t strtab_base, uint64_t l1ptr, int l1_ste_offset, uint64_t l2ptr, int l2_ste_offset, int max_l2_ste) "strtab_base:0x%"PRIx64" l1ptr:0x%"PRIx64" l1_off:0x%x, l2ptr:0x%"PRIx64" l2_off:0x%x max_l2_ste:%d"
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smmuv3_get_ste(uint64_t addr) "STE addr: 0x%"PRIx64
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2021-03-09 13:27:42 +03:00
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smmuv3_translate_disable(const char *n, uint16_t sid, uint64_t addr, bool is_write) "%s sid=0x%x bypass (smmu disabled) iova:0x%"PRIx64" is_write=%d"
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smmuv3_translate_bypass(const char *n, uint16_t sid, uint64_t addr, bool is_write) "%s sid=0x%x STE bypass iova:0x%"PRIx64" is_write=%d"
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smmuv3_translate_abort(const char *n, uint16_t sid, uint64_t addr, bool is_write) "%s sid=0x%x abort on iova:0x%"PRIx64" is_write=%d"
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smmuv3_translate_success(const char *n, uint16_t sid, uint64_t iova, uint64_t translated, int perm) "%s sid=0x%x iova=0x%"PRIx64" translated=0x%"PRIx64" perm=0x%x"
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2018-05-04 20:05:51 +03:00
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smmuv3_get_cd(uint64_t addr) "CD addr: 0x%"PRIx64
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smmuv3_decode_cd(uint32_t oas) "oas=%d"
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2020-07-28 18:08:14 +03:00
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smmuv3_decode_cd_tt(int i, uint32_t tsz, uint64_t ttb, uint32_t granule_sz, bool had) "TT[%d]:tsz:%d ttb:0x%"PRIx64" granule_sz:%d had:%d"
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2021-03-09 13:27:42 +03:00
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smmuv3_cmdq_cfgi_ste(int streamid) "streamid= 0x%x"
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2020-10-14 22:33:55 +03:00
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smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=0x%x - end=0x%x"
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2021-03-09 13:27:42 +03:00
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smmuv3_cmdq_cfgi_cd(uint32_t sid) "sid=0x%x"
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smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache HIT for sid=0x%x (hits=%d, misses=%d, hit rate=%d)"
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smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache MISS for sid=0x%x (hits=%d, misses=%d, hit rate=%d)"
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2023-05-25 12:37:51 +03:00
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smmuv3_range_inval(int vmid, int asid, uint64_t addr, uint8_t tg, uint64_t num_pages, uint8_t ttl, bool leaf) "vmid=%d asid=%d addr=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64" ttl=%d leaf=%d"
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2018-06-26 19:50:42 +03:00
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smmuv3_cmdq_tlbi_nh(void) ""
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smmuv3_cmdq_tlbi_nh_asid(uint16_t asid) "asid=%d"
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2023-05-25 12:37:51 +03:00
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smmuv3_cmdq_tlbi_s12_vmid(uint16_t vmid) "vmid=%d"
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2021-03-09 13:27:42 +03:00
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smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid=0x%x"
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2018-06-26 19:50:42 +03:00
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smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu mr=%s"
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smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu mr=%s"
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2023-05-25 12:37:51 +03:00
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smmuv3_inv_notifiers_iova(const char *name, uint16_t asid, uint16_t vmid, uint64_t iova, uint8_t tg, uint64_t num_pages) "iommu mr=%s asid=%d vmid=%d iova=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64
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2018-06-26 19:50:42 +03:00
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2024-01-29 19:09:36 +03:00
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# strongarm.c
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strongarm_uart_update_parameters(const char *label, int speed, char parity, int data_bits, int stop_bits) "%s speed=%d parity=%c data=%d stop=%d"
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strongarm_ssp_read_underrun(void) "SSP rx underrun"
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2024-01-29 19:09:37 +03:00
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# z2.c
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z2_lcd_reg_update(uint8_t cur, uint8_t i_0, uint8_t i_1, uint8_t i_2, uint32_t value) "cur_reg = 0x%x, buf = [0x%x, 0x%x, 0x%x], value = 0x%x"
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z2_lcd_enable_disable_result(const char *result) "LCD %s"
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z2_aer915_send_too_long(int8_t msg) "message too long (%i bytes)"
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z2_aer915_send(uint8_t reg, uint8_t value) "reg %d value 0x%02x"
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z2_aer915_event(int8_t event, int8_t len) "i2c event =0x%x len=%d bytes"
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2024-01-29 19:09:38 +03:00
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# xen_arm.c
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xen_create_virtio_mmio_devices(int i, int irq, uint64_t base) "Created virtio-mmio device %d: irq %d base 0x%"PRIx64
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xen_init_ram(uint64_t machine_ram_size) "Initialized xen ram with size 0x%"PRIx64
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xen_enable_tpm(uint64_t addr) "Connected tpmdev at address 0x%"PRIx64
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