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qemu/tests/tcg/xtensa/test_phys_mem.S

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tests/tcg/xtensa: add test for failed memory transactions Failed memory transactions should raise exceptions 14 (for fetch) or 15 (for load/store) with XEA2. Memory accesses that result in TLB miss followed by an attempt to load PTE from physical memory which fails should raise InstTLBMiss or LoadStoreTLBMiss with XEA2. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-08-20 06:21:50 +03:00
#include "macros.inc"
test_suite phys_mem
tests/tcg/xtensa: enable autorefill phys_mem tests for MMUv3 Autorefill tests in the phys_mem test suite are disabled for cores that have spanning TLB way, i.e. for all MMUv3 cores. Instead of disabling it invalidate TLB mappings for entries that conflict with the test. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-04-26 06:05:18 +03:00
#if XCHAL_HAVE_PTP_MMU
tests/tcg/xtensa: conditionalize MMU-related tests Make MMU-related tests conditional on the presence of MMUv2 option. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 18:19:02 +03:00
tests/tcg/xtensa: add test for failed memory transactions Failed memory transactions should raise exceptions 14 (for fetch) or 15 (for load/store) with XEA2. Memory accesses that result in TLB miss followed by an attempt to load PTE from physical memory which fails should raise InstTLBMiss or LoadStoreTLBMiss with XEA2. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-08-20 06:21:50 +03:00
.purgem test_init
.macro test_init
movi a2, 0xc0000003 /* PPN */
movi a3, 0xc0000004 /* VPN */
wdtlb a2, a3
witlb a2, a3
movi a2, 0xc0000000
wsr a2, ptevaddr
tests/tcg/xtensa: enable autorefill phys_mem tests for MMUv3 Autorefill tests in the phys_mem test suite are disabled for cores that have spanning TLB way, i.e. for all MMUv3 cores. Instead of disabling it invalidate TLB mappings for entries that conflict with the test. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-04-26 06:05:18 +03:00
#if XCHAL_HAVE_SPANNING_WAY
movi a2, 0xc0000000 | XCHAL_SPANNING_WAY
idtlb a2
iitlb a2
movi a2, 0x20000000 | XCHAL_SPANNING_WAY
idtlb a2
iitlb a2
#endif
tests/tcg/xtensa: add test for failed memory transactions Failed memory transactions should raise exceptions 14 (for fetch) or 15 (for load/store) with XEA2. Memory accesses that result in TLB miss followed by an attempt to load PTE from physical memory which fails should raise InstTLBMiss or LoadStoreTLBMiss with XEA2. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-08-20 06:21:50 +03:00
.endm
test inst_fetch_get_pte_no_phys
set_vector kernel, 2f
movi a2, 0x20000000
jx a2
2:
movi a2, 0x20000000
rsr a3, excvaddr
assert eq, a2, a3
rsr a3, epc1
assert eq, a2, a3
rsr a3, exccause
movi a2, 16
assert eq, a2, a3
test_end
test read_get_pte_no_phys
set_vector kernel, 2f
movi a2, 0x20000000
1:
l32i a3, a2, 0
test_fail
2:
movi a2, 0x20000000
rsr a3, excvaddr
assert eq, a2, a3
movi a2, 1b
rsr a3, epc1
assert eq, a2, a3
rsr a3, exccause
movi a2, 24
assert eq, a2, a3
test_end
test write_get_pte_no_phys
set_vector kernel, 2f
movi a2, 0x20000000
1:
s32i a3, a2, 0
test_fail
2:
movi a2, 0x20000000
rsr a3, excvaddr
assert eq, a2, a3
movi a2, 1b
rsr a3, epc1
assert eq, a2, a3
rsr a3, exccause
movi a2, 24
assert eq, a2, a3
test_end
tests/tcg/xtensa: conditionalize MMU-related tests Make MMU-related tests conditional on the presence of MMUv2 option. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 18:19:02 +03:00
#endif
tests/tcg/xtensa: add test for failed memory transactions Failed memory transactions should raise exceptions 14 (for fetch) or 15 (for load/store) with XEA2. Memory accesses that result in TLB miss followed by an attempt to load PTE from physical memory which fails should raise InstTLBMiss or LoadStoreTLBMiss with XEA2. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-08-20 06:21:50 +03:00
test inst_fetch_no_phys
set_vector kernel, 2f
movi a2, 0xc0000000
jx a2
2:
movi a2, 0xc0000000
rsr a3, excvaddr
assert eq, a2, a3
rsr a3, epc1
assert eq, a2, a3
rsr a3, exccause
movi a2, 14
assert eq, a2, a3
test_end
test read_no_phys
set_vector kernel, 2f
movi a2, 0xc0000000
1:
l32i a3, a2, 0
test_fail
2:
movi a2, 0xc0000000
rsr a3, excvaddr
assert eq, a2, a3
movi a2, 1b
rsr a3, epc1
assert eq, a2, a3
rsr a3, exccause
movi a2, 15
assert eq, a2, a3
test_end
test write_no_phys
set_vector kernel, 2f
movi a2, 0xc0000000
1:
s32i a3, a2, 0
test_fail
2:
movi a2, 0xc0000000
rsr a3, excvaddr
assert eq, a2, a3
movi a2, 1b
rsr a3, epc1
assert eq, a2, a3
rsr a3, exccause
movi a2, 15
assert eq, a2, a3
test_end
test_suite_end
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