2018-02-09 16:44:14 +03:00
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/*
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* QEMU paravirtual RDMA
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*
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* Copyright (C) 2018 Oracle
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* Copyright (C) 2018 Red Hat Inc
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*
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* Authors:
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* Yuval Shaia <yuval.shaia@oracle.com>
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* Marcel Apfelbaum <marcel@redhat.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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2018-03-21 18:22:07 +03:00
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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2019-05-23 17:35:07 +03:00
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#include "qemu/module.h"
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2018-03-21 18:22:07 +03:00
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_ids.h"
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#include "hw/pci/msi.h"
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#include "hw/pci/msix.h"
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#include "hw/qdev-properties.h"
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#include "cpu.h"
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2018-02-09 16:44:14 +03:00
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#include "trace.h"
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2019-03-11 13:29:09 +03:00
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#include "monitor/monitor.h"
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#include "hw/rdma/rdma.h"
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2018-02-09 16:44:14 +03:00
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#include "../rdma_rm.h"
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#include "../rdma_backend.h"
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#include "../rdma_utils.h"
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#include <infiniband/verbs.h>
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#include "pvrdma.h"
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2018-03-21 18:22:07 +03:00
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#include "standard-headers/rdma/vmw_pvrdma-abi.h"
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2019-08-12 08:23:59 +03:00
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#include "sysemu/runstate.h"
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2018-03-21 18:22:07 +03:00
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#include "standard-headers/drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h"
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2018-02-09 16:44:14 +03:00
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#include "pvrdma_qp_ops.h"
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static Property pvrdma_dev_properties[] = {
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2018-12-21 17:40:25 +03:00
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DEFINE_PROP_STRING("netdev", PVRDMADev, backend_eth_device_name),
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DEFINE_PROP_STRING("ibdev", PVRDMADev, backend_device_name),
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DEFINE_PROP_UINT8("ibport", PVRDMADev, backend_port_num, 1),
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2018-02-09 16:44:14 +03:00
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DEFINE_PROP_UINT64("dev-caps-max-mr-size", PVRDMADev, dev_attr.max_mr_size,
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MAX_MR_SIZE),
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DEFINE_PROP_INT32("dev-caps-max-qp", PVRDMADev, dev_attr.max_qp, MAX_QP),
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DEFINE_PROP_INT32("dev-caps-max-cq", PVRDMADev, dev_attr.max_cq, MAX_CQ),
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DEFINE_PROP_INT32("dev-caps-max-mr", PVRDMADev, dev_attr.max_mr, MAX_MR),
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DEFINE_PROP_INT32("dev-caps-max-pd", PVRDMADev, dev_attr.max_pd, MAX_PD),
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DEFINE_PROP_INT32("dev-caps-qp-rd-atom", PVRDMADev, dev_attr.max_qp_rd_atom,
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MAX_QP_RD_ATOM),
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DEFINE_PROP_INT32("dev-caps-max-qp-init-rd-atom", PVRDMADev,
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dev_attr.max_qp_init_rd_atom, MAX_QP_INIT_RD_ATOM),
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DEFINE_PROP_INT32("dev-caps-max-ah", PVRDMADev, dev_attr.max_ah, MAX_AH),
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2019-04-03 14:33:43 +03:00
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DEFINE_PROP_INT32("dev-caps-max-srq", PVRDMADev, dev_attr.max_srq, MAX_SRQ),
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2018-12-21 17:40:19 +03:00
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DEFINE_PROP_CHR("mad-chardev", PVRDMADev, mad_chr),
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2018-02-09 16:44:14 +03:00
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DEFINE_PROP_END_OF_LIST(),
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};
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2019-03-11 13:29:09 +03:00
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static void pvrdma_print_statistics(Monitor *mon, RdmaProvider *obj)
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{
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PVRDMADev *dev = PVRDMA_DEV(obj);
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PCIDevice *pdev = PCI_DEVICE(dev);
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monitor_printf(mon, "%s, %x.%x\n", pdev->name, PCI_SLOT(pdev->devfn),
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PCI_FUNC(pdev->devfn));
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monitor_printf(mon, "\tcommands : %" PRId64 "\n",
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dev->stats.commands);
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monitor_printf(mon, "\tregs_reads : %" PRId64 "\n",
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dev->stats.regs_reads);
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monitor_printf(mon, "\tregs_writes : %" PRId64 "\n",
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dev->stats.regs_writes);
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monitor_printf(mon, "\tuar_writes : %" PRId64 "\n",
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dev->stats.uar_writes);
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monitor_printf(mon, "\tinterrupts : %" PRId64 "\n",
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dev->stats.interrupts);
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rdma_dump_device_counters(mon, &dev->rdma_dev_res);
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}
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2018-02-09 16:44:14 +03:00
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static void free_dev_ring(PCIDevice *pci_dev, PvrdmaRing *ring,
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void *ring_state)
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{
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pvrdma_ring_free(ring);
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rdma_pci_dma_unmap(pci_dev, ring_state, TARGET_PAGE_SIZE);
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}
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static int init_dev_ring(PvrdmaRing *ring, struct pvrdma_ring **ring_state,
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const char *name, PCIDevice *pci_dev,
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dma_addr_t dir_addr, uint32_t num_pages)
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{
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uint64_t *dir, *tbl;
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int rc = 0;
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dir = rdma_pci_dma_map(pci_dev, dir_addr, TARGET_PAGE_SIZE);
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if (!dir) {
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2019-03-11 13:29:05 +03:00
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rdma_error_report("Failed to map to page directory (ring %s)", name);
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2018-02-09 16:44:14 +03:00
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rc = -ENOMEM;
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goto out;
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}
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tbl = rdma_pci_dma_map(pci_dev, dir[0], TARGET_PAGE_SIZE);
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if (!tbl) {
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2019-03-11 13:29:05 +03:00
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rdma_error_report("Failed to map to page table (ring %s)", name);
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2018-02-09 16:44:14 +03:00
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rc = -ENOMEM;
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goto out_free_dir;
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}
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*ring_state = rdma_pci_dma_map(pci_dev, tbl[0], TARGET_PAGE_SIZE);
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if (!*ring_state) {
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2019-03-11 13:29:05 +03:00
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rdma_error_report("Failed to map to ring state (ring %s)", name);
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2018-02-09 16:44:14 +03:00
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rc = -ENOMEM;
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goto out_free_tbl;
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}
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/* RX ring is the second */
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2018-03-21 17:03:16 +03:00
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(*ring_state)++;
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2018-02-09 16:44:14 +03:00
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rc = pvrdma_ring_init(ring, name, pci_dev,
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(struct pvrdma_ring *)*ring_state,
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(num_pages - 1) * TARGET_PAGE_SIZE /
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sizeof(struct pvrdma_cqne),
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sizeof(struct pvrdma_cqne),
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(dma_addr_t *)&tbl[1], (dma_addr_t)num_pages - 1);
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if (rc) {
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rc = -ENOMEM;
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goto out_free_ring_state;
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}
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goto out_free_tbl;
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out_free_ring_state:
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rdma_pci_dma_unmap(pci_dev, *ring_state, TARGET_PAGE_SIZE);
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out_free_tbl:
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rdma_pci_dma_unmap(pci_dev, tbl, TARGET_PAGE_SIZE);
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out_free_dir:
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rdma_pci_dma_unmap(pci_dev, dir, TARGET_PAGE_SIZE);
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out:
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return rc;
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}
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static void free_dsr(PVRDMADev *dev)
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{
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PCIDevice *pci_dev = PCI_DEVICE(dev);
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if (!dev->dsr_info.dsr) {
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return;
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}
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free_dev_ring(pci_dev, &dev->dsr_info.async,
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dev->dsr_info.async_ring_state);
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free_dev_ring(pci_dev, &dev->dsr_info.cq, dev->dsr_info.cq_ring_state);
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rdma_pci_dma_unmap(pci_dev, dev->dsr_info.req,
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sizeof(union pvrdma_cmd_req));
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rdma_pci_dma_unmap(pci_dev, dev->dsr_info.rsp,
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sizeof(union pvrdma_cmd_resp));
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rdma_pci_dma_unmap(pci_dev, dev->dsr_info.dsr,
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sizeof(struct pvrdma_device_shared_region));
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dev->dsr_info.dsr = NULL;
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}
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static int load_dsr(PVRDMADev *dev)
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{
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int rc = 0;
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PCIDevice *pci_dev = PCI_DEVICE(dev);
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DSRInfo *dsr_info;
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struct pvrdma_device_shared_region *dsr;
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free_dsr(dev);
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/* Map to DSR */
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dev->dsr_info.dsr = rdma_pci_dma_map(pci_dev, dev->dsr_info.dma,
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sizeof(struct pvrdma_device_shared_region));
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if (!dev->dsr_info.dsr) {
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2019-03-11 13:29:05 +03:00
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rdma_error_report("Failed to map to DSR");
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2018-02-09 16:44:14 +03:00
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rc = -ENOMEM;
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goto out;
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}
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/* Shortcuts */
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dsr_info = &dev->dsr_info;
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dsr = dsr_info->dsr;
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/* Map to command slot */
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dsr_info->req = rdma_pci_dma_map(pci_dev, dsr->cmd_slot_dma,
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sizeof(union pvrdma_cmd_req));
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if (!dsr_info->req) {
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2019-03-11 13:29:05 +03:00
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rdma_error_report("Failed to map to command slot address");
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2018-02-09 16:44:14 +03:00
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rc = -ENOMEM;
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goto out_free_dsr;
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}
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/* Map to response slot */
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dsr_info->rsp = rdma_pci_dma_map(pci_dev, dsr->resp_slot_dma,
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sizeof(union pvrdma_cmd_resp));
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if (!dsr_info->rsp) {
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2019-03-11 13:29:05 +03:00
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rdma_error_report("Failed to map to response slot address");
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2018-02-09 16:44:14 +03:00
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rc = -ENOMEM;
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goto out_free_req;
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}
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/* Map to CQ notification ring */
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rc = init_dev_ring(&dsr_info->cq, &dsr_info->cq_ring_state, "dev_cq",
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pci_dev, dsr->cq_ring_pages.pdir_dma,
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dsr->cq_ring_pages.num_pages);
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if (rc) {
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rc = -ENOMEM;
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goto out_free_rsp;
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}
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/* Map to event notification ring */
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rc = init_dev_ring(&dsr_info->async, &dsr_info->async_ring_state,
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"dev_async", pci_dev, dsr->async_ring_pages.pdir_dma,
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dsr->async_ring_pages.num_pages);
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if (rc) {
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rc = -ENOMEM;
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goto out_free_rsp;
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}
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goto out;
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out_free_rsp:
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rdma_pci_dma_unmap(pci_dev, dsr_info->rsp, sizeof(union pvrdma_cmd_resp));
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out_free_req:
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rdma_pci_dma_unmap(pci_dev, dsr_info->req, sizeof(union pvrdma_cmd_req));
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out_free_dsr:
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rdma_pci_dma_unmap(pci_dev, dsr_info->dsr,
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sizeof(struct pvrdma_device_shared_region));
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dsr_info->dsr = NULL;
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out:
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return rc;
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}
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static void init_dsr_dev_caps(PVRDMADev *dev)
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{
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struct pvrdma_device_shared_region *dsr;
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if (dev->dsr_info.dsr == NULL) {
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2019-03-11 13:29:05 +03:00
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rdma_error_report("Can't initialized DSR");
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2018-02-09 16:44:14 +03:00
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return;
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}
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dsr = dev->dsr_info.dsr;
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dsr->caps.fw_ver = PVRDMA_FW_VERSION;
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dsr->caps.mode = PVRDMA_DEVICE_MODE_ROCE;
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dsr->caps.gid_types |= PVRDMA_GID_TYPE_FLAG_ROCE_V1;
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dsr->caps.max_uar = RDMA_BAR2_UAR_SIZE;
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dsr->caps.max_mr_size = dev->dev_attr.max_mr_size;
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dsr->caps.max_qp = dev->dev_attr.max_qp;
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dsr->caps.max_qp_wr = dev->dev_attr.max_qp_wr;
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dsr->caps.max_sge = dev->dev_attr.max_sge;
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dsr->caps.max_cq = dev->dev_attr.max_cq;
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dsr->caps.max_cqe = dev->dev_attr.max_cqe;
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dsr->caps.max_mr = dev->dev_attr.max_mr;
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dsr->caps.max_pd = dev->dev_attr.max_pd;
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dsr->caps.max_ah = dev->dev_attr.max_ah;
|
2019-04-03 14:33:43 +03:00
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dsr->caps.max_srq = dev->dev_attr.max_srq;
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dsr->caps.max_srq_wr = dev->dev_attr.max_srq_wr;
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dsr->caps.max_srq_sge = dev->dev_attr.max_srq_sge;
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2018-02-09 16:44:14 +03:00
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dsr->caps.gid_tbl_len = MAX_GIDS;
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dsr->caps.sys_image_guid = 0;
|
2018-12-21 17:40:28 +03:00
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dsr->caps.node_guid = dev->node_guid;
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2018-02-09 16:44:14 +03:00
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dsr->caps.phys_port_cnt = MAX_PORTS;
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dsr->caps.max_pkeys = MAX_PKEYS;
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}
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|
2018-08-05 18:35:06 +03:00
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static void uninit_msix(PCIDevice *pdev, int used_vectors)
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{
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PVRDMADev *dev = PVRDMA_DEV(pdev);
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int i;
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for (i = 0; i < used_vectors; i++) {
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msix_vector_unuse(pdev, i);
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}
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msix_uninit(pdev, &dev->msix, &dev->msix);
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}
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|
2019-03-11 13:29:05 +03:00
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static int init_msix(PCIDevice *pdev)
|
2018-08-05 18:35:06 +03:00
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{
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PVRDMADev *dev = PVRDMA_DEV(pdev);
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int i;
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int rc;
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rc = msix_init(pdev, RDMA_MAX_INTRS, &dev->msix, RDMA_MSIX_BAR_IDX,
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RDMA_MSIX_TABLE, &dev->msix, RDMA_MSIX_BAR_IDX,
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RDMA_MSIX_PBA, 0, NULL);
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if (rc < 0) {
|
2019-03-11 13:29:05 +03:00
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rdma_error_report("Failed to initialize MSI-X");
|
2018-08-05 18:35:06 +03:00
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return rc;
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}
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for (i = 0; i < RDMA_MAX_INTRS; i++) {
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rc = msix_vector_use(PCI_DEVICE(dev), i);
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if (rc < 0) {
|
2019-03-11 13:29:05 +03:00
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|
|
rdma_error_report("Fail mark MSI-X vector %d", i);
|
2018-08-05 18:35:06 +03:00
|
|
|
uninit_msix(pdev, i);
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pvrdma_fini(PCIDevice *pdev)
|
|
|
|
{
|
|
|
|
PVRDMADev *dev = PVRDMA_DEV(pdev);
|
|
|
|
|
2019-03-11 13:29:14 +03:00
|
|
|
notifier_remove(&dev->shutdown_notifier);
|
|
|
|
|
2018-08-05 18:35:06 +03:00
|
|
|
pvrdma_qp_ops_fini();
|
|
|
|
|
2019-03-11 13:29:10 +03:00
|
|
|
rdma_backend_stop(&dev->backend_dev);
|
|
|
|
|
2018-12-21 17:40:25 +03:00
|
|
|
rdma_rm_fini(&dev->rdma_dev_res, &dev->backend_dev,
|
|
|
|
dev->backend_eth_device_name);
|
2018-08-05 18:35:06 +03:00
|
|
|
|
|
|
|
rdma_backend_fini(&dev->backend_dev);
|
|
|
|
|
|
|
|
free_dsr(dev);
|
|
|
|
|
|
|
|
if (msix_enabled(pdev)) {
|
|
|
|
uninit_msix(pdev, RDMA_MAX_INTRS);
|
|
|
|
}
|
2018-12-21 17:40:34 +03:00
|
|
|
|
2019-03-11 13:29:05 +03:00
|
|
|
rdma_info_report("Device %s %x.%x is down", pdev->name,
|
|
|
|
PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
|
2018-08-05 18:35:06 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static void pvrdma_stop(PVRDMADev *dev)
|
|
|
|
{
|
|
|
|
rdma_backend_stop(&dev->backend_dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pvrdma_start(PVRDMADev *dev)
|
|
|
|
{
|
|
|
|
rdma_backend_start(&dev->backend_dev);
|
|
|
|
}
|
|
|
|
|
2018-02-09 16:44:14 +03:00
|
|
|
static void activate_device(PVRDMADev *dev)
|
|
|
|
{
|
2018-08-05 18:35:06 +03:00
|
|
|
pvrdma_start(dev);
|
2018-02-09 16:44:14 +03:00
|
|
|
set_reg_val(dev, PVRDMA_REG_ERR, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int unquiesce_device(PVRDMADev *dev)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-12-21 17:40:20 +03:00
|
|
|
static void reset_device(PVRDMADev *dev)
|
2018-02-09 16:44:14 +03:00
|
|
|
{
|
2018-08-05 18:35:06 +03:00
|
|
|
pvrdma_stop(dev);
|
2018-02-09 16:44:14 +03:00
|
|
|
}
|
|
|
|
|
2019-03-11 13:29:05 +03:00
|
|
|
static uint64_t pvrdma_regs_read(void *opaque, hwaddr addr, unsigned size)
|
2018-02-09 16:44:14 +03:00
|
|
|
{
|
|
|
|
PVRDMADev *dev = opaque;
|
|
|
|
uint32_t val;
|
|
|
|
|
2019-03-11 13:29:08 +03:00
|
|
|
dev->stats.regs_reads++;
|
|
|
|
|
2018-02-09 16:44:14 +03:00
|
|
|
if (get_reg_val(dev, addr, &val)) {
|
2019-03-11 13:29:05 +03:00
|
|
|
rdma_error_report("Failed to read REG value from address 0x%x",
|
|
|
|
(uint32_t)addr);
|
2018-02-09 16:44:14 +03:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
trace_pvrdma_regs_read(addr, val);
|
|
|
|
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
2019-03-11 13:29:05 +03:00
|
|
|
static void pvrdma_regs_write(void *opaque, hwaddr addr, uint64_t val,
|
|
|
|
unsigned size)
|
2018-02-09 16:44:14 +03:00
|
|
|
{
|
|
|
|
PVRDMADev *dev = opaque;
|
|
|
|
|
2019-03-11 13:29:08 +03:00
|
|
|
dev->stats.regs_writes++;
|
|
|
|
|
2018-02-09 16:44:14 +03:00
|
|
|
if (set_reg_val(dev, addr, val)) {
|
2019-03-11 13:29:05 +03:00
|
|
|
rdma_error_report("Failed to set REG value, addr=0x%"PRIx64 ", val=0x%"PRIx64,
|
|
|
|
addr, val);
|
2018-02-09 16:44:14 +03:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (addr) {
|
|
|
|
case PVRDMA_REG_DSRLOW:
|
2019-03-11 13:29:05 +03:00
|
|
|
trace_pvrdma_regs_write(addr, val, "DSRLOW", "");
|
2018-02-09 16:44:14 +03:00
|
|
|
dev->dsr_info.dma = val;
|
|
|
|
break;
|
|
|
|
case PVRDMA_REG_DSRHIGH:
|
2019-03-11 13:29:05 +03:00
|
|
|
trace_pvrdma_regs_write(addr, val, "DSRHIGH", "");
|
2018-02-09 16:44:14 +03:00
|
|
|
dev->dsr_info.dma |= val << 32;
|
|
|
|
load_dsr(dev);
|
|
|
|
init_dsr_dev_caps(dev);
|
|
|
|
break;
|
|
|
|
case PVRDMA_REG_CTL:
|
|
|
|
switch (val) {
|
|
|
|
case PVRDMA_DEVICE_CTL_ACTIVATE:
|
2019-03-11 13:29:05 +03:00
|
|
|
trace_pvrdma_regs_write(addr, val, "CTL", "ACTIVATE");
|
2018-02-09 16:44:14 +03:00
|
|
|
activate_device(dev);
|
|
|
|
break;
|
|
|
|
case PVRDMA_DEVICE_CTL_UNQUIESCE:
|
2019-03-11 13:29:05 +03:00
|
|
|
trace_pvrdma_regs_write(addr, val, "CTL", "UNQUIESCE");
|
2018-02-09 16:44:14 +03:00
|
|
|
unquiesce_device(dev);
|
|
|
|
break;
|
|
|
|
case PVRDMA_DEVICE_CTL_RESET:
|
2019-03-11 13:29:05 +03:00
|
|
|
trace_pvrdma_regs_write(addr, val, "CTL", "URESET");
|
2018-02-09 16:44:14 +03:00
|
|
|
reset_device(dev);
|
|
|
|
break;
|
|
|
|
}
|
2018-08-05 18:35:14 +03:00
|
|
|
break;
|
2018-02-09 16:44:14 +03:00
|
|
|
case PVRDMA_REG_IMR:
|
2019-03-11 13:29:05 +03:00
|
|
|
trace_pvrdma_regs_write(addr, val, "INTR_MASK", "");
|
2018-02-09 16:44:14 +03:00
|
|
|
dev->interrupt_mask = val;
|
|
|
|
break;
|
|
|
|
case PVRDMA_REG_REQUEST:
|
|
|
|
if (val == 0) {
|
2019-03-11 13:29:05 +03:00
|
|
|
trace_pvrdma_regs_write(addr, val, "REQUEST", "");
|
|
|
|
pvrdma_exec_cmd(dev);
|
2018-02-09 16:44:14 +03:00
|
|
|
}
|
2018-08-05 18:35:14 +03:00
|
|
|
break;
|
2018-02-09 16:44:14 +03:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static const MemoryRegionOps regs_ops = {
|
2019-03-11 13:29:05 +03:00
|
|
|
.read = pvrdma_regs_read,
|
|
|
|
.write = pvrdma_regs_write,
|
2018-02-09 16:44:14 +03:00
|
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
|
|
.impl = {
|
|
|
|
.min_access_size = sizeof(uint32_t),
|
|
|
|
.max_access_size = sizeof(uint32_t),
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2019-03-11 13:29:05 +03:00
|
|
|
static uint64_t pvrdma_uar_read(void *opaque, hwaddr addr, unsigned size)
|
2018-12-12 22:30:35 +03:00
|
|
|
{
|
|
|
|
return 0xffffffff;
|
|
|
|
}
|
|
|
|
|
2019-03-11 13:29:05 +03:00
|
|
|
static void pvrdma_uar_write(void *opaque, hwaddr addr, uint64_t val,
|
|
|
|
unsigned size)
|
2018-02-09 16:44:14 +03:00
|
|
|
{
|
|
|
|
PVRDMADev *dev = opaque;
|
|
|
|
|
2019-03-11 13:29:08 +03:00
|
|
|
dev->stats.uar_writes++;
|
|
|
|
|
2018-02-09 16:44:14 +03:00
|
|
|
switch (addr & 0xFFF) { /* Mask with 0xFFF as each UC gets page */
|
|
|
|
case PVRDMA_UAR_QP_OFFSET:
|
|
|
|
if (val & PVRDMA_UAR_QP_SEND) {
|
2019-03-11 13:29:05 +03:00
|
|
|
trace_pvrdma_uar_write(addr, val, "QP", "SEND",
|
|
|
|
val & PVRDMA_UAR_HANDLE_MASK, 0);
|
2018-02-09 16:44:14 +03:00
|
|
|
pvrdma_qp_send(dev, val & PVRDMA_UAR_HANDLE_MASK);
|
|
|
|
}
|
|
|
|
if (val & PVRDMA_UAR_QP_RECV) {
|
2019-03-11 13:29:05 +03:00
|
|
|
trace_pvrdma_uar_write(addr, val, "QP", "RECV",
|
|
|
|
val & PVRDMA_UAR_HANDLE_MASK, 0);
|
2018-02-09 16:44:14 +03:00
|
|
|
pvrdma_qp_recv(dev, val & PVRDMA_UAR_HANDLE_MASK);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case PVRDMA_UAR_CQ_OFFSET:
|
|
|
|
if (val & PVRDMA_UAR_CQ_ARM) {
|
2019-03-11 13:29:05 +03:00
|
|
|
trace_pvrdma_uar_write(addr, val, "CQ", "ARM",
|
|
|
|
val & PVRDMA_UAR_HANDLE_MASK,
|
|
|
|
!!(val & PVRDMA_UAR_CQ_ARM_SOL));
|
2018-02-09 16:44:14 +03:00
|
|
|
rdma_rm_req_notify_cq(&dev->rdma_dev_res,
|
|
|
|
val & PVRDMA_UAR_HANDLE_MASK,
|
|
|
|
!!(val & PVRDMA_UAR_CQ_ARM_SOL));
|
|
|
|
}
|
|
|
|
if (val & PVRDMA_UAR_CQ_ARM_SOL) {
|
2019-03-11 13:29:05 +03:00
|
|
|
trace_pvrdma_uar_write(addr, val, "CQ", "ARMSOL - not supported", 0,
|
|
|
|
0);
|
2018-02-09 16:44:14 +03:00
|
|
|
}
|
|
|
|
if (val & PVRDMA_UAR_CQ_POLL) {
|
2019-03-11 13:29:05 +03:00
|
|
|
trace_pvrdma_uar_write(addr, val, "CQ", "POLL",
|
|
|
|
val & PVRDMA_UAR_HANDLE_MASK, 0);
|
2018-02-09 16:44:14 +03:00
|
|
|
pvrdma_cq_poll(&dev->rdma_dev_res, val & PVRDMA_UAR_HANDLE_MASK);
|
|
|
|
}
|
|
|
|
break;
|
2019-04-03 14:33:43 +03:00
|
|
|
case PVRDMA_UAR_SRQ_OFFSET:
|
|
|
|
if (val & PVRDMA_UAR_SRQ_RECV) {
|
|
|
|
trace_pvrdma_uar_write(addr, val, "QP", "SRQ",
|
|
|
|
val & PVRDMA_UAR_HANDLE_MASK, 0);
|
|
|
|
pvrdma_srq_recv(dev, val & PVRDMA_UAR_HANDLE_MASK);
|
|
|
|
}
|
|
|
|
break;
|
2018-02-09 16:44:14 +03:00
|
|
|
default:
|
2019-03-11 13:29:05 +03:00
|
|
|
rdma_error_report("Unsupported command, addr=0x%"PRIx64", val=0x%"PRIx64,
|
|
|
|
addr, val);
|
2018-02-09 16:44:14 +03:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static const MemoryRegionOps uar_ops = {
|
2019-03-11 13:29:05 +03:00
|
|
|
.read = pvrdma_uar_read,
|
|
|
|
.write = pvrdma_uar_write,
|
2018-02-09 16:44:14 +03:00
|
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
|
|
.impl = {
|
|
|
|
.min_access_size = sizeof(uint32_t),
|
|
|
|
.max_access_size = sizeof(uint32_t),
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static void init_pci_config(PCIDevice *pdev)
|
|
|
|
{
|
|
|
|
pdev->config[PCI_INTERRUPT_PIN] = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void init_bars(PCIDevice *pdev)
|
|
|
|
{
|
|
|
|
PVRDMADev *dev = PVRDMA_DEV(pdev);
|
|
|
|
|
|
|
|
/* BAR 0 - MSI-X */
|
|
|
|
memory_region_init(&dev->msix, OBJECT(dev), "pvrdma-msix",
|
|
|
|
RDMA_BAR0_MSIX_SIZE);
|
|
|
|
pci_register_bar(pdev, RDMA_MSIX_BAR_IDX, PCI_BASE_ADDRESS_SPACE_MEMORY,
|
|
|
|
&dev->msix);
|
|
|
|
|
|
|
|
/* BAR 1 - Registers */
|
|
|
|
memset(&dev->regs_data, 0, sizeof(dev->regs_data));
|
|
|
|
memory_region_init_io(&dev->regs, OBJECT(dev), ®s_ops, dev,
|
2018-04-30 23:02:21 +03:00
|
|
|
"pvrdma-regs", sizeof(dev->regs_data));
|
2018-02-09 16:44:14 +03:00
|
|
|
pci_register_bar(pdev, RDMA_REG_BAR_IDX, PCI_BASE_ADDRESS_SPACE_MEMORY,
|
|
|
|
&dev->regs);
|
|
|
|
|
|
|
|
/* BAR 2 - UAR */
|
|
|
|
memset(&dev->uar_data, 0, sizeof(dev->uar_data));
|
|
|
|
memory_region_init_io(&dev->uar, OBJECT(dev), &uar_ops, dev, "rdma-uar",
|
2018-04-30 23:02:21 +03:00
|
|
|
sizeof(dev->uar_data));
|
2018-02-09 16:44:14 +03:00
|
|
|
pci_register_bar(pdev, RDMA_UAR_BAR_IDX, PCI_BASE_ADDRESS_SPACE_MEMORY,
|
|
|
|
&dev->uar);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void init_regs(PCIDevice *pdev)
|
|
|
|
{
|
|
|
|
PVRDMADev *dev = PVRDMA_DEV(pdev);
|
|
|
|
|
|
|
|
set_reg_val(dev, PVRDMA_REG_VERSION, PVRDMA_HW_VERSION);
|
|
|
|
set_reg_val(dev, PVRDMA_REG_ERR, 0xFFFF);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void init_dev_caps(PVRDMADev *dev)
|
|
|
|
{
|
|
|
|
size_t pg_tbl_bytes = TARGET_PAGE_SIZE *
|
|
|
|
(TARGET_PAGE_SIZE / sizeof(uint64_t));
|
|
|
|
size_t wr_sz = MAX(sizeof(struct pvrdma_sq_wqe_hdr),
|
|
|
|
sizeof(struct pvrdma_rq_wqe_hdr));
|
|
|
|
|
|
|
|
dev->dev_attr.max_qp_wr = pg_tbl_bytes /
|
2019-01-09 22:41:23 +03:00
|
|
|
(wr_sz + sizeof(struct pvrdma_sge) *
|
|
|
|
dev->dev_attr.max_sge) - TARGET_PAGE_SIZE;
|
|
|
|
/* First page is ring state ^^^^ */
|
2018-02-09 16:44:14 +03:00
|
|
|
|
|
|
|
dev->dev_attr.max_cqe = pg_tbl_bytes / sizeof(struct pvrdma_cqe) -
|
|
|
|
TARGET_PAGE_SIZE; /* First page is ring state */
|
2019-04-03 14:33:43 +03:00
|
|
|
|
|
|
|
dev->dev_attr.max_srq_wr = pg_tbl_bytes /
|
|
|
|
((sizeof(struct pvrdma_rq_wqe_hdr) +
|
|
|
|
sizeof(struct pvrdma_sge)) *
|
|
|
|
dev->dev_attr.max_sge) - TARGET_PAGE_SIZE;
|
2018-02-09 16:44:14 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static int pvrdma_check_ram_shared(Object *obj, void *opaque)
|
|
|
|
{
|
|
|
|
bool *shared = opaque;
|
|
|
|
|
|
|
|
if (object_dynamic_cast(obj, "memory-backend-ram")) {
|
|
|
|
*shared = object_property_get_bool(obj, "share", NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-12-21 17:40:34 +03:00
|
|
|
static void pvrdma_shutdown_notifier(Notifier *n, void *opaque)
|
|
|
|
{
|
|
|
|
PVRDMADev *dev = container_of(n, PVRDMADev, shutdown_notifier);
|
|
|
|
PCIDevice *pci_dev = PCI_DEVICE(dev);
|
|
|
|
|
|
|
|
pvrdma_fini(pci_dev);
|
|
|
|
}
|
|
|
|
|
2018-02-09 16:44:14 +03:00
|
|
|
static void pvrdma_realize(PCIDevice *pdev, Error **errp)
|
|
|
|
{
|
2018-12-12 20:58:17 +03:00
|
|
|
int rc = 0;
|
2018-02-09 16:44:14 +03:00
|
|
|
PVRDMADev *dev = PVRDMA_DEV(pdev);
|
|
|
|
Object *memdev_root;
|
|
|
|
bool ram_shared = false;
|
2018-12-21 17:40:27 +03:00
|
|
|
PCIDevice *func0;
|
2018-02-09 16:44:14 +03:00
|
|
|
|
2019-03-11 13:29:05 +03:00
|
|
|
rdma_info_report("Initializing device %s %x.%x", pdev->name,
|
|
|
|
PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
|
2018-02-09 16:44:14 +03:00
|
|
|
|
2019-10-13 05:11:45 +03:00
|
|
|
if (TARGET_PAGE_SIZE != qemu_real_host_page_size) {
|
2018-02-09 16:44:14 +03:00
|
|
|
error_setg(errp, "Target page size must be the same as host page size");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-12-21 17:40:27 +03:00
|
|
|
func0 = pci_get_function_0(pdev);
|
|
|
|
/* Break if not vmxnet3 device in slot 0 */
|
2019-03-11 13:29:15 +03:00
|
|
|
if (strcmp(object_get_typename(OBJECT(func0)), TYPE_VMXNET3)) {
|
2018-12-21 17:40:27 +03:00
|
|
|
error_setg(errp, "Device on %x.0 must be %s", PCI_SLOT(pdev->devfn),
|
|
|
|
TYPE_VMXNET3);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
dev->func0 = VMXNET3(func0);
|
|
|
|
|
2018-12-21 17:40:28 +03:00
|
|
|
addrconf_addr_eui48((unsigned char *)&dev->node_guid,
|
|
|
|
(const char *)&dev->func0->conf.macaddr.a);
|
|
|
|
|
2018-02-09 16:44:14 +03:00
|
|
|
memdev_root = object_resolve_path("/objects", NULL);
|
|
|
|
if (memdev_root) {
|
|
|
|
object_child_foreach(memdev_root, pvrdma_check_ram_shared, &ram_shared);
|
|
|
|
}
|
|
|
|
if (!ram_shared) {
|
|
|
|
error_setg(errp, "Only shared memory backed ram is supported");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
dev->dsr_info.dsr = NULL;
|
|
|
|
|
|
|
|
init_pci_config(pdev);
|
|
|
|
|
|
|
|
init_bars(pdev);
|
|
|
|
|
|
|
|
init_regs(pdev);
|
|
|
|
|
2019-03-11 13:29:05 +03:00
|
|
|
rc = init_msix(pdev);
|
2018-02-09 16:44:14 +03:00
|
|
|
if (rc) {
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
2018-08-05 18:35:18 +03:00
|
|
|
rc = rdma_backend_init(&dev->backend_dev, pdev, &dev->rdma_dev_res,
|
2018-02-09 16:44:14 +03:00
|
|
|
dev->backend_device_name, dev->backend_port_num,
|
2019-03-11 13:29:05 +03:00
|
|
|
&dev->dev_attr, &dev->mad_chr);
|
2018-02-09 16:44:14 +03:00
|
|
|
if (rc) {
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
2019-01-09 22:41:23 +03:00
|
|
|
init_dev_caps(dev);
|
|
|
|
|
2019-03-11 13:29:05 +03:00
|
|
|
rc = rdma_rm_init(&dev->rdma_dev_res, &dev->dev_attr);
|
2018-02-09 16:44:14 +03:00
|
|
|
if (rc) {
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
rc = pvrdma_qp_ops_init();
|
|
|
|
if (rc) {
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
2019-03-11 13:29:08 +03:00
|
|
|
memset(&dev->stats, 0, sizeof(dev->stats));
|
|
|
|
|
2018-12-21 17:40:34 +03:00
|
|
|
dev->shutdown_notifier.notify = pvrdma_shutdown_notifier;
|
|
|
|
qemu_register_shutdown_notifier(&dev->shutdown_notifier);
|
|
|
|
|
2019-08-18 16:21:07 +03:00
|
|
|
#ifdef LEGACY_RDMA_REG_MR
|
|
|
|
rdma_info_report("Using legacy reg_mr");
|
|
|
|
#else
|
|
|
|
rdma_info_report("Using iova reg_mr");
|
|
|
|
#endif
|
|
|
|
|
2018-02-09 16:44:14 +03:00
|
|
|
out:
|
|
|
|
if (rc) {
|
2018-12-12 20:58:17 +03:00
|
|
|
pvrdma_fini(pdev);
|
2019-03-11 13:29:05 +03:00
|
|
|
error_append_hint(errp, "Device failed to load\n");
|
2018-02-09 16:44:14 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pvrdma_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
2019-03-11 13:29:09 +03:00
|
|
|
RdmaProviderClass *ir = INTERFACE_RDMA_PROVIDER_CLASS(klass);
|
2018-02-09 16:44:14 +03:00
|
|
|
|
|
|
|
k->realize = pvrdma_realize;
|
|
|
|
k->vendor_id = PCI_VENDOR_ID_VMWARE;
|
|
|
|
k->device_id = PCI_DEVICE_ID_VMWARE_PVRDMA;
|
|
|
|
k->revision = 0x00;
|
|
|
|
k->class_id = PCI_CLASS_NETWORK_OTHER;
|
|
|
|
|
|
|
|
dc->desc = "RDMA Device";
|
2020-01-10 18:30:32 +03:00
|
|
|
device_class_set_props(dc, pvrdma_dev_properties);
|
2018-02-09 16:44:14 +03:00
|
|
|
set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
|
2019-03-11 13:29:09 +03:00
|
|
|
|
|
|
|
ir->print_statistics = pvrdma_print_statistics;
|
2018-02-09 16:44:14 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo pvrdma_info = {
|
|
|
|
.name = PVRDMA_HW_NAME,
|
|
|
|
.parent = TYPE_PCI_DEVICE,
|
|
|
|
.instance_size = sizeof(PVRDMADev),
|
|
|
|
.class_init = pvrdma_class_init,
|
|
|
|
.interfaces = (InterfaceInfo[]) {
|
|
|
|
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
|
2019-03-11 13:29:09 +03:00
|
|
|
{ INTERFACE_RDMA_PROVIDER },
|
2018-02-09 16:44:14 +03:00
|
|
|
{ }
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
static void register_types(void)
|
|
|
|
{
|
|
|
|
type_register_static(&pvrdma_info);
|
|
|
|
}
|
|
|
|
|
|
|
|
type_init(register_types)
|