2011-10-17 01:25:49 +04:00
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/*
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* KVM in-kernel IOPIC support
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*
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* Copyright (c) 2011 Siemens AG
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*
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* Authors:
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* Jan Kiszka <jan.kiszka@siemens.com>
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*
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* This work is licensed under the terms of the GNU GPL version 2.
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* See the COPYING file in the top-level directory.
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*/
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2016-01-26 21:17:03 +03:00
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#include "qemu/osdep.h"
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2015-09-22 16:18:20 +03:00
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#include "monitor/monitor.h"
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2019-12-12 16:14:40 +03:00
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#include "hw/i386/x86.h"
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2019-08-12 08:23:51 +03:00
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#include "hw/qdev-properties.h"
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2013-02-05 20:06:20 +04:00
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#include "hw/i386/ioapic_internal.h"
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#include "hw/i386/apic_internal.h"
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2012-12-17 21:20:04 +04:00
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#include "sysemu/kvm.h"
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2011-10-17 01:25:49 +04:00
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2012-11-15 00:54:02 +04:00
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/* PC Utility function */
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void kvm_pc_setup_irq_routing(bool pci_enabled)
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{
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KVMState *s = kvm_state;
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int i;
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2020-09-22 23:19:21 +03:00
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assert(kvm_has_gsi_routing());
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for (i = 0; i < 8; ++i) {
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if (i == 2) {
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continue;
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2012-11-15 00:54:02 +04:00
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}
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2020-09-22 23:19:21 +03:00
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kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_PIC_MASTER, i);
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}
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for (i = 8; i < 16; ++i) {
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kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_PIC_SLAVE, i - 8);
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}
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if (pci_enabled) {
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for (i = 0; i < 24; ++i) {
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if (i == 0) {
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kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_IOAPIC, 2);
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} else if (i != 2) {
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kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_IOAPIC, i);
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2012-11-15 00:54:02 +04:00
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}
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}
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}
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2020-09-22 23:19:21 +03:00
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kvm_irqchip_commit_routes(s);
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2012-11-15 00:54:02 +04:00
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}
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2011-10-17 01:25:49 +04:00
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typedef struct KVMIOAPICState KVMIOAPICState;
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struct KVMIOAPICState {
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IOAPICCommonState ioapic;
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uint32_t kvm_gsi_base;
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};
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static void kvm_ioapic_get(IOAPICCommonState *s)
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{
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struct kvm_irqchip chip;
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struct kvm_ioapic_state *kioapic;
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int ret, i;
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chip.chip_id = KVM_IRQCHIP_IOAPIC;
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ret = kvm_vm_ioctl(kvm_state, KVM_GET_IRQCHIP, &chip);
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if (ret < 0) {
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2021-05-19 14:35:28 +03:00
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fprintf(stderr, "KVM_GET_IRQCHIP failed: %s\n", strerror(-ret));
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2011-10-17 01:25:49 +04:00
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abort();
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}
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kioapic = &chip.chip.ioapic;
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s->id = kioapic->id;
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s->ioregsel = kioapic->ioregsel;
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s->irr = kioapic->irr;
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for (i = 0; i < IOAPIC_NUM_PINS; i++) {
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s->ioredtbl[i] = kioapic->redirtbl[i].bits;
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}
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}
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static void kvm_ioapic_put(IOAPICCommonState *s)
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{
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struct kvm_irqchip chip;
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struct kvm_ioapic_state *kioapic;
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int ret, i;
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chip.chip_id = KVM_IRQCHIP_IOAPIC;
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kioapic = &chip.chip.ioapic;
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kioapic->id = s->id;
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kioapic->ioregsel = s->ioregsel;
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kioapic->base_address = s->busdev.mmio[0].addr;
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kioapic->irr = s->irr;
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for (i = 0; i < IOAPIC_NUM_PINS; i++) {
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kioapic->redirtbl[i].bits = s->ioredtbl[i];
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}
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ret = kvm_vm_ioctl(kvm_state, KVM_SET_IRQCHIP, &chip);
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if (ret < 0) {
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2021-05-19 14:35:28 +03:00
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fprintf(stderr, "KVM_SET_IRQCHIP failed: %s\n", strerror(-ret));
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2011-10-17 01:25:49 +04:00
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abort();
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}
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}
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static void kvm_ioapic_reset(DeviceState *dev)
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{
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2013-07-27 18:30:47 +04:00
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IOAPICCommonState *s = IOAPIC_COMMON(dev);
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2011-10-17 01:25:49 +04:00
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ioapic_reset_common(dev);
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kvm_ioapic_put(s);
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}
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static void kvm_ioapic_set_irq(void *opaque, int irq, int level)
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{
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KVMIOAPICState *s = opaque;
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2017-12-29 10:31:03 +03:00
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IOAPICCommonState *common = IOAPIC_COMMON(s);
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2011-10-17 01:25:49 +04:00
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int delivered;
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2017-12-29 10:31:03 +03:00
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ioapic_stat_update_irq(common, irq, level);
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2012-07-26 18:35:12 +04:00
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delivered = kvm_set_irq(kvm_state, s->kvm_gsi_base + irq, level);
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2011-10-17 01:25:49 +04:00
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apic_report_irq_delivered(delivered);
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}
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2013-11-05 14:16:05 +04:00
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static void kvm_ioapic_realize(DeviceState *dev, Error **errp)
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2011-10-17 01:25:49 +04:00
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{
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2013-11-05 14:16:05 +04:00
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IOAPICCommonState *s = IOAPIC_COMMON(dev);
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2013-11-05 14:16:04 +04:00
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2018-05-15 17:35:16 +03:00
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memory_region_init_io(&s->io_memory, OBJECT(dev), NULL, NULL, "kvm-ioapic", 0x1000);
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2017-02-03 10:18:18 +03:00
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/*
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* KVM ioapic only supports 0x11 now. This will only be used when
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* we want to dump ioapic version.
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*/
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s->version = 0x11;
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2011-10-17 01:25:49 +04:00
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2013-11-05 14:16:04 +04:00
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qdev_init_gpio_in(dev, kvm_ioapic_set_irq, IOAPIC_NUM_PINS);
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2011-10-17 01:25:49 +04:00
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}
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2011-12-08 07:34:16 +04:00
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static Property kvm_ioapic_properties[] = {
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DEFINE_PROP_UINT32("gsi_base", KVMIOAPICState, kvm_gsi_base, 0),
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DEFINE_PROP_END_OF_LIST()
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};
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2012-01-24 23:12:29 +04:00
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static void kvm_ioapic_class_init(ObjectClass *klass, void *data)
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{
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IOAPICCommonClass *k = IOAPIC_COMMON_CLASS(klass);
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2011-12-08 07:34:16 +04:00
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DeviceClass *dc = DEVICE_CLASS(klass);
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2012-01-24 23:12:29 +04:00
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2013-11-05 14:16:05 +04:00
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k->realize = kvm_ioapic_realize;
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2012-01-24 23:12:29 +04:00
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k->pre_save = kvm_ioapic_get;
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k->post_load = kvm_ioapic_put;
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2011-12-08 07:34:16 +04:00
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dc->reset = kvm_ioapic_reset;
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2020-01-10 18:30:32 +03:00
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device_class_set_props(dc, kvm_ioapic_properties);
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2012-01-24 23:12:29 +04:00
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}
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2013-01-10 19:19:07 +04:00
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static const TypeInfo kvm_ioapic_info = {
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2019-01-05 05:38:31 +03:00
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.name = TYPE_KVM_IOAPIC,
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2011-12-08 07:34:16 +04:00
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.parent = TYPE_IOAPIC_COMMON,
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.instance_size = sizeof(KVMIOAPICState),
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2012-01-24 23:12:29 +04:00
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.class_init = kvm_ioapic_class_init,
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2011-10-17 01:25:49 +04:00
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};
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2012-02-09 18:20:55 +04:00
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static void kvm_ioapic_register_types(void)
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2011-10-17 01:25:49 +04:00
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{
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2011-12-08 07:34:16 +04:00
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type_register_static(&kvm_ioapic_info);
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2011-10-17 01:25:49 +04:00
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}
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2012-02-09 18:20:55 +04:00
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type_init(kvm_ioapic_register_types)
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