2022-09-23 20:38:27 +03:00
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#!/usr/bin/env python3
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##
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2023-03-20 12:25:32 +03:00
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## Copyright(c) 2019-2023 rev.ng Labs Srl. All Rights Reserved.
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2022-09-23 20:38:27 +03:00
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, see <http://www.gnu.org/licenses/>.
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##
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import sys
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import re
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import string
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from io import StringIO
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import hex_common
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2023-03-20 12:25:33 +03:00
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2022-09-23 20:38:27 +03:00
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##
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## Generate code to be fed to the idef_parser
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##
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## Consider A2_add:
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##
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## Rd32=add(Rs32,Rt32), { RdV=RsV+RtV;}
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##
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## We produce:
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##
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## A2_add(RdV, in RsV, in RtV) {
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## { RdV=RsV+RtV;}
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## }
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##
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## A2_add represents the instruction tag. Then we have a list of TCGv
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## that the code generated by the parser can expect in input. Some of
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## them are inputs ("in" prefix), while some others are outputs.
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##
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def main():
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hex_common.read_semantics_file(sys.argv[1])
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hex_common.read_attribs_file(sys.argv[2])
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hex_common.calculate_attribs()
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2023-12-11 01:07:08 +03:00
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hex_common.init_registers()
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2022-09-23 20:38:27 +03:00
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tagregs = hex_common.get_tagregs()
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tagimms = hex_common.get_tagimms()
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2023-03-20 12:25:33 +03:00
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with open(sys.argv[3], "w") as f:
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2022-09-23 20:38:27 +03:00
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f.write('#include "macros.inc"\n\n')
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for tag in hex_common.tags:
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## Skip the priv instructions
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2023-03-20 12:25:33 +03:00
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if "A_PRIV" in hex_common.attribdict[tag]:
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2022-09-23 20:38:27 +03:00
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continue
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## Skip the guest instructions
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if "A_GUEST" in hex_common.attribdict[tag]:
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2022-09-23 20:38:27 +03:00
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continue
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## Skip instructions that saturate in a ternary expression
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if tag in {"S2_asr_r_r_sat", "S2_asl_r_r_sat"}:
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continue
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## Skip instructions using switch
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if tag in {"S4_vrcrotate_acc", "S4_vrcrotate"}:
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continue
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## Skip trap instructions
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2023-03-20 12:25:33 +03:00
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if tag in {"J2_trap0", "J2_trap1"}:
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continue
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## Skip 128-bit instructions
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if tag in {"A7_croundd_ri", "A7_croundd_rr"}:
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continue
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2023-03-20 12:25:33 +03:00
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if tag in {
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"M7_wcmpyrw",
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"M7_wcmpyrwc",
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"M7_wcmpyiw",
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"M7_wcmpyiwc",
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"M7_wcmpyrw_rnd",
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"M7_wcmpyrwc_rnd",
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"M7_wcmpyiw_rnd",
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"M7_wcmpyiwc_rnd",
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}:
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continue
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## Skip interleave/deinterleave instructions
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if tag in {"S2_interleave", "S2_deinterleave"}:
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continue
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## Skip instructions using bit reverse
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if tag in {
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"S2_brev",
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"S2_brevp",
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"S2_ct0",
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"S2_ct1",
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"S2_ct0p",
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"S2_ct1p",
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"A4_tlbmatch",
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}:
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continue
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## Skip other unsupported instructions
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if tag == "S2_cabacdecbin" or tag == "A5_ACS":
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continue
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if tag.startswith("Y"):
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continue
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if tag.startswith("V6_"):
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continue
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2023-04-26 20:32:32 +03:00
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if ( tag.startswith("F") and
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tag not in {
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"F2_sfimm_p",
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"F2_sfimm_n",
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"F2_dfimm_p",
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"F2_dfimm_n",
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"F2_dfmpyll",
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"F2_dfmpylh"
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}):
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continue
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if tag.endswith("_locked"):
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continue
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if "A_COF" in hex_common.attribdict[tag]:
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continue
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2023-04-28 01:40:50 +03:00
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if ( tag.startswith('R6_release_') ):
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continue
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Hexagon (target/hexagon) Short-circuit packet register writes
In certain cases, we can avoid the overhead of writing to hex_new_value
and write directly to hex_gpr. We add need_commit field to DisasContext
indicating if the end-of-packet commit is needed. If it is not needed,
get_result_gpr() and get_result_gpr_pair() can return hex_gpr.
We pass the ctx->need_commit to helpers when needed.
Finally, we can early-exit from gen_reg_writes during packet commit.
There are a few instructions whose semantics write to the result before
reading all the inputs. Therefore, the idef-parser generated code is
incompatible with short-circuit. We tell idef-parser to skip them.
For debugging purposes, we add a cpu property to turn off short-circuit.
When the short-circuit property is false, we skip the analysis and force
the end-of-packet commit.
Here's a simple example of the TCG generated for
0x004000b4: 0x7800c020 { R0 = #0x1 }
BEFORE:
---- 004000b4
movi_i32 new_r0,$0x1
mov_i32 r0,new_r0
AFTER:
---- 004000b4
movi_i32 r0,$0x1
This patch reintroduces a use of check_for_attrib, so we remove the
G_GNUC_UNUSED added earlier in this series.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Brian Cain <bcain@quicinc.com>
Message-Id: <20230427230012.3800327-12-tsimpson@quicinc.com>
2023-04-28 02:00:02 +03:00
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## Skip instructions that are incompatible with short-circuit
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## packet register writes
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if ( tag == 'S2_insert' or
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tag == 'S2_insert_rp' or
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tag == 'S2_asr_r_svw_trun' or
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tag == 'A2_swiz' ):
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continue
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regs = tagregs[tag]
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imms = tagimms[tag]
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arguments = []
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2023-05-24 17:41:47 +03:00
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for regtype, regid in regs:
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2023-12-11 01:07:08 +03:00
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reg = hex_common.get_register(tag, regtype, regid)
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prefix = "in " if reg.is_read() else ""
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arguments.append(f"{prefix}{reg.reg_tcg()}")
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2023-03-20 12:25:33 +03:00
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for immlett, bits, immshift in imms:
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arguments.append(hex_common.imm_name(immlett))
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2023-03-20 12:25:32 +03:00
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f.write(f"{tag}({', '.join(arguments)}) {{\n")
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f.write(" ")
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2022-09-23 20:38:27 +03:00
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if hex_common.need_ea(tag):
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f.write("size4u_t EA; ")
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f.write(f"{hex_common.semdict[tag]}\n")
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f.write("}\n\n")
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2023-03-20 12:25:33 +03:00
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2022-09-23 20:38:27 +03:00
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if __name__ == "__main__":
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main()
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