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qemu/tests/tcg/xtensa/test_timer.S

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target-xtensa: allow using core configuration in tests Add path to the core configuration directory to test build command and replace .include asm directive with #include to enable preprocessing. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-10 20:20:52 +04:00
#include "macros.inc"
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
target/xtensa: tests: fix timer tests Don't expect that CCOUNT increments are equal to the number of executed instructions. Verify that timer interrupt does not fire before the programmed CCOMPARE value and does fire after. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2016-09-06 06:55:13 +03:00
#define CCOUNT_SHIFT 4
#define WAIT_LOOPS 20
tests/tcg/xtensa: conditionalize timer/CCOUNT tests Make timer/CCOUNT tests conditional on the presence of timer option and number of configured timers. Don't use hard coded interrupt levels for timers, use configured values. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:55:15 +03:00
#define level1 kernel
#define INTERRUPT_LEVEL(n) glue3(XCHAL_INT, n, _LEVEL)
target/xtensa: tests: fix timer tests Don't expect that CCOUNT increments are equal to the number of executed instructions. Verify that timer interrupt does not fire before the programmed CCOMPARE value and does fire after. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2016-09-06 06:55:13 +03:00
.macro make_ccount_delta target, delta
rsr \delta, ccount
rsr \target, ccount
sub \delta, \target, \delta
slli \delta, \delta, CCOUNT_SHIFT
add \target, \target, \delta
.endm
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
test_suite timer
tests/tcg/xtensa: conditionalize timer/CCOUNT tests Make timer/CCOUNT tests conditional on the presence of timer option and number of configured timers. Don't use hard coded interrupt levels for timers, use configured values. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:55:15 +03:00
#if XCHAL_HAVE_CCOUNT
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
test ccount
rsr a3, ccount
rsr a4, ccount
target/xtensa: tests: fix timer tests Don't expect that CCOUNT increments are equal to the number of executed instructions. Verify that timer interrupt does not fire before the programmed CCOMPARE value and does fire after. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2016-09-06 06:55:13 +03:00
assert ne, a3, a4
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
test_end
target/xtensa: tests: add ccount write tests Check that CCOUNT SR is writable and that CCOMPARE timers are updated when CCOUNT is written to. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15 19:42:31 +03:00
test ccount_write
rsr a3, ccount
rsr a4, ccount
sub a4, a4, a3
movi a2, 0x12345678
wsr a2, ccount
esync
rsr a3, ccount
sub a3, a3, a2
slli a4, a4, 2
assert ltu, a3, a4
test_end
tests/tcg/xtensa: conditionalize timer/CCOUNT tests Make timer/CCOUNT tests conditional on the presence of timer option and number of configured timers. Don't use hard coded interrupt levels for timers, use configured values. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:55:15 +03:00
#if XCHAL_NUM_TIMERS
tests/tcg/xtensa: fix vectors and checks in timer test Timer test assumes that timer 0 IRQ has level 1 and other timers have higher level IRQs. This assumption is not correct and the levels may be arbitrary. Fix that assumption by providing TIMER*_VECTOR macro and using it for vector selection and by making the check for the timer exception cause conditional. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-04-27 20:06:00 +03:00
#if INTERRUPT_LEVEL(XCHAL_TIMER0_INTERRUPT) == 1
#define TIMER0_VECTOR kernel
#else
#define TIMER0_VECTOR glue(level, INTERRUPT_LEVEL(XCHAL_TIMER0_INTERRUPT))
#endif
#if XCHAL_NUM_TIMERS > 1
#if INTERRUPT_LEVEL(XCHAL_TIMER1_INTERRUPT) == 1
#define TIMER1_VECTOR kernel
#else
#define TIMER1_VECTOR glue(level, INTERRUPT_LEVEL(XCHAL_TIMER1_INTERRUPT))
#endif
#endif
#if XCHAL_NUM_TIMERS > 2
#if INTERRUPT_LEVEL(XCHAL_TIMER2_INTERRUPT) == 1
#define TIMER2_VECTOR kernel
#else
#define TIMER2_VECTOR glue(level, INTERRUPT_LEVEL(XCHAL_TIMER2_INTERRUPT))
#endif
#endif
target/xtensa: tests: add ccount write tests Check that CCOUNT SR is writable and that CCOMPARE timers are updated when CCOUNT is written to. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15 19:42:31 +03:00
test ccount_update_deadline
movi a2, 0
wsr a2, intenable
rsr a2, interrupt
wsr a2, intclear
movi a2, 0
tests/tcg/xtensa: conditionalize timer/CCOUNT tests Make timer/CCOUNT tests conditional on the presence of timer option and number of configured timers. Don't use hard coded interrupt levels for timers, use configured values. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:55:15 +03:00
#if XCHAL_NUM_TIMERS > 1
target/xtensa: tests: add ccount write tests Check that CCOUNT SR is writable and that CCOMPARE timers are updated when CCOUNT is written to. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15 19:42:31 +03:00
wsr a2, ccompare1
tests/tcg/xtensa: conditionalize timer/CCOUNT tests Make timer/CCOUNT tests conditional on the presence of timer option and number of configured timers. Don't use hard coded interrupt levels for timers, use configured values. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:55:15 +03:00
#endif
#if XCHAL_NUM_TIMERS > 2
target/xtensa: tests: add ccount write tests Check that CCOUNT SR is writable and that CCOMPARE timers are updated when CCOUNT is written to. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15 19:42:31 +03:00
wsr a2, ccompare2
tests/tcg/xtensa: conditionalize timer/CCOUNT tests Make timer/CCOUNT tests conditional on the presence of timer option and number of configured timers. Don't use hard coded interrupt levels for timers, use configured values. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:55:15 +03:00
#endif
target/xtensa: tests: add ccount write tests Check that CCOUNT SR is writable and that CCOMPARE timers are updated when CCOUNT is written to. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15 19:42:31 +03:00
movi a2, 0x12345678
wsr a2, ccompare0
rsr a3, interrupt
assert eqi, a3, 0
movi a2, 0x12345677
wsr a2, ccount
esync
nop
rsr a2, interrupt
movi a3, 1 << XCHAL_TIMER0_INTERRUPT
assert eq, a2, a3
test_end
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
test ccompare
movi a2, 0
wsr a2, intenable
rsr a2, interrupt
wsr a2, intclear
target-xtensa: fix guest hang on masked CCOMPARE interrupt QEMU timer is used to post CCOMPARE interrupt when the core is halted. If that CCOMPARE interrupt is masked off then the timer must be rearmed in the callback, otherwise it will be rearmed next time the core goes to halt by the waiti instruction. Add test case into timer testsuite. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-10 06:25:04 +04:00
movi a2, 0
tests/tcg/xtensa: conditionalize timer/CCOUNT tests Make timer/CCOUNT tests conditional on the presence of timer option and number of configured timers. Don't use hard coded interrupt levels for timers, use configured values. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:55:15 +03:00
#if XCHAL_NUM_TIMERS > 1
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
wsr a2, ccompare1
tests/tcg/xtensa: conditionalize timer/CCOUNT tests Make timer/CCOUNT tests conditional on the presence of timer option and number of configured timers. Don't use hard coded interrupt levels for timers, use configured values. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:55:15 +03:00
#endif
#if XCHAL_NUM_TIMERS > 2
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
wsr a2, ccompare2
tests/tcg/xtensa: conditionalize timer/CCOUNT tests Make timer/CCOUNT tests conditional on the presence of timer option and number of configured timers. Don't use hard coded interrupt levels for timers, use configured values. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:55:15 +03:00
#endif
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
target/xtensa: tests: fix timer tests Don't expect that CCOUNT increments are equal to the number of executed instructions. Verify that timer interrupt does not fire before the programmed CCOMPARE value and does fire after. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2016-09-06 06:55:13 +03:00
make_ccount_delta a2, a15
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
wsr a2, ccompare0
1:
target/xtensa: tests: fix timer tests Don't expect that CCOUNT increments are equal to the number of executed instructions. Verify that timer interrupt does not fire before the programmed CCOMPARE value and does fire after. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2016-09-06 06:55:13 +03:00
rsr a3, interrupt
rsr a4, ccount
rsr a5, interrupt
sub a4, a4, a2
bgez a4, 2f
assert eqi, a3, 0
j 1b
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
2:
target/xtensa: tests: fix timer tests Don't expect that CCOUNT increments are equal to the number of executed instructions. Verify that timer interrupt does not fire before the programmed CCOMPARE value and does fire after. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2016-09-06 06:55:13 +03:00
assert nei, a5, 0
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
test_end
test ccompare0_interrupt
tests/tcg/xtensa: fix vectors and checks in timer test Timer test assumes that timer 0 IRQ has level 1 and other timers have higher level IRQs. This assumption is not correct and the levels may be arbitrary. Fix that assumption by providing TIMER*_VECTOR macro and using it for vector selection and by making the check for the timer exception cause conditional. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-04-27 20:06:00 +03:00
set_vector TIMER0_VECTOR, 2f
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
movi a2, 0
wsr a2, intenable
rsr a2, interrupt
wsr a2, intclear
target-xtensa: fix guest hang on masked CCOMPARE interrupt QEMU timer is used to post CCOMPARE interrupt when the core is halted. If that CCOMPARE interrupt is masked off then the timer must be rearmed in the callback, otherwise it will be rearmed next time the core goes to halt by the waiti instruction. Add test case into timer testsuite. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-10 06:25:04 +04:00
movi a2, 0
tests/tcg/xtensa: conditionalize timer/CCOUNT tests Make timer/CCOUNT tests conditional on the presence of timer option and number of configured timers. Don't use hard coded interrupt levels for timers, use configured values. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:55:15 +03:00
#if XCHAL_NUM_TIMERS > 1
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
wsr a2, ccompare1
tests/tcg/xtensa: conditionalize timer/CCOUNT tests Make timer/CCOUNT tests conditional on the presence of timer option and number of configured timers. Don't use hard coded interrupt levels for timers, use configured values. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:55:15 +03:00
#endif
#if XCHAL_NUM_TIMERS > 2
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
wsr a2, ccompare2
tests/tcg/xtensa: conditionalize timer/CCOUNT tests Make timer/CCOUNT tests conditional on the presence of timer option and number of configured timers. Don't use hard coded interrupt levels for timers, use configured values. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:55:15 +03:00
#endif
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
target/xtensa: tests: fix timer tests Don't expect that CCOUNT increments are equal to the number of executed instructions. Verify that timer interrupt does not fire before the programmed CCOMPARE value and does fire after. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2016-09-06 06:55:13 +03:00
movi a3, WAIT_LOOPS
make_ccount_delta a2, a15
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
wsr a2, ccompare0
rsync
rsr a2, interrupt
assert eqi, a2, 0
target/xtensa: tests: replace hardcoded interrupt masks Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15 06:58:55 +03:00
movi a2, 1 << XCHAL_TIMER0_INTERRUPT
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
wsr a2, intenable
rsil a2, 0
1:
tests/tcg/xtensa: remove dependency on the loop option xtensa core may not have the loop option, but still have timers. Don't use loop opcode in the timer test. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-04-26 04:12:53 +03:00
addi a3, a3, -1
bnez a3, 1b
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
test_fail
2:
tests/tcg/xtensa: fix vectors and checks in timer test Timer test assumes that timer 0 IRQ has level 1 and other timers have higher level IRQs. This assumption is not correct and the levels may be arbitrary. Fix that assumption by providing TIMER*_VECTOR macro and using it for vector selection and by making the check for the timer exception cause conditional. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-04-27 20:06:00 +03:00
#if INTERRUPT_LEVEL(XCHAL_TIMER0_INTERRUPT) == 1
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
rsr a2, exccause
assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */
tests/tcg/xtensa: conditionalize timer/CCOUNT tests Make timer/CCOUNT tests conditional on the presence of timer option and number of configured timers. Don't use hard coded interrupt levels for timers, use configured values. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:55:15 +03:00
#endif
tests/tcg/xtensa: fix vectors and checks in timer test Timer test assumes that timer 0 IRQ has level 1 and other timers have higher level IRQs. This assumption is not correct and the levels may be arbitrary. Fix that assumption by providing TIMER*_VECTOR macro and using it for vector selection and by making the check for the timer exception cause conditional. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-04-27 20:06:00 +03:00
test_end
tests/tcg/xtensa: conditionalize timer/CCOUNT tests Make timer/CCOUNT tests conditional on the presence of timer option and number of configured timers. Don't use hard coded interrupt levels for timers, use configured values. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:55:15 +03:00
#if XCHAL_NUM_TIMERS > 1
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
test ccompare1_interrupt
tests/tcg/xtensa: fix vectors and checks in timer test Timer test assumes that timer 0 IRQ has level 1 and other timers have higher level IRQs. This assumption is not correct and the levels may be arbitrary. Fix that assumption by providing TIMER*_VECTOR macro and using it for vector selection and by making the check for the timer exception cause conditional. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-04-27 20:06:00 +03:00
set_vector TIMER1_VECTOR, 2f
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
movi a2, 0
wsr a2, intenable
rsr a2, interrupt
wsr a2, intclear
target-xtensa: fix guest hang on masked CCOMPARE interrupt QEMU timer is used to post CCOMPARE interrupt when the core is halted. If that CCOMPARE interrupt is masked off then the timer must be rearmed in the callback, otherwise it will be rearmed next time the core goes to halt by the waiti instruction. Add test case into timer testsuite. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-10 06:25:04 +04:00
movi a2, 0
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
wsr a2, ccompare0
tests/tcg/xtensa: conditionalize timer/CCOUNT tests Make timer/CCOUNT tests conditional on the presence of timer option and number of configured timers. Don't use hard coded interrupt levels for timers, use configured values. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:55:15 +03:00
#if XCHAL_NUM_TIMERS > 2
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
wsr a2, ccompare2
tests/tcg/xtensa: conditionalize timer/CCOUNT tests Make timer/CCOUNT tests conditional on the presence of timer option and number of configured timers. Don't use hard coded interrupt levels for timers, use configured values. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:55:15 +03:00
#endif
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
target/xtensa: tests: fix timer tests Don't expect that CCOUNT increments are equal to the number of executed instructions. Verify that timer interrupt does not fire before the programmed CCOMPARE value and does fire after. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2016-09-06 06:55:13 +03:00
movi a3, WAIT_LOOPS
make_ccount_delta a2, a15
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
wsr a2, ccompare1
rsync
rsr a2, interrupt
assert eqi, a2, 0
target/xtensa: tests: replace hardcoded interrupt masks Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15 06:58:55 +03:00
movi a2, 1 << XCHAL_TIMER1_INTERRUPT
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
wsr a2, intenable
tests/tcg/xtensa: conditionalize timer/CCOUNT tests Make timer/CCOUNT tests conditional on the presence of timer option and number of configured timers. Don't use hard coded interrupt levels for timers, use configured values. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:55:15 +03:00
rsil a2, INTERRUPT_LEVEL(XCHAL_TIMER1_INTERRUPT) - 1
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
1:
tests/tcg/xtensa: remove dependency on the loop option xtensa core may not have the loop option, but still have timers. Don't use loop opcode in the timer test. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-04-26 04:12:53 +03:00
addi a3, a3, -1
bnez a3, 1b
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
test_fail
2:
tests/tcg/xtensa: fix vectors and checks in timer test Timer test assumes that timer 0 IRQ has level 1 and other timers have higher level IRQs. This assumption is not correct and the levels may be arbitrary. Fix that assumption by providing TIMER*_VECTOR macro and using it for vector selection and by making the check for the timer exception cause conditional. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-04-27 20:06:00 +03:00
#if INTERRUPT_LEVEL(XCHAL_TIMER1_INTERRUPT) == 1
rsr a2, exccause
assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */
#endif
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
test_end
tests/tcg/xtensa: conditionalize timer/CCOUNT tests Make timer/CCOUNT tests conditional on the presence of timer option and number of configured timers. Don't use hard coded interrupt levels for timers, use configured values. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:55:15 +03:00
#endif
#if XCHAL_NUM_TIMERS > 2
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
test ccompare2_interrupt
tests/tcg/xtensa: fix vectors and checks in timer test Timer test assumes that timer 0 IRQ has level 1 and other timers have higher level IRQs. This assumption is not correct and the levels may be arbitrary. Fix that assumption by providing TIMER*_VECTOR macro and using it for vector selection and by making the check for the timer exception cause conditional. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-04-27 20:06:00 +03:00
set_vector TIMER2_VECTOR, 2f
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
movi a2, 0
wsr a2, intenable
rsr a2, interrupt
wsr a2, intclear
target-xtensa: fix guest hang on masked CCOMPARE interrupt QEMU timer is used to post CCOMPARE interrupt when the core is halted. If that CCOMPARE interrupt is masked off then the timer must be rearmed in the callback, otherwise it will be rearmed next time the core goes to halt by the waiti instruction. Add test case into timer testsuite. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-10 06:25:04 +04:00
movi a2, 0
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
wsr a2, ccompare0
wsr a2, ccompare1
target/xtensa: tests: fix timer tests Don't expect that CCOUNT increments are equal to the number of executed instructions. Verify that timer interrupt does not fire before the programmed CCOMPARE value and does fire after. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2016-09-06 06:55:13 +03:00
movi a3, WAIT_LOOPS
make_ccount_delta a2, a15
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
wsr a2, ccompare2
rsync
rsr a2, interrupt
assert eqi, a2, 0
target/xtensa: tests: replace hardcoded interrupt masks Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15 06:58:55 +03:00
movi a2, 1 << XCHAL_TIMER2_INTERRUPT
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
wsr a2, intenable
tests/tcg/xtensa: conditionalize timer/CCOUNT tests Make timer/CCOUNT tests conditional on the presence of timer option and number of configured timers. Don't use hard coded interrupt levels for timers, use configured values. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:55:15 +03:00
rsil a2, INTERRUPT_LEVEL(XCHAL_TIMER2_INTERRUPT) - 1
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
1:
tests/tcg/xtensa: remove dependency on the loop option xtensa core may not have the loop option, but still have timers. Don't use loop opcode in the timer test. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-04-26 04:12:53 +03:00
addi a3, a3, -1
bnez a3, 1b
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
test_fail
2:
tests/tcg/xtensa: fix vectors and checks in timer test Timer test assumes that timer 0 IRQ has level 1 and other timers have higher level IRQs. This assumption is not correct and the levels may be arbitrary. Fix that assumption by providing TIMER*_VECTOR macro and using it for vector selection and by making the check for the timer exception cause conditional. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-04-27 20:06:00 +03:00
#if INTERRUPT_LEVEL(XCHAL_TIMER2_INTERRUPT) == 1
rsr a2, exccause
assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */
#endif
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
test_end
tests/tcg/xtensa: conditionalize timer/CCOUNT tests Make timer/CCOUNT tests conditional on the presence of timer option and number of configured timers. Don't use hard coded interrupt levels for timers, use configured values. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:55:15 +03:00
#endif
target-xtensa: fix guest hang on masked CCOMPARE interrupt QEMU timer is used to post CCOMPARE interrupt when the core is halted. If that CCOMPARE interrupt is masked off then the timer must be rearmed in the callback, otherwise it will be rearmed next time the core goes to halt by the waiti instruction. Add test case into timer testsuite. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-10 06:25:04 +04:00
test ccompare_interrupt_masked
tests/tcg/xtensa: fix vectors and checks in timer test Timer test assumes that timer 0 IRQ has level 1 and other timers have higher level IRQs. This assumption is not correct and the levels may be arbitrary. Fix that assumption by providing TIMER*_VECTOR macro and using it for vector selection and by making the check for the timer exception cause conditional. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-04-27 20:06:00 +03:00
set_vector TIMER0_VECTOR, 2f
target-xtensa: fix guest hang on masked CCOMPARE interrupt QEMU timer is used to post CCOMPARE interrupt when the core is halted. If that CCOMPARE interrupt is masked off then the timer must be rearmed in the callback, otherwise it will be rearmed next time the core goes to halt by the waiti instruction. Add test case into timer testsuite. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-10 06:25:04 +04:00
movi a2, 0
wsr a2, intenable
rsr a2, interrupt
wsr a2, intclear
movi a2, 0
tests/tcg/xtensa: conditionalize timer/CCOUNT tests Make timer/CCOUNT tests conditional on the presence of timer option and number of configured timers. Don't use hard coded interrupt levels for timers, use configured values. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:55:15 +03:00
#if XCHAL_NUM_TIMERS > 2
target-xtensa: fix guest hang on masked CCOMPARE interrupt QEMU timer is used to post CCOMPARE interrupt when the core is halted. If that CCOMPARE interrupt is masked off then the timer must be rearmed in the callback, otherwise it will be rearmed next time the core goes to halt by the waiti instruction. Add test case into timer testsuite. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-10 06:25:04 +04:00
wsr a2, ccompare2
tests/tcg/xtensa: conditionalize timer/CCOUNT tests Make timer/CCOUNT tests conditional on the presence of timer option and number of configured timers. Don't use hard coded interrupt levels for timers, use configured values. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:55:15 +03:00
#endif
target-xtensa: fix guest hang on masked CCOMPARE interrupt QEMU timer is used to post CCOMPARE interrupt when the core is halted. If that CCOMPARE interrupt is masked off then the timer must be rearmed in the callback, otherwise it will be rearmed next time the core goes to halt by the waiti instruction. Add test case into timer testsuite. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-10 06:25:04 +04:00
tests/tcg/xtensa: remove dependency on the loop option xtensa core may not have the loop option, but still have timers. Don't use loop opcode in the timer test. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-04-26 04:12:53 +03:00
movi a3, WAIT_LOOPS
target/xtensa: tests: fix timer tests Don't expect that CCOUNT increments are equal to the number of executed instructions. Verify that timer interrupt does not fire before the programmed CCOMPARE value and does fire after. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2016-09-06 06:55:13 +03:00
make_ccount_delta a2, a15
tests/tcg/xtensa: conditionalize timer/CCOUNT tests Make timer/CCOUNT tests conditional on the presence of timer option and number of configured timers. Don't use hard coded interrupt levels for timers, use configured values. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:55:15 +03:00
#if XCHAL_NUM_TIMERS > 1
target-xtensa: fix guest hang on masked CCOMPARE interrupt QEMU timer is used to post CCOMPARE interrupt when the core is halted. If that CCOMPARE interrupt is masked off then the timer must be rearmed in the callback, otherwise it will be rearmed next time the core goes to halt by the waiti instruction. Add test case into timer testsuite. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-10 06:25:04 +04:00
wsr a2, ccompare1
tests/tcg/xtensa: conditionalize timer/CCOUNT tests Make timer/CCOUNT tests conditional on the presence of timer option and number of configured timers. Don't use hard coded interrupt levels for timers, use configured values. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:55:15 +03:00
#endif
target/xtensa: tests: fix timer tests Don't expect that CCOUNT increments are equal to the number of executed instructions. Verify that timer interrupt does not fire before the programmed CCOMPARE value and does fire after. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2016-09-06 06:55:13 +03:00
add a2, a2, a15
target-xtensa: fix guest hang on masked CCOMPARE interrupt QEMU timer is used to post CCOMPARE interrupt when the core is halted. If that CCOMPARE interrupt is masked off then the timer must be rearmed in the callback, otherwise it will be rearmed next time the core goes to halt by the waiti instruction. Add test case into timer testsuite. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-10 06:25:04 +04:00
wsr a2, ccompare0
rsync
rsr a2, interrupt
assert eqi, a2, 0
target/xtensa: tests: replace hardcoded interrupt masks Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15 06:58:55 +03:00
movi a2, 1 << XCHAL_TIMER0_INTERRUPT
target-xtensa: fix guest hang on masked CCOMPARE interrupt QEMU timer is used to post CCOMPARE interrupt when the core is halted. If that CCOMPARE interrupt is masked off then the timer must be rearmed in the callback, otherwise it will be rearmed next time the core goes to halt by the waiti instruction. Add test case into timer testsuite. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-10 06:25:04 +04:00
wsr a2, intenable
rsil a2, 0
1:
tests/tcg/xtensa: remove dependency on the loop option xtensa core may not have the loop option, but still have timers. Don't use loop opcode in the timer test. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-04-26 04:12:53 +03:00
addi a3, a3, -1
bnez a3, 1b
target-xtensa: fix guest hang on masked CCOMPARE interrupt QEMU timer is used to post CCOMPARE interrupt when the core is halted. If that CCOMPARE interrupt is masked off then the timer must be rearmed in the callback, otherwise it will be rearmed next time the core goes to halt by the waiti instruction. Add test case into timer testsuite. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-10 06:25:04 +04:00
test_fail
2:
tests/tcg/xtensa: fix vectors and checks in timer test Timer test assumes that timer 0 IRQ has level 1 and other timers have higher level IRQs. This assumption is not correct and the levels may be arbitrary. Fix that assumption by providing TIMER*_VECTOR macro and using it for vector selection and by making the check for the timer exception cause conditional. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-04-27 20:06:00 +03:00
#if INTERRUPT_LEVEL(XCHAL_TIMER0_INTERRUPT) == 1
target-xtensa: fix guest hang on masked CCOMPARE interrupt QEMU timer is used to post CCOMPARE interrupt when the core is halted. If that CCOMPARE interrupt is masked off then the timer must be rearmed in the callback, otherwise it will be rearmed next time the core goes to halt by the waiti instruction. Add test case into timer testsuite. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-10 06:25:04 +04:00
rsr a2, exccause
assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */
tests/tcg/xtensa: fix vectors and checks in timer test Timer test assumes that timer 0 IRQ has level 1 and other timers have higher level IRQs. This assumption is not correct and the levels may be arbitrary. Fix that assumption by providing TIMER*_VECTOR macro and using it for vector selection and by making the check for the timer exception cause conditional. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-04-27 20:06:00 +03:00
#endif
target-xtensa: fix guest hang on masked CCOMPARE interrupt QEMU timer is used to post CCOMPARE interrupt when the core is halted. If that CCOMPARE interrupt is masked off then the timer must be rearmed in the callback, otherwise it will be rearmed next time the core goes to halt by the waiti instruction. Add test case into timer testsuite. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-10 06:25:04 +04:00
test_end
test ccompare_interrupt_masked_waiti
tests/tcg/xtensa: fix vectors and checks in timer test Timer test assumes that timer 0 IRQ has level 1 and other timers have higher level IRQs. This assumption is not correct and the levels may be arbitrary. Fix that assumption by providing TIMER*_VECTOR macro and using it for vector selection and by making the check for the timer exception cause conditional. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-04-27 20:06:00 +03:00
set_vector TIMER0_VECTOR, 2f
target-xtensa: fix guest hang on masked CCOMPARE interrupt QEMU timer is used to post CCOMPARE interrupt when the core is halted. If that CCOMPARE interrupt is masked off then the timer must be rearmed in the callback, otherwise it will be rearmed next time the core goes to halt by the waiti instruction. Add test case into timer testsuite. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-10 06:25:04 +04:00
movi a2, 0
wsr a2, intenable
rsr a2, interrupt
wsr a2, intclear
movi a2, 0
tests/tcg/xtensa: conditionalize timer/CCOUNT tests Make timer/CCOUNT tests conditional on the presence of timer option and number of configured timers. Don't use hard coded interrupt levels for timers, use configured values. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:55:15 +03:00
#if XCHAL_NUM_TIMERS > 2
target-xtensa: fix guest hang on masked CCOMPARE interrupt QEMU timer is used to post CCOMPARE interrupt when the core is halted. If that CCOMPARE interrupt is masked off then the timer must be rearmed in the callback, otherwise it will be rearmed next time the core goes to halt by the waiti instruction. Add test case into timer testsuite. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-10 06:25:04 +04:00
wsr a2, ccompare2
tests/tcg/xtensa: conditionalize timer/CCOUNT tests Make timer/CCOUNT tests conditional on the presence of timer option and number of configured timers. Don't use hard coded interrupt levels for timers, use configured values. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:55:15 +03:00
#endif
target-xtensa: fix guest hang on masked CCOMPARE interrupt QEMU timer is used to post CCOMPARE interrupt when the core is halted. If that CCOMPARE interrupt is masked off then the timer must be rearmed in the callback, otherwise it will be rearmed next time the core goes to halt by the waiti instruction. Add test case into timer testsuite. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-10 06:25:04 +04:00
target/xtensa: tests: fix timer tests Don't expect that CCOUNT increments are equal to the number of executed instructions. Verify that timer interrupt does not fire before the programmed CCOMPARE value and does fire after. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2016-09-06 06:55:13 +03:00
make_ccount_delta a2, a15
tests/tcg/xtensa: conditionalize timer/CCOUNT tests Make timer/CCOUNT tests conditional on the presence of timer option and number of configured timers. Don't use hard coded interrupt levels for timers, use configured values. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:55:15 +03:00
#if XCHAL_NUM_TIMERS > 1
target-xtensa: fix guest hang on masked CCOMPARE interrupt QEMU timer is used to post CCOMPARE interrupt when the core is halted. If that CCOMPARE interrupt is masked off then the timer must be rearmed in the callback, otherwise it will be rearmed next time the core goes to halt by the waiti instruction. Add test case into timer testsuite. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-10 06:25:04 +04:00
wsr a2, ccompare1
tests/tcg/xtensa: conditionalize timer/CCOUNT tests Make timer/CCOUNT tests conditional on the presence of timer option and number of configured timers. Don't use hard coded interrupt levels for timers, use configured values. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:55:15 +03:00
#endif
target/xtensa: tests: fix timer tests Don't expect that CCOUNT increments are equal to the number of executed instructions. Verify that timer interrupt does not fire before the programmed CCOMPARE value and does fire after. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2016-09-06 06:55:13 +03:00
add a2, a2, a15
target-xtensa: fix guest hang on masked CCOMPARE interrupt QEMU timer is used to post CCOMPARE interrupt when the core is halted. If that CCOMPARE interrupt is masked off then the timer must be rearmed in the callback, otherwise it will be rearmed next time the core goes to halt by the waiti instruction. Add test case into timer testsuite. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-10 06:25:04 +04:00
wsr a2, ccompare0
rsync
rsr a2, interrupt
assert eqi, a2, 0
target/xtensa: tests: replace hardcoded interrupt masks Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15 06:58:55 +03:00
movi a2, 1 << XCHAL_TIMER0_INTERRUPT
target-xtensa: fix guest hang on masked CCOMPARE interrupt QEMU timer is used to post CCOMPARE interrupt when the core is halted. If that CCOMPARE interrupt is masked off then the timer must be rearmed in the callback, otherwise it will be rearmed next time the core goes to halt by the waiti instruction. Add test case into timer testsuite. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-10 06:25:04 +04:00
wsr a2, intenable
waiti 0
test_fail
2:
tests/tcg/xtensa: fix vectors and checks in timer test Timer test assumes that timer 0 IRQ has level 1 and other timers have higher level IRQs. This assumption is not correct and the levels may be arbitrary. Fix that assumption by providing TIMER*_VECTOR macro and using it for vector selection and by making the check for the timer exception cause conditional. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-04-27 20:06:00 +03:00
#if INTERRUPT_LEVEL(XCHAL_TIMER0_INTERRUPT) == 1
target-xtensa: fix guest hang on masked CCOMPARE interrupt QEMU timer is used to post CCOMPARE interrupt when the core is halted. If that CCOMPARE interrupt is masked off then the timer must be rearmed in the callback, otherwise it will be rearmed next time the core goes to halt by the waiti instruction. Add test case into timer testsuite. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-10 06:25:04 +04:00
rsr a2, exccause
assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */
tests/tcg/xtensa: fix vectors and checks in timer test Timer test assumes that timer 0 IRQ has level 1 and other timers have higher level IRQs. This assumption is not correct and the levels may be arbitrary. Fix that assumption by providing TIMER*_VECTOR macro and using it for vector selection and by making the check for the timer exception cause conditional. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2022-04-27 20:06:00 +03:00
#endif
target-xtensa: fix guest hang on masked CCOMPARE interrupt QEMU timer is used to post CCOMPARE interrupt when the core is halted. If that CCOMPARE interrupt is masked off then the timer must be rearmed in the callback, otherwise it will be rearmed next time the core goes to halt by the waiti instruction. Add test case into timer testsuite. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-10 06:25:04 +04:00
test_end
tests/tcg/xtensa: conditionalize timer/CCOUNT tests Make timer/CCOUNT tests conditional on the presence of timer option and number of configured timers. Don't use hard coded interrupt levels for timers, use configured values. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:55:15 +03:00
#endif
#endif
target-xtensa: add regression testsuite Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 03:55:57 +04:00
test_suite_end
Reference in New Issue Copy Permalink