73 lines
2.6 KiB
C
73 lines
2.6 KiB
C
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#ifndef MMU_RADIX64_H
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#define MMU_RADIX64_H
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#ifndef CONFIG_USER_ONLY
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/* Radix Quadrants */
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#define R_EADDR_MASK 0x3FFFFFFFFFFFFFFF
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#define R_EADDR_QUADRANT 0xC000000000000000
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#define R_EADDR_QUADRANT0 0x0000000000000000
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#define R_EADDR_QUADRANT1 0x4000000000000000
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#define R_EADDR_QUADRANT2 0x8000000000000000
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#define R_EADDR_QUADRANT3 0xC000000000000000
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/* Radix Partition Table Entry Fields */
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#define PATBE1_R_PRTB 0x0FFFFFFFFFFFF000
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#define PATBE1_R_PRTS 0x000000000000001F
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/* Radix Process Table Entry Fields */
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#define PRTBE_R_GET_RTS(rts) \
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((((rts >> 58) & 0x18) | ((rts >> 5) & 0x7)) + 31)
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#define PRTBE_R_RPDB 0x0FFFFFFFFFFFFF00
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#define PRTBE_R_RPDS 0x000000000000001F
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/* Radix Page Directory/Table Entry Fields */
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#define R_PTE_VALID 0x8000000000000000
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#define R_PTE_LEAF 0x4000000000000000
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#define R_PTE_SW0 0x2000000000000000
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#define R_PTE_RPN 0x01FFFFFFFFFFF000
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#define R_PTE_SW1 0x0000000000000E00
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#define R_GET_SW(sw) (((sw >> 58) & 0x8) | ((sw >> 9) & 0x7))
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#define R_PTE_R 0x0000000000000100
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#define R_PTE_C 0x0000000000000080
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#define R_PTE_ATT 0x0000000000000030
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#define R_PTE_ATT_NORMAL 0x0000000000000000
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#define R_PTE_ATT_SAO 0x0000000000000010
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#define R_PTE_ATT_NI_IO 0x0000000000000020
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#define R_PTE_ATT_TOLERANT_IO 0x0000000000000030
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#define R_PTE_EAA_PRIV 0x0000000000000008
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#define R_PTE_EAA_R 0x0000000000000004
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#define R_PTE_EAA_RW 0x0000000000000002
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#define R_PTE_EAA_X 0x0000000000000001
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#define R_PDE_NLB PRTBE_R_RPDB
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#define R_PDE_NLS PRTBE_R_RPDS
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#ifdef TARGET_PPC64
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int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
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int mmu_idx);
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static inline int ppc_radix64_get_prot_eaa(uint64_t pte)
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{
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return (pte & R_PTE_EAA_R ? PAGE_READ : 0) |
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(pte & R_PTE_EAA_RW ? PAGE_READ | PAGE_WRITE : 0) |
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(pte & R_PTE_EAA_X ? PAGE_EXEC : 0);
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}
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static inline int ppc_radix64_get_prot_amr(PowerPCCPU *cpu)
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{
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CPUPPCState *env = &cpu->env;
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int amr = env->spr[SPR_AMR] >> 62; /* We only care about key0 AMR63:62 */
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int iamr = env->spr[SPR_IAMR] >> 62; /* We only care about key0 IAMR63:62 */
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return (amr & 0x2 ? 0 : PAGE_WRITE) | /* Access denied if bit is set */
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(amr & 0x1 ? 0 : PAGE_READ) |
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(iamr & 0x1 ? 0 : PAGE_EXEC);
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}
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#endif /* TARGET_PPC64 */
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#endif /* CONFIG_USER_ONLY */
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#endif /* MMU_RADIX64_H */
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