2021-02-08 08:46:11 +03:00
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/*
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* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* This program generates the encodings file that is processed by
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* the dectree.py script to produce the decoding tree. We use the C
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* preprocessor to manipulate the files imported from the Hexagon
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* architecture library.
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*/
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#include <stdio.h>
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#include <string.h>
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#include "opcodes.h"
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#define STRINGIZE(X) #X
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const char * const opcode_names[] = {
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#define OPCODE(IID) STRINGIZE(IID)
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#include "opcodes_def_generated.h.inc"
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NULL
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#undef OPCODE
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};
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/*
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* Process the instruction definitions
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* Scalar core instructions have the following form
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* Q6INSN(A2_add,"Rd32=add(Rs32,Rt32)",ATTRIBS(),
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* "Add 32-bit registers",
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* { RdV=RsV+RtV;})
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2021-02-26 13:57:23 +03:00
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* HVX instructions have the following form
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* EXTINSN(V6_vinsertwr, "Vx32.w=vinsert(Rt32)",
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* ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VX,A_CVI_LATE),
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* "Insert Word Scalar into Vector",
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* VxV.uw[0] = RtV;)
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2021-02-08 08:46:11 +03:00
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*/
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const char * const opcode_syntax[XX_LAST_OPCODE] = {
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#define Q6INSN(TAG, BEH, ATTRIBS, DESCR, SEM) \
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[TAG] = BEH,
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#define EXTINSN(TAG, BEH, ATTRIBS, DESCR, SEM) \
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[TAG] = BEH,
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#include "imported/allidefs.def"
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#undef Q6INSN
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#undef EXTINSN
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};
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const OpcodeEncoding opcode_encodings[] = {
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#define DEF_ENC32(TAG, ENCSTR) \
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[TAG] = { .encoding = ENCSTR },
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#define DEF_ENC_SUBINSN(TAG, CLASS, ENCSTR) \
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[TAG] = { .encoding = ENCSTR, .enc_class = CLASS },
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#define DEF_EXT_ENC(TAG, CLASS, ENCSTR) \
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[TAG] = { .encoding = ENCSTR, .enc_class = CLASS },
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#include "imported/encode.def"
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#undef DEF_ENC32
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#undef DEF_ENC_SUBINSN
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#undef DEF_EXT_ENC
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};
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static const char * const opcode_enc_class_names[XX_LAST_ENC_CLASS] = {
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"NORMAL",
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"16BIT",
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"SUBINSN_A",
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"SUBINSN_L1",
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"SUBINSN_L2",
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"SUBINSN_S1",
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"SUBINSN_S2",
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"EXT_noext",
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"EXT_mmvec",
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};
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static const char *get_opcode_enc(int opcode)
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{
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const char *tmp = opcode_encodings[opcode].encoding;
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if (tmp == NULL) {
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tmp = "MISSING ENCODING";
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}
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return tmp;
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}
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static const char *get_opcode_enc_class(int opcode)
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{
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2021-02-26 13:57:23 +03:00
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const char *tmp = opcode_encodings[opcode].encoding;
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if (tmp == NULL) {
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const char *test = "V6_"; /* HVX */
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const char *name = opcode_names[opcode];
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if (strncmp(name, test, strlen(test)) == 0) {
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return "EXT_mmvec";
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}
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}
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2021-02-08 08:46:11 +03:00
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return opcode_enc_class_names[opcode_encodings[opcode].enc_class];
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}
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static void gen_iset_table(FILE *out)
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{
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int i;
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fprintf(out, "iset = {\n");
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for (i = 0; i < XX_LAST_OPCODE; i++) {
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fprintf(out, "\t\'%s\' : {\n", opcode_names[i]);
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fprintf(out, "\t\t\'tag\' : \'%s\',\n", opcode_names[i]);
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fprintf(out, "\t\t\'syntax\' : \'%s\',\n", opcode_syntax[i]);
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fprintf(out, "\t\t\'enc\' : \'%s\',\n", get_opcode_enc(i));
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fprintf(out, "\t\t\'enc_class\' : \'%s\',\n", get_opcode_enc_class(i));
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fprintf(out, "\t},\n");
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}
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fprintf(out, "};\n\n");
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}
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static void gen_tags_list(FILE *out)
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{
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int i;
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fprintf(out, "tags = [\n");
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for (i = 0; i < XX_LAST_OPCODE; i++) {
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fprintf(out, "\t\'%s\',\n", opcode_names[i]);
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}
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fprintf(out, "];\n\n");
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}
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int main(int argc, char *argv[])
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{
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FILE *outfile;
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if (argc != 2) {
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fprintf(stderr, "Usage: gen_dectree_import ouptputfile\n");
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return 1;
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}
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outfile = fopen(argv[1], "w");
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if (outfile == NULL) {
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fprintf(stderr, "Cannot open %s for writing\n", argv[1]);
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return 1;
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}
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gen_iset_table(outfile);
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gen_tags_list(outfile);
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fclose(outfile);
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return 0;
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}
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