2003-08-09 03:58:05 +04:00
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/*
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* Software MMU support
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2007-09-17 01:08:06 +04:00
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*
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2011-09-22 00:00:18 +04:00
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* Generate helpers used by TCG for qemu_ld/st ops and code load
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* functions.
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*
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* Included from target op helpers and exec.c.
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*
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2003-08-09 03:58:05 +04:00
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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2009-07-17 00:47:01 +04:00
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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2003-08-09 03:58:05 +04:00
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*/
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#if DATA_SIZE == 8
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#define SUFFIX q
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2013-08-27 22:31:48 +04:00
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#define LSUFFIX q
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2013-08-28 01:09:14 +04:00
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#define SDATA_TYPE int64_t
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2014-01-18 17:47:23 +04:00
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#define DATA_TYPE uint64_t
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2003-08-09 03:58:05 +04:00
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#elif DATA_SIZE == 4
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#define SUFFIX l
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2013-08-27 22:31:48 +04:00
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#define LSUFFIX l
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2013-08-28 01:09:14 +04:00
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#define SDATA_TYPE int32_t
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2014-01-18 17:47:23 +04:00
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#define DATA_TYPE uint32_t
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2003-08-09 03:58:05 +04:00
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#elif DATA_SIZE == 2
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#define SUFFIX w
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2013-08-27 22:31:48 +04:00
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#define LSUFFIX uw
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2013-08-28 01:09:14 +04:00
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#define SDATA_TYPE int16_t
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2014-01-18 17:47:23 +04:00
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#define DATA_TYPE uint16_t
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2003-08-09 03:58:05 +04:00
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#elif DATA_SIZE == 1
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#define SUFFIX b
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2013-08-27 22:31:48 +04:00
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#define LSUFFIX ub
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2013-08-28 01:09:14 +04:00
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#define SDATA_TYPE int8_t
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2014-01-18 17:47:23 +04:00
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#define DATA_TYPE uint8_t
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2003-08-09 03:58:05 +04:00
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#else
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#error unsupported data size
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#endif
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2013-08-28 01:09:14 +04:00
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/* For the benefit of TCG generated code, we want to avoid the complication
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of ABI-specific return type promotion and always return a value extended
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to the register size of the host. This is tcg_target_long, except in the
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case of a 32-bit host and 64-bit data, and for that we always have
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uint64_t. Don't bother with this widened value for SOFTMMU_CODE_ACCESS. */
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#if defined(SOFTMMU_CODE_ACCESS) || DATA_SIZE == 8
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# define WORD_TYPE DATA_TYPE
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# define USUFFIX SUFFIX
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#else
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# define WORD_TYPE tcg_target_ulong
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# define USUFFIX glue(u, SUFFIX)
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# define SSUFFIX glue(s, SUFFIX)
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#endif
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2004-10-03 19:07:13 +04:00
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#ifdef SOFTMMU_CODE_ACCESS
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2014-07-07 14:23:56 +04:00
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#define READ_ACCESS_TYPE MMU_INST_FETCH
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2005-11-29 00:19:04 +03:00
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#define ADDR_READ addr_code
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2004-10-03 19:07:13 +04:00
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#else
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2014-07-07 14:23:56 +04:00
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#define READ_ACCESS_TYPE MMU_DATA_LOAD
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2005-11-29 00:19:04 +03:00
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#define ADDR_READ addr_read
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2004-10-03 19:07:13 +04:00
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#endif
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2013-09-04 22:45:20 +04:00
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#if DATA_SIZE == 8
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# define BSWAP(X) bswap64(X)
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#elif DATA_SIZE == 4
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# define BSWAP(X) bswap32(X)
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#elif DATA_SIZE == 2
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# define BSWAP(X) bswap16(X)
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#else
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# define BSWAP(X) (X)
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#endif
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#if DATA_SIZE == 1
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# define helper_le_ld_name glue(glue(helper_ret_ld, USUFFIX), MMUSUFFIX)
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# define helper_be_ld_name helper_le_ld_name
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# define helper_le_lds_name glue(glue(helper_ret_ld, SSUFFIX), MMUSUFFIX)
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# define helper_be_lds_name helper_le_lds_name
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# define helper_le_st_name glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)
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# define helper_be_st_name helper_le_st_name
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#else
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# define helper_le_ld_name glue(glue(helper_le_ld, USUFFIX), MMUSUFFIX)
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# define helper_be_ld_name glue(glue(helper_be_ld, USUFFIX), MMUSUFFIX)
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# define helper_le_lds_name glue(glue(helper_le_ld, SSUFFIX), MMUSUFFIX)
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# define helper_be_lds_name glue(glue(helper_be_ld, SSUFFIX), MMUSUFFIX)
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# define helper_le_st_name glue(glue(helper_le_st, SUFFIX), MMUSUFFIX)
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# define helper_be_st_name glue(glue(helper_be_st, SUFFIX), MMUSUFFIX)
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#endif
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2014-03-28 20:55:24 +04:00
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#ifndef SOFTMMU_CODE_ACCESS
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2012-09-02 19:28:56 +04:00
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static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
|
2016-07-09 04:51:28 +03:00
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|
size_t mmu_idx, size_t index,
|
2008-06-29 05:03:05 +04:00
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target_ulong addr,
|
2012-04-09 18:20:20 +04:00
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uintptr_t retaddr)
|
2003-08-09 03:58:05 +04:00
|
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{
|
2016-07-09 04:51:28 +03:00
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CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index];
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return io_readx(env, iotlbentry, addr, retaddr, DATA_SIZE);
|
2003-08-09 03:58:05 +04:00
|
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|
}
|
2014-03-28 20:55:24 +04:00
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|
#endif
|
2003-08-09 03:58:05 +04:00
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|
2015-05-13 19:10:33 +03:00
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WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, uintptr_t retaddr)
|
2003-08-09 03:58:05 +04:00
|
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|
{
|
2015-05-13 19:10:33 +03:00
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unsigned mmu_idx = get_mmuidx(oi);
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2013-07-26 22:29:15 +04:00
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int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
|
2016-07-14 22:43:06 +03:00
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unsigned a_bits = get_alignment_bits(get_memop(oi));
|
2013-07-26 22:29:15 +04:00
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uintptr_t haddr;
|
2013-09-04 22:45:20 +04:00
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DATA_TYPE res;
|
2007-09-17 12:09:54 +04:00
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|
2016-07-14 22:43:06 +03:00
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if (addr & ((1 << a_bits) - 1)) {
|
2016-06-23 21:16:46 +03:00
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cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
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mmu_idx, retaddr);
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}
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|
2013-07-26 22:29:15 +04:00
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/* If the TLB entry is for a different page, reload and try again. */
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if ((addr & TARGET_PAGE_MASK)
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!= (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
|
2016-07-06 21:26:52 +03:00
|
|
|
if (!VICTIM_TLB_HIT(ADDR_READ, addr)) {
|
implementing victim TLB for QEMU system emulated TLB
QEMU system mode page table walks are expensive. Taken by running QEMU
qemu-system-x86_64 system mode on Intel PIN , a TLB miss and walking a
4-level page tables in guest Linux OS takes ~450 X86 instructions on
average.
QEMU system mode TLB is implemented using a directly-mapped hashtable.
This structure suffers from conflict misses. Increasing the
associativity of the TLB may not be the solution to conflict misses as
all the ways may have to be walked in serial.
A victim TLB is a TLB used to hold translations evicted from the
primary TLB upon replacement. The victim TLB lies between the main TLB
and its refill path. Victim TLB is of greater associativity (fully
associative in this patch). It takes longer to lookup the victim TLB,
but its likely better than a full page table walk. The memory
translation path is changed as follows :
Before Victim TLB:
1. Inline TLB lookup
2. Exit code cache on TLB miss.
3. Check for unaligned, IO accesses
4. TLB refill.
5. Do the memory access.
6. Return to code cache.
After Victim TLB:
1. Inline TLB lookup
2. Exit code cache on TLB miss.
3. Check for unaligned, IO accesses
4. Victim TLB lookup.
5. If victim TLB misses, TLB refill
6. Do the memory access.
7. Return to code cache
The advantage is that victim TLB can offer more associativity to a
directly mapped TLB and thus potentially fewer page table walks while
still keeping the time taken to flush within reasonable limits.
However, placing a victim TLB before the refill path increase TLB
refill path as the victim TLB is consulted before the TLB refill. The
performance results demonstrate that the pros outweigh the cons.
some performance results taken on SPECINT2006 train
datasets and kernel boot and qemu configure script on an
Intel(R) Xeon(R) CPU E5620 @ 2.40GHz Linux machine are shown in the
Google Doc link below.
https://docs.google.com/spreadsheets/d/1eiItzekZwNQOal_h-5iJmC4tMDi051m9qidi5_nwvH4/edit?usp=sharing
In summary, victim TLB improves the performance of qemu-system-x86_64 by
11% on average on SPECINT2006, kernelboot and qemu configscript and with
highest improvement of in 26% in 456.hmmer. And victim TLB does not result
in any performance degradation in any of the measured benchmarks. Furthermore,
the implemented victim TLB is architecture independent and is expected to
benefit other architectures in QEMU as well.
Although there are measurement fluctuations, the performance
improvement is very significant and by no means in the range of
noises.
Signed-off-by: Xin Tong <trent.tong@gmail.com>
Message-id: 1407202523-23553-1-git-send-email-trent.tong@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-05 05:35:23 +04:00
|
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tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
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mmu_idx, retaddr);
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}
|
2013-07-26 22:29:15 +04:00
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tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
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|
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}
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/* Handle an IO access. */
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|
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if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
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if ((addr & (DATA_SIZE - 1)) != 0) {
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goto do_unaligned_access;
|
2003-08-09 03:58:05 +04:00
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}
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2013-09-04 22:45:20 +04:00
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/* ??? Note that the io helpers always read data in the target
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byte ordering. We should push the LE/BE request down into io. */
|
2016-07-09 04:51:28 +03:00
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res = glue(io_read, SUFFIX)(env, mmu_idx, index, addr, retaddr);
|
2013-09-04 22:45:20 +04:00
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res = TGT_LE(res);
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return res;
|
2013-07-26 22:29:15 +04:00
|
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|
}
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/* Handle slow unaligned access (it spans two pages or IO). */
|
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if (DATA_SIZE > 1
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&& unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
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|
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>= TARGET_PAGE_SIZE)) {
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target_ulong addr1, addr2;
|
2013-09-04 22:45:20 +04:00
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DATA_TYPE res1, res2;
|
2013-07-26 22:29:15 +04:00
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unsigned shift;
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do_unaligned_access:
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addr1 = addr & ~(DATA_SIZE - 1);
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addr2 = addr1 + DATA_SIZE;
|
2016-07-26 03:39:16 +03:00
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res1 = helper_le_ld_name(env, addr1, oi, retaddr);
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res2 = helper_le_ld_name(env, addr2, oi, retaddr);
|
2013-07-26 22:29:15 +04:00
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shift = (addr & (DATA_SIZE - 1)) * 8;
|
2013-09-04 22:45:20 +04:00
|
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/* Little-endian combine. */
|
2013-07-26 22:29:15 +04:00
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res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
|
2013-09-04 22:45:20 +04:00
|
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|
return res;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
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|
haddr = addr + env->tlb_table[mmu_idx][index].addend;
|
|
|
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|
#if DATA_SIZE == 1
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|
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|
res = glue(glue(ld, LSUFFIX), _p)((uint8_t *)haddr);
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#else
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res = glue(glue(ld, LSUFFIX), _le_p)((uint8_t *)haddr);
|
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|
|
|
#endif
|
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|
|
|
return res;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#if DATA_SIZE > 1
|
2015-05-13 19:10:33 +03:00
|
|
|
WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr,
|
|
|
|
|
TCGMemOpIdx oi, uintptr_t retaddr)
|
2013-09-04 22:45:20 +04:00
|
|
|
{
|
2015-05-13 19:10:33 +03:00
|
|
|
unsigned mmu_idx = get_mmuidx(oi);
|
2013-09-04 22:45:20 +04:00
|
|
|
int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
|
|
|
|
target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
|
2016-07-14 22:43:06 +03:00
|
|
|
unsigned a_bits = get_alignment_bits(get_memop(oi));
|
2013-09-04 22:45:20 +04:00
|
|
|
uintptr_t haddr;
|
|
|
|
|
DATA_TYPE res;
|
|
|
|
|
|
2016-07-14 22:43:06 +03:00
|
|
|
if (addr & ((1 << a_bits) - 1)) {
|
2016-06-23 21:16:46 +03:00
|
|
|
cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
|
|
|
|
|
mmu_idx, retaddr);
|
|
|
|
|
}
|
|
|
|
|
|
2013-09-04 22:45:20 +04:00
|
|
|
/* If the TLB entry is for a different page, reload and try again. */
|
|
|
|
|
if ((addr & TARGET_PAGE_MASK)
|
|
|
|
|
!= (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
|
2016-07-06 21:26:52 +03:00
|
|
|
if (!VICTIM_TLB_HIT(ADDR_READ, addr)) {
|
implementing victim TLB for QEMU system emulated TLB
QEMU system mode page table walks are expensive. Taken by running QEMU
qemu-system-x86_64 system mode on Intel PIN , a TLB miss and walking a
4-level page tables in guest Linux OS takes ~450 X86 instructions on
average.
QEMU system mode TLB is implemented using a directly-mapped hashtable.
This structure suffers from conflict misses. Increasing the
associativity of the TLB may not be the solution to conflict misses as
all the ways may have to be walked in serial.
A victim TLB is a TLB used to hold translations evicted from the
primary TLB upon replacement. The victim TLB lies between the main TLB
and its refill path. Victim TLB is of greater associativity (fully
associative in this patch). It takes longer to lookup the victim TLB,
but its likely better than a full page table walk. The memory
translation path is changed as follows :
Before Victim TLB:
1. Inline TLB lookup
2. Exit code cache on TLB miss.
3. Check for unaligned, IO accesses
4. TLB refill.
5. Do the memory access.
6. Return to code cache.
After Victim TLB:
1. Inline TLB lookup
2. Exit code cache on TLB miss.
3. Check for unaligned, IO accesses
4. Victim TLB lookup.
5. If victim TLB misses, TLB refill
6. Do the memory access.
7. Return to code cache
The advantage is that victim TLB can offer more associativity to a
directly mapped TLB and thus potentially fewer page table walks while
still keeping the time taken to flush within reasonable limits.
However, placing a victim TLB before the refill path increase TLB
refill path as the victim TLB is consulted before the TLB refill. The
performance results demonstrate that the pros outweigh the cons.
some performance results taken on SPECINT2006 train
datasets and kernel boot and qemu configure script on an
Intel(R) Xeon(R) CPU E5620 @ 2.40GHz Linux machine are shown in the
Google Doc link below.
https://docs.google.com/spreadsheets/d/1eiItzekZwNQOal_h-5iJmC4tMDi051m9qidi5_nwvH4/edit?usp=sharing
In summary, victim TLB improves the performance of qemu-system-x86_64 by
11% on average on SPECINT2006, kernelboot and qemu configscript and with
highest improvement of in 26% in 456.hmmer. And victim TLB does not result
in any performance degradation in any of the measured benchmarks. Furthermore,
the implemented victim TLB is architecture independent and is expected to
benefit other architectures in QEMU as well.
Although there are measurement fluctuations, the performance
improvement is very significant and by no means in the range of
noises.
Signed-off-by: Xin Tong <trent.tong@gmail.com>
Message-id: 1407202523-23553-1-git-send-email-trent.tong@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-05 05:35:23 +04:00
|
|
|
tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
|
|
|
|
|
mmu_idx, retaddr);
|
|
|
|
|
}
|
2013-09-04 22:45:20 +04:00
|
|
|
tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Handle an IO access. */
|
|
|
|
|
if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
|
|
|
|
|
if ((addr & (DATA_SIZE - 1)) != 0) {
|
|
|
|
|
goto do_unaligned_access;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* ??? Note that the io helpers always read data in the target
|
|
|
|
|
byte ordering. We should push the LE/BE request down into io. */
|
2016-07-09 04:51:28 +03:00
|
|
|
res = glue(io_read, SUFFIX)(env, mmu_idx, index, addr, retaddr);
|
2013-09-04 22:45:20 +04:00
|
|
|
res = TGT_BE(res);
|
|
|
|
|
return res;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Handle slow unaligned access (it spans two pages or IO). */
|
|
|
|
|
if (DATA_SIZE > 1
|
|
|
|
|
&& unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
|
|
|
|
|
>= TARGET_PAGE_SIZE)) {
|
|
|
|
|
target_ulong addr1, addr2;
|
|
|
|
|
DATA_TYPE res1, res2;
|
|
|
|
|
unsigned shift;
|
|
|
|
|
do_unaligned_access:
|
|
|
|
|
addr1 = addr & ~(DATA_SIZE - 1);
|
|
|
|
|
addr2 = addr1 + DATA_SIZE;
|
2016-07-26 03:39:16 +03:00
|
|
|
res1 = helper_be_ld_name(env, addr1, oi, retaddr);
|
|
|
|
|
res2 = helper_be_ld_name(env, addr2, oi, retaddr);
|
2013-09-04 22:45:20 +04:00
|
|
|
shift = (addr & (DATA_SIZE - 1)) * 8;
|
|
|
|
|
|
|
|
|
|
/* Big-endian combine. */
|
|
|
|
|
res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
|
2013-07-26 22:29:15 +04:00
|
|
|
return res;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
haddr = addr + env->tlb_table[mmu_idx][index].addend;
|
2013-09-04 22:45:20 +04:00
|
|
|
res = glue(glue(ld, LSUFFIX), _be_p)((uint8_t *)haddr);
|
|
|
|
|
return res;
|
2003-08-09 03:58:05 +04:00
|
|
|
}
|
2013-09-04 22:45:20 +04:00
|
|
|
#endif /* DATA_SIZE > 1 */
|
2003-08-09 03:58:05 +04:00
|
|
|
|
2004-10-03 19:07:13 +04:00
|
|
|
#ifndef SOFTMMU_CODE_ACCESS
|
|
|
|
|
|
2013-08-28 01:09:14 +04:00
|
|
|
/* Provide signed versions of the load routines as well. We can of course
|
|
|
|
|
avoid this for 64-bit data, or for 32-bit data on 32-bit host. */
|
|
|
|
|
#if DATA_SIZE * 8 < TCG_TARGET_REG_BITS
|
2013-09-04 22:45:20 +04:00
|
|
|
WORD_TYPE helper_le_lds_name(CPUArchState *env, target_ulong addr,
|
2015-05-13 19:10:33 +03:00
|
|
|
TCGMemOpIdx oi, uintptr_t retaddr)
|
2013-09-04 22:45:20 +04:00
|
|
|
{
|
2015-05-13 19:10:33 +03:00
|
|
|
return (SDATA_TYPE)helper_le_ld_name(env, addr, oi, retaddr);
|
2013-09-04 22:45:20 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
# if DATA_SIZE > 1
|
|
|
|
|
WORD_TYPE helper_be_lds_name(CPUArchState *env, target_ulong addr,
|
2015-05-13 19:10:33 +03:00
|
|
|
TCGMemOpIdx oi, uintptr_t retaddr)
|
2013-08-28 01:09:14 +04:00
|
|
|
{
|
2015-05-13 19:10:33 +03:00
|
|
|
return (SDATA_TYPE)helper_be_ld_name(env, addr, oi, retaddr);
|
2013-08-28 01:09:14 +04:00
|
|
|
}
|
2013-09-04 22:45:20 +04:00
|
|
|
# endif
|
2013-08-28 01:09:14 +04:00
|
|
|
#endif
|
|
|
|
|
|
2012-09-02 19:28:56 +04:00
|
|
|
static inline void glue(io_write, SUFFIX)(CPUArchState *env,
|
2016-07-09 04:51:28 +03:00
|
|
|
size_t mmu_idx, size_t index,
|
2004-10-03 19:07:13 +04:00
|
|
|
DATA_TYPE val,
|
2008-06-09 04:20:13 +04:00
|
|
|
target_ulong addr,
|
2012-04-09 18:20:20 +04:00
|
|
|
uintptr_t retaddr)
|
2004-10-03 19:07:13 +04:00
|
|
|
{
|
2016-07-09 04:51:28 +03:00
|
|
|
CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index];
|
|
|
|
|
return io_writex(env, iotlbentry, val, addr, retaddr, DATA_SIZE);
|
2004-10-03 19:07:13 +04:00
|
|
|
}
|
2003-08-09 03:58:05 +04:00
|
|
|
|
2013-09-04 22:45:20 +04:00
|
|
|
void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
|
2015-05-13 19:10:33 +03:00
|
|
|
TCGMemOpIdx oi, uintptr_t retaddr)
|
2003-08-09 03:58:05 +04:00
|
|
|
{
|
2015-05-13 19:10:33 +03:00
|
|
|
unsigned mmu_idx = get_mmuidx(oi);
|
2013-07-26 22:29:15 +04:00
|
|
|
int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
|
|
|
|
target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
|
2016-07-14 22:43:06 +03:00
|
|
|
unsigned a_bits = get_alignment_bits(get_memop(oi));
|
2013-07-26 22:29:15 +04:00
|
|
|
uintptr_t haddr;
|
2007-09-17 12:09:54 +04:00
|
|
|
|
2016-07-14 22:43:06 +03:00
|
|
|
if (addr & ((1 << a_bits) - 1)) {
|
2016-06-23 21:16:46 +03:00
|
|
|
cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
|
|
|
|
|
mmu_idx, retaddr);
|
|
|
|
|
}
|
|
|
|
|
|
2013-07-26 22:29:15 +04:00
|
|
|
/* If the TLB entry is for a different page, reload and try again. */
|
|
|
|
|
if ((addr & TARGET_PAGE_MASK)
|
|
|
|
|
!= (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
|
2016-07-06 21:26:52 +03:00
|
|
|
if (!VICTIM_TLB_HIT(addr_write, addr)) {
|
2014-07-07 14:23:56 +04:00
|
|
|
tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
|
implementing victim TLB for QEMU system emulated TLB
QEMU system mode page table walks are expensive. Taken by running QEMU
qemu-system-x86_64 system mode on Intel PIN , a TLB miss and walking a
4-level page tables in guest Linux OS takes ~450 X86 instructions on
average.
QEMU system mode TLB is implemented using a directly-mapped hashtable.
This structure suffers from conflict misses. Increasing the
associativity of the TLB may not be the solution to conflict misses as
all the ways may have to be walked in serial.
A victim TLB is a TLB used to hold translations evicted from the
primary TLB upon replacement. The victim TLB lies between the main TLB
and its refill path. Victim TLB is of greater associativity (fully
associative in this patch). It takes longer to lookup the victim TLB,
but its likely better than a full page table walk. The memory
translation path is changed as follows :
Before Victim TLB:
1. Inline TLB lookup
2. Exit code cache on TLB miss.
3. Check for unaligned, IO accesses
4. TLB refill.
5. Do the memory access.
6. Return to code cache.
After Victim TLB:
1. Inline TLB lookup
2. Exit code cache on TLB miss.
3. Check for unaligned, IO accesses
4. Victim TLB lookup.
5. If victim TLB misses, TLB refill
6. Do the memory access.
7. Return to code cache
The advantage is that victim TLB can offer more associativity to a
directly mapped TLB and thus potentially fewer page table walks while
still keeping the time taken to flush within reasonable limits.
However, placing a victim TLB before the refill path increase TLB
refill path as the victim TLB is consulted before the TLB refill. The
performance results demonstrate that the pros outweigh the cons.
some performance results taken on SPECINT2006 train
datasets and kernel boot and qemu configure script on an
Intel(R) Xeon(R) CPU E5620 @ 2.40GHz Linux machine are shown in the
Google Doc link below.
https://docs.google.com/spreadsheets/d/1eiItzekZwNQOal_h-5iJmC4tMDi051m9qidi5_nwvH4/edit?usp=sharing
In summary, victim TLB improves the performance of qemu-system-x86_64 by
11% on average on SPECINT2006, kernelboot and qemu configscript and with
highest improvement of in 26% in 456.hmmer. And victim TLB does not result
in any performance degradation in any of the measured benchmarks. Furthermore,
the implemented victim TLB is architecture independent and is expected to
benefit other architectures in QEMU as well.
Although there are measurement fluctuations, the performance
improvement is very significant and by no means in the range of
noises.
Signed-off-by: Xin Tong <trent.tong@gmail.com>
Message-id: 1407202523-23553-1-git-send-email-trent.tong@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-05 05:35:23 +04:00
|
|
|
}
|
2013-07-26 22:29:15 +04:00
|
|
|
tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Handle an IO access. */
|
|
|
|
|
if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
|
|
|
|
|
if ((addr & (DATA_SIZE - 1)) != 0) {
|
|
|
|
|
goto do_unaligned_access;
|
|
|
|
|
}
|
2013-09-04 22:45:20 +04:00
|
|
|
|
|
|
|
|
/* ??? Note that the io helpers always read data in the target
|
|
|
|
|
byte ordering. We should push the LE/BE request down into io. */
|
|
|
|
|
val = TGT_LE(val);
|
2016-07-09 04:51:28 +03:00
|
|
|
glue(io_write, SUFFIX)(env, mmu_idx, index, val, addr, retaddr);
|
2013-07-26 22:29:15 +04:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Handle slow unaligned access (it spans two pages or IO). */
|
|
|
|
|
if (DATA_SIZE > 1
|
|
|
|
|
&& unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
|
|
|
|
|
>= TARGET_PAGE_SIZE)) {
|
cputlb: Fix for self-modifying writes across page boundaries
As it currently stands, QEMU does not properly handle self-modifying code
when the write is unaligned and crosses a page boundary. The procedure
for handling a write to the current translation block is to write-protect
the current translation block, catch the write, split up the translation
block into the current instruction (which remains write-protected so that
the current instruction is not modified) and the remaining instructions
in the translation block, and then restore the CPU state to before the
write occurred so the write will be retried and successfully executed.
However, since unaligned writes across pages are split into one-byte
writes for simplicity, writes to the second page (which is not the
current TB) may succeed before a write to the current TB is attempted,
and since these writes are not invalidated before resuming state after
splitting the TB, these writes will be performed a second time, thus
corrupting the second page. Credit goes to Patrick Hulin for
discovering this.
In recent 64-bit versions of Windows running in emulated mode, this
results in either being very unstable (a BSOD after a couple minutes of
uptime), or being entirely unable to boot. Windows performs one or more
8-byte unaligned self-modifying writes (xors) which intersect the end
of the current TB and the beginning of the next TB, which runs into the
aforementioned issue. This commit fixes that issue by making the
unaligned write loop perform the writes in forwards order, instead of
reverse order. This way, QEMU immediately tries to write to the current
TB, and splits the TB before any write to the second page is executed.
The write then proceeds as intended. With this patch applied, I am able
to boot and use Windows 7 64-bit and Windows 10 64-bit in QEMU without
KVM.
Per Richard Henderson's input, this patch also ensures the second page
is in the TLB before executing the write loop, to ensure the second
page is mapped.
The original discussion of the issue is located at
http://lists.nongnu.org/archive/html/qemu-devel/2014-08/msg02161.html.
Signed-off-by: Samuel Damashek <samuel.damashek@invincea.com>
Message-Id: <20160706182652.16190-1-samuel.damashek@invincea.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-07-08 22:54:34 +03:00
|
|
|
int i, index2;
|
|
|
|
|
target_ulong page2, tlb_addr2;
|
2013-07-26 22:29:15 +04:00
|
|
|
do_unaligned_access:
|
cputlb: Fix for self-modifying writes across page boundaries
As it currently stands, QEMU does not properly handle self-modifying code
when the write is unaligned and crosses a page boundary. The procedure
for handling a write to the current translation block is to write-protect
the current translation block, catch the write, split up the translation
block into the current instruction (which remains write-protected so that
the current instruction is not modified) and the remaining instructions
in the translation block, and then restore the CPU state to before the
write occurred so the write will be retried and successfully executed.
However, since unaligned writes across pages are split into one-byte
writes for simplicity, writes to the second page (which is not the
current TB) may succeed before a write to the current TB is attempted,
and since these writes are not invalidated before resuming state after
splitting the TB, these writes will be performed a second time, thus
corrupting the second page. Credit goes to Patrick Hulin for
discovering this.
In recent 64-bit versions of Windows running in emulated mode, this
results in either being very unstable (a BSOD after a couple minutes of
uptime), or being entirely unable to boot. Windows performs one or more
8-byte unaligned self-modifying writes (xors) which intersect the end
of the current TB and the beginning of the next TB, which runs into the
aforementioned issue. This commit fixes that issue by making the
unaligned write loop perform the writes in forwards order, instead of
reverse order. This way, QEMU immediately tries to write to the current
TB, and splits the TB before any write to the second page is executed.
The write then proceeds as intended. With this patch applied, I am able
to boot and use Windows 7 64-bit and Windows 10 64-bit in QEMU without
KVM.
Per Richard Henderson's input, this patch also ensures the second page
is in the TLB before executing the write loop, to ensure the second
page is mapped.
The original discussion of the issue is located at
http://lists.nongnu.org/archive/html/qemu-devel/2014-08/msg02161.html.
Signed-off-by: Samuel Damashek <samuel.damashek@invincea.com>
Message-Id: <20160706182652.16190-1-samuel.damashek@invincea.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-07-08 22:54:34 +03:00
|
|
|
/* Ensure the second page is in the TLB. Note that the first page
|
|
|
|
|
is already guaranteed to be filled, and that the second page
|
|
|
|
|
cannot evict the first. */
|
|
|
|
|
page2 = (addr + DATA_SIZE) & TARGET_PAGE_MASK;
|
|
|
|
|
index2 = (page2 >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
|
|
|
|
tlb_addr2 = env->tlb_table[mmu_idx][index2].addr_write;
|
|
|
|
|
if (page2 != (tlb_addr2 & (TARGET_PAGE_MASK | TLB_INVALID_MASK))
|
|
|
|
|
&& !VICTIM_TLB_HIT(addr_write, page2)) {
|
|
|
|
|
tlb_fill(ENV_GET_CPU(env), page2, MMU_DATA_STORE,
|
|
|
|
|
mmu_idx, retaddr);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* XXX: not efficient, but simple. */
|
|
|
|
|
/* This loop must go in the forward direction to avoid issues
|
|
|
|
|
with self-modifying code in Windows 64-bit. */
|
|
|
|
|
for (i = 0; i < DATA_SIZE; ++i) {
|
2013-09-04 22:45:20 +04:00
|
|
|
/* Little-endian extract. */
|
2013-07-26 22:29:15 +04:00
|
|
|
uint8_t val8 = val >> (i * 8);
|
2013-09-04 22:45:20 +04:00
|
|
|
glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8,
|
2016-07-26 03:39:16 +03:00
|
|
|
oi, retaddr);
|
2013-09-04 22:45:20 +04:00
|
|
|
}
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
haddr = addr + env->tlb_table[mmu_idx][index].addend;
|
|
|
|
|
#if DATA_SIZE == 1
|
|
|
|
|
glue(glue(st, SUFFIX), _p)((uint8_t *)haddr, val);
|
|
|
|
|
#else
|
|
|
|
|
glue(glue(st, SUFFIX), _le_p)((uint8_t *)haddr, val);
|
2005-12-05 22:57:57 +03:00
|
|
|
#endif
|
2013-09-04 22:45:20 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#if DATA_SIZE > 1
|
|
|
|
|
void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
|
2015-05-13 19:10:33 +03:00
|
|
|
TCGMemOpIdx oi, uintptr_t retaddr)
|
2013-09-04 22:45:20 +04:00
|
|
|
{
|
2015-05-13 19:10:33 +03:00
|
|
|
unsigned mmu_idx = get_mmuidx(oi);
|
2013-09-04 22:45:20 +04:00
|
|
|
int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
|
|
|
|
target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
|
2016-07-14 22:43:06 +03:00
|
|
|
unsigned a_bits = get_alignment_bits(get_memop(oi));
|
2013-09-04 22:45:20 +04:00
|
|
|
uintptr_t haddr;
|
|
|
|
|
|
2016-07-14 22:43:06 +03:00
|
|
|
if (addr & ((1 << a_bits) - 1)) {
|
2016-06-23 21:16:46 +03:00
|
|
|
cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
|
|
|
|
|
mmu_idx, retaddr);
|
|
|
|
|
}
|
|
|
|
|
|
2013-09-04 22:45:20 +04:00
|
|
|
/* If the TLB entry is for a different page, reload and try again. */
|
|
|
|
|
if ((addr & TARGET_PAGE_MASK)
|
|
|
|
|
!= (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
|
2016-07-06 21:26:52 +03:00
|
|
|
if (!VICTIM_TLB_HIT(addr_write, addr)) {
|
2014-07-07 14:23:56 +04:00
|
|
|
tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
|
implementing victim TLB for QEMU system emulated TLB
QEMU system mode page table walks are expensive. Taken by running QEMU
qemu-system-x86_64 system mode on Intel PIN , a TLB miss and walking a
4-level page tables in guest Linux OS takes ~450 X86 instructions on
average.
QEMU system mode TLB is implemented using a directly-mapped hashtable.
This structure suffers from conflict misses. Increasing the
associativity of the TLB may not be the solution to conflict misses as
all the ways may have to be walked in serial.
A victim TLB is a TLB used to hold translations evicted from the
primary TLB upon replacement. The victim TLB lies between the main TLB
and its refill path. Victim TLB is of greater associativity (fully
associative in this patch). It takes longer to lookup the victim TLB,
but its likely better than a full page table walk. The memory
translation path is changed as follows :
Before Victim TLB:
1. Inline TLB lookup
2. Exit code cache on TLB miss.
3. Check for unaligned, IO accesses
4. TLB refill.
5. Do the memory access.
6. Return to code cache.
After Victim TLB:
1. Inline TLB lookup
2. Exit code cache on TLB miss.
3. Check for unaligned, IO accesses
4. Victim TLB lookup.
5. If victim TLB misses, TLB refill
6. Do the memory access.
7. Return to code cache
The advantage is that victim TLB can offer more associativity to a
directly mapped TLB and thus potentially fewer page table walks while
still keeping the time taken to flush within reasonable limits.
However, placing a victim TLB before the refill path increase TLB
refill path as the victim TLB is consulted before the TLB refill. The
performance results demonstrate that the pros outweigh the cons.
some performance results taken on SPECINT2006 train
datasets and kernel boot and qemu configure script on an
Intel(R) Xeon(R) CPU E5620 @ 2.40GHz Linux machine are shown in the
Google Doc link below.
https://docs.google.com/spreadsheets/d/1eiItzekZwNQOal_h-5iJmC4tMDi051m9qidi5_nwvH4/edit?usp=sharing
In summary, victim TLB improves the performance of qemu-system-x86_64 by
11% on average on SPECINT2006, kernelboot and qemu configscript and with
highest improvement of in 26% in 456.hmmer. And victim TLB does not result
in any performance degradation in any of the measured benchmarks. Furthermore,
the implemented victim TLB is architecture independent and is expected to
benefit other architectures in QEMU as well.
Although there are measurement fluctuations, the performance
improvement is very significant and by no means in the range of
noises.
Signed-off-by: Xin Tong <trent.tong@gmail.com>
Message-id: 1407202523-23553-1-git-send-email-trent.tong@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-05 05:35:23 +04:00
|
|
|
}
|
2013-09-04 22:45:20 +04:00
|
|
|
tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Handle an IO access. */
|
|
|
|
|
if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
|
|
|
|
|
if ((addr & (DATA_SIZE - 1)) != 0) {
|
|
|
|
|
goto do_unaligned_access;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* ??? Note that the io helpers always read data in the target
|
|
|
|
|
byte ordering. We should push the LE/BE request down into io. */
|
|
|
|
|
val = TGT_BE(val);
|
2016-07-09 04:51:28 +03:00
|
|
|
glue(io_write, SUFFIX)(env, mmu_idx, index, val, addr, retaddr);
|
2013-09-04 22:45:20 +04:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Handle slow unaligned access (it spans two pages or IO). */
|
|
|
|
|
if (DATA_SIZE > 1
|
|
|
|
|
&& unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
|
|
|
|
|
>= TARGET_PAGE_SIZE)) {
|
cputlb: Fix for self-modifying writes across page boundaries
As it currently stands, QEMU does not properly handle self-modifying code
when the write is unaligned and crosses a page boundary. The procedure
for handling a write to the current translation block is to write-protect
the current translation block, catch the write, split up the translation
block into the current instruction (which remains write-protected so that
the current instruction is not modified) and the remaining instructions
in the translation block, and then restore the CPU state to before the
write occurred so the write will be retried and successfully executed.
However, since unaligned writes across pages are split into one-byte
writes for simplicity, writes to the second page (which is not the
current TB) may succeed before a write to the current TB is attempted,
and since these writes are not invalidated before resuming state after
splitting the TB, these writes will be performed a second time, thus
corrupting the second page. Credit goes to Patrick Hulin for
discovering this.
In recent 64-bit versions of Windows running in emulated mode, this
results in either being very unstable (a BSOD after a couple minutes of
uptime), or being entirely unable to boot. Windows performs one or more
8-byte unaligned self-modifying writes (xors) which intersect the end
of the current TB and the beginning of the next TB, which runs into the
aforementioned issue. This commit fixes that issue by making the
unaligned write loop perform the writes in forwards order, instead of
reverse order. This way, QEMU immediately tries to write to the current
TB, and splits the TB before any write to the second page is executed.
The write then proceeds as intended. With this patch applied, I am able
to boot and use Windows 7 64-bit and Windows 10 64-bit in QEMU without
KVM.
Per Richard Henderson's input, this patch also ensures the second page
is in the TLB before executing the write loop, to ensure the second
page is mapped.
The original discussion of the issue is located at
http://lists.nongnu.org/archive/html/qemu-devel/2014-08/msg02161.html.
Signed-off-by: Samuel Damashek <samuel.damashek@invincea.com>
Message-Id: <20160706182652.16190-1-samuel.damashek@invincea.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-07-08 22:54:34 +03:00
|
|
|
int i, index2;
|
|
|
|
|
target_ulong page2, tlb_addr2;
|
2013-09-04 22:45:20 +04:00
|
|
|
do_unaligned_access:
|
cputlb: Fix for self-modifying writes across page boundaries
As it currently stands, QEMU does not properly handle self-modifying code
when the write is unaligned and crosses a page boundary. The procedure
for handling a write to the current translation block is to write-protect
the current translation block, catch the write, split up the translation
block into the current instruction (which remains write-protected so that
the current instruction is not modified) and the remaining instructions
in the translation block, and then restore the CPU state to before the
write occurred so the write will be retried and successfully executed.
However, since unaligned writes across pages are split into one-byte
writes for simplicity, writes to the second page (which is not the
current TB) may succeed before a write to the current TB is attempted,
and since these writes are not invalidated before resuming state after
splitting the TB, these writes will be performed a second time, thus
corrupting the second page. Credit goes to Patrick Hulin for
discovering this.
In recent 64-bit versions of Windows running in emulated mode, this
results in either being very unstable (a BSOD after a couple minutes of
uptime), or being entirely unable to boot. Windows performs one or more
8-byte unaligned self-modifying writes (xors) which intersect the end
of the current TB and the beginning of the next TB, which runs into the
aforementioned issue. This commit fixes that issue by making the
unaligned write loop perform the writes in forwards order, instead of
reverse order. This way, QEMU immediately tries to write to the current
TB, and splits the TB before any write to the second page is executed.
The write then proceeds as intended. With this patch applied, I am able
to boot and use Windows 7 64-bit and Windows 10 64-bit in QEMU without
KVM.
Per Richard Henderson's input, this patch also ensures the second page
is in the TLB before executing the write loop, to ensure the second
page is mapped.
The original discussion of the issue is located at
http://lists.nongnu.org/archive/html/qemu-devel/2014-08/msg02161.html.
Signed-off-by: Samuel Damashek <samuel.damashek@invincea.com>
Message-Id: <20160706182652.16190-1-samuel.damashek@invincea.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-07-08 22:54:34 +03:00
|
|
|
/* Ensure the second page is in the TLB. Note that the first page
|
|
|
|
|
is already guaranteed to be filled, and that the second page
|
|
|
|
|
cannot evict the first. */
|
|
|
|
|
page2 = (addr + DATA_SIZE) & TARGET_PAGE_MASK;
|
|
|
|
|
index2 = (page2 >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
|
|
|
|
tlb_addr2 = env->tlb_table[mmu_idx][index2].addr_write;
|
|
|
|
|
if (page2 != (tlb_addr2 & (TARGET_PAGE_MASK | TLB_INVALID_MASK))
|
|
|
|
|
&& !VICTIM_TLB_HIT(addr_write, page2)) {
|
|
|
|
|
tlb_fill(ENV_GET_CPU(env), page2, MMU_DATA_STORE,
|
|
|
|
|
mmu_idx, retaddr);
|
|
|
|
|
}
|
|
|
|
|
|
2013-09-04 22:45:20 +04:00
|
|
|
/* XXX: not efficient, but simple */
|
cputlb: Fix for self-modifying writes across page boundaries
As it currently stands, QEMU does not properly handle self-modifying code
when the write is unaligned and crosses a page boundary. The procedure
for handling a write to the current translation block is to write-protect
the current translation block, catch the write, split up the translation
block into the current instruction (which remains write-protected so that
the current instruction is not modified) and the remaining instructions
in the translation block, and then restore the CPU state to before the
write occurred so the write will be retried and successfully executed.
However, since unaligned writes across pages are split into one-byte
writes for simplicity, writes to the second page (which is not the
current TB) may succeed before a write to the current TB is attempted,
and since these writes are not invalidated before resuming state after
splitting the TB, these writes will be performed a second time, thus
corrupting the second page. Credit goes to Patrick Hulin for
discovering this.
In recent 64-bit versions of Windows running in emulated mode, this
results in either being very unstable (a BSOD after a couple minutes of
uptime), or being entirely unable to boot. Windows performs one or more
8-byte unaligned self-modifying writes (xors) which intersect the end
of the current TB and the beginning of the next TB, which runs into the
aforementioned issue. This commit fixes that issue by making the
unaligned write loop perform the writes in forwards order, instead of
reverse order. This way, QEMU immediately tries to write to the current
TB, and splits the TB before any write to the second page is executed.
The write then proceeds as intended. With this patch applied, I am able
to boot and use Windows 7 64-bit and Windows 10 64-bit in QEMU without
KVM.
Per Richard Henderson's input, this patch also ensures the second page
is in the TLB before executing the write loop, to ensure the second
page is mapped.
The original discussion of the issue is located at
http://lists.nongnu.org/archive/html/qemu-devel/2014-08/msg02161.html.
Signed-off-by: Samuel Damashek <samuel.damashek@invincea.com>
Message-Id: <20160706182652.16190-1-samuel.damashek@invincea.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-07-08 22:54:34 +03:00
|
|
|
/* This loop must go in the forward direction to avoid issues
|
|
|
|
|
with self-modifying code. */
|
|
|
|
|
for (i = 0; i < DATA_SIZE; ++i) {
|
2013-09-04 22:45:20 +04:00
|
|
|
/* Big-endian extract. */
|
|
|
|
|
uint8_t val8 = val >> (((DATA_SIZE - 1) * 8) - (i * 8));
|
2013-07-26 22:29:15 +04:00
|
|
|
glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8,
|
2016-07-26 03:39:16 +03:00
|
|
|
oi, retaddr);
|
2003-08-09 03:58:05 +04:00
|
|
|
}
|
2013-07-26 22:29:15 +04:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
haddr = addr + env->tlb_table[mmu_idx][index].addend;
|
2013-09-04 22:45:20 +04:00
|
|
|
glue(glue(st, SUFFIX), _be_p)((uint8_t *)haddr, val);
|
2003-08-09 03:58:05 +04:00
|
|
|
}
|
2013-09-04 22:45:20 +04:00
|
|
|
#endif /* DATA_SIZE > 1 */
|
2004-10-03 19:07:13 +04:00
|
|
|
#endif /* !defined(SOFTMMU_CODE_ACCESS) */
|
|
|
|
|
|
|
|
|
|
#undef READ_ACCESS_TYPE
|
2003-08-09 03:58:05 +04:00
|
|
|
#undef DATA_TYPE
|
|
|
|
|
#undef SUFFIX
|
2013-08-27 22:31:48 +04:00
|
|
|
#undef LSUFFIX
|
2003-08-09 03:58:05 +04:00
|
|
|
#undef DATA_SIZE
|
2005-11-29 00:19:04 +03:00
|
|
|
#undef ADDR_READ
|
2013-08-28 01:09:14 +04:00
|
|
|
#undef WORD_TYPE
|
|
|
|
|
#undef SDATA_TYPE
|
|
|
|
|
#undef USUFFIX
|
|
|
|
|
#undef SSUFFIX
|
2013-09-04 22:45:20 +04:00
|
|
|
#undef BSWAP
|
|
|
|
|
#undef helper_le_ld_name
|
|
|
|
|
#undef helper_be_ld_name
|
|
|
|
|
#undef helper_le_lds_name
|
|
|
|
|
#undef helper_be_lds_name
|
|
|
|
|
#undef helper_le_st_name
|
|
|
|
|
#undef helper_be_st_name
|