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qemu/tcg/ppc/tcg-target-con-set.h

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tcg/ppc: Split out constraint sets to tcg-target-con-set.h Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-10-17 19:35:21 +03:00
/* SPDX-License-Identifier: MIT */
/*
* Define PowerPC target-specific constraint sets.
* Copyright (c) 2021 Linaro
*/
/*
* C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
* Each operand should be a sequence of constraint letters as defined by
* tcg-target-con-str.h; the constraint combination is inclusive or.
*/
C_O0_I1(r)
C_O0_I2(r, r)
C_O0_I2(r, ri)
C_O0_I2(v, r)
tcg/ppc: Adjust constraints on qemu_ld/st The softmmu tlb uses TCG_REG_{TMP1,TMP2,R0}, not any of the normally available registers. Now that we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-04-04 03:04:49 +03:00
C_O0_I3(r, r, r)
tcg/ppc: Support 128-bit load/store Use LQ/STQ with ISA v2.07, and 16-byte atomicity is required. Note that these instructions do not require 16-byte alignment. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-04-19 16:13:22 +03:00
C_O0_I3(o, m, r)
tcg/ppc: Split out constraint sets to tcg-target-con-set.h Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-10-17 19:35:21 +03:00
C_O0_I4(r, r, ri, ri)
tcg/ppc: Adjust constraints on qemu_ld/st The softmmu tlb uses TCG_REG_{TMP1,TMP2,R0}, not any of the normally available registers. Now that we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-04-04 03:04:49 +03:00
C_O0_I4(r, r, r, r)
tcg/ppc: Split out constraint sets to tcg-target-con-set.h Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-10-17 19:35:21 +03:00
C_O1_I1(r, r)
C_O1_I1(v, r)
C_O1_I1(v, v)
C_O1_I1(v, vr)
C_O1_I2(r, 0, rZ)
C_O1_I2(r, rI, ri)
C_O1_I2(r, rI, rT)
C_O1_I2(r, r, r)
C_O1_I2(r, r, ri)
C_O1_I2(r, r, rI)
C_O1_I2(r, r, rT)
C_O1_I2(r, r, rU)
C_O1_I2(r, r, rZW)
C_O1_I2(v, v, v)
C_O1_I3(v, v, v, v)
C_O1_I4(r, r, ri, rZ, rZ)
C_O1_I4(r, r, r, ri, ri)
tcg/ppc: Adjust constraints on qemu_ld/st The softmmu tlb uses TCG_REG_{TMP1,TMP2,R0}, not any of the normally available registers. Now that we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-04-04 03:04:49 +03:00
C_O2_I1(r, r, r)
tcg/ppc: Support 128-bit load/store Use LQ/STQ with ISA v2.07, and 16-byte atomicity is required. Note that these instructions do not require 16-byte alignment. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-04-19 16:13:22 +03:00
C_O2_I1(o, m, r)
tcg/ppc: Adjust constraints on qemu_ld/st The softmmu tlb uses TCG_REG_{TMP1,TMP2,R0}, not any of the normally available registers. Now that we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-04-04 03:04:49 +03:00
C_O2_I2(r, r, r, r)
tcg/ppc: Split out constraint sets to tcg-target-con-set.h Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-10-17 19:35:21 +03:00
C_O2_I4(r, r, rI, rZM, r, r)
C_O2_I4(r, r, r, r, rI, rZM)
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