224 lines
5.3 KiB
ArmAsm
224 lines
5.3 KiB
ArmAsm
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.include "macros.inc"
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#define debug_level 6
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#define debug_vector level6
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test_suite break
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test break
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set_vector debug_vector, 0
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rsil a2, debug_level
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_break 0, 0
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set_vector debug_vector, 2f
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rsil a2, debug_level - 1
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1:
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_break 0, 0
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test_fail
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2:
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rsr a2, ps
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movi a3, 0x1f
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and a2, a2, a3
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movi a3, 0x10 | debug_level
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assert eq, a2, a3
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rsr a2, epc6
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movi a3, 1b
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assert eq, a2, a3
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rsr a2, debugcause
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movi a3, 0x8
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assert eq, a2, a3
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test_end
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test breakn
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set_vector debug_vector, 0
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rsil a2, debug_level
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_break.n 0
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set_vector debug_vector, 2f
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rsil a2, debug_level - 1
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1:
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_break.n 0
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test_fail
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2:
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rsr a2, ps
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movi a3, 0x1f
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and a2, a2, a3
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movi a3, 0x10 | debug_level
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assert eq, a2, a3
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rsr a2, epc6
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movi a3, 1b
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assert eq, a2, a3
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rsr a2, debugcause
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movi a3, 0x10
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assert eq, a2, a3
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test_end
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test ibreak
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set_vector debug_vector, 0
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rsil a2, debug_level
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movi a2, 1f
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wsr a2, ibreaka0
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movi a2, 1
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wsr a2, ibreakenable
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isync
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1:
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rsil a2, debug_level - 1
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movi a2, 1f
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wsr a2, ibreaka0
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movi a2, 0
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wsr a2, ibreakenable
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isync
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1:
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set_vector debug_vector, 2f
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movi a2, 1f
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wsr a2, ibreaka0
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movi a2, 1
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wsr a2, ibreakenable
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isync
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1:
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test_fail
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2:
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rsr a2, ps
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movi a3, 0x1f
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and a2, a2, a3
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movi a3, 0x10 | debug_level
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assert eq, a2, a3
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rsr a2, epc6
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movi a3, 1b
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assert eq, a2, a3
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rsr a2, debugcause
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movi a3, 0x2
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assert eq, a2, a3
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test_end
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test ibreak_priority
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set_vector debug_vector, 2f
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rsil a2, debug_level - 1
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movi a2, 1f
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wsr a2, ibreaka0
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movi a2, 1
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wsr a2, ibreakenable
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isync
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1:
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break 0, 0
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test_fail
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2:
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rsr a2, debugcause
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movi a3, 0x2
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assert eq, a2, a3
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test_end
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test icount
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set_vector debug_vector, 2f
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rsil a2, debug_level - 1
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movi a2, -2
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wsr a2, icount
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movi a2, 1
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wsr a2, icountlevel
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isync
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rsil a2, 0
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nop
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1:
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break 0, 0
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test_fail
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2:
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movi a2, 0
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wsr a2, icountlevel
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rsr a2, epc6
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movi a3, 1b
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assert eq, a2, a3
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rsr a2, debugcause
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movi a3, 0x1
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assert eq, a2, a3
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test_end
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.macro check_dbreak dr
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rsr a2, epc6
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movi a3, 1b
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assert eq, a2, a3
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rsr a2, debugcause
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movi a3, 0x4 | (\dr << 8)
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assert eq, a2, a3
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movi a2, 0
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wsr a2, dbreakc\dr
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.endm
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.macro dbreak_test dr, ctl, break, access, op
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set_vector debug_vector, 2f
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rsil a2, debug_level - 1
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movi a2, \ctl
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wsr a2, dbreakc\dr
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movi a2, \break
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wsr a2, dbreaka\dr
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movi a2, \access
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isync
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1:
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\op a3, a2, 0
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test_fail
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2:
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check_dbreak \dr
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reset_ps
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.endm
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test dbreak_exact
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dbreak_test 0, 0x4000003f, 0xd000007f, 0xd000007f, l8ui
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dbreak_test 1, 0x4000003e, 0xd000007e, 0xd000007e, l16ui
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dbreak_test 0, 0x4000003c, 0xd000007c, 0xd000007c, l32i
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dbreak_test 1, 0x8000003f, 0xd000007f, 0xd000007f, s8i
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dbreak_test 0, 0x8000003e, 0xd000007e, 0xd000007e, s16i
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dbreak_test 1, 0x8000003c, 0xd000007c, 0xd000007c, s32i
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test_end
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test dbreak_overlap
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dbreak_test 0, 0x4000003f, 0xd000007d, 0xd000007c, l16ui
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dbreak_test 1, 0x4000003f, 0xd000007d, 0xd000007c, l32i
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dbreak_test 0, 0x4000003e, 0xd000007e, 0xd000007f, l8ui
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dbreak_test 1, 0x4000003e, 0xd000007e, 0xd000007c, l32i
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dbreak_test 0, 0x4000003c, 0xd000007c, 0xd000007d, l8ui
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dbreak_test 1, 0x4000003c, 0xd000007c, 0xd000007c, l16ui
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dbreak_test 0, 0x40000038, 0xd0000078, 0xd000007b, l8ui
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dbreak_test 1, 0x40000038, 0xd0000078, 0xd000007a, l16ui
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dbreak_test 0, 0x40000038, 0xd0000078, 0xd000007c, l32i
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dbreak_test 1, 0x40000030, 0xd0000070, 0xd0000075, l8ui
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dbreak_test 0, 0x40000030, 0xd0000070, 0xd0000076, l16ui
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dbreak_test 1, 0x40000030, 0xd0000070, 0xd0000078, l32i
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dbreak_test 0, 0x40000020, 0xd0000060, 0xd000006f, l8ui
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dbreak_test 1, 0x40000020, 0xd0000060, 0xd0000070, l16ui
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dbreak_test 0, 0x40000020, 0xd0000060, 0xd0000074, l32i
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dbreak_test 0, 0x8000003f, 0xd000007d, 0xd000007c, s16i
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dbreak_test 1, 0x8000003f, 0xd000007d, 0xd000007c, s32i
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dbreak_test 0, 0x8000003e, 0xd000007e, 0xd000007f, s8i
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dbreak_test 1, 0x8000003e, 0xd000007e, 0xd000007c, s32i
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dbreak_test 0, 0x8000003c, 0xd000007c, 0xd000007d, s8i
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dbreak_test 1, 0x8000003c, 0xd000007c, 0xd000007c, s16i
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dbreak_test 0, 0x80000038, 0xd0000078, 0xd000007b, s8i
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dbreak_test 1, 0x80000038, 0xd0000078, 0xd000007a, s16i
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dbreak_test 0, 0x80000038, 0xd0000078, 0xd000007c, s32i
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dbreak_test 1, 0x80000030, 0xd0000070, 0xd0000075, s8i
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dbreak_test 0, 0x80000030, 0xd0000070, 0xd0000076, s16i
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dbreak_test 1, 0x80000030, 0xd0000070, 0xd0000078, s32i
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dbreak_test 0, 0x80000020, 0xd0000060, 0xd000006f, s8i
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dbreak_test 1, 0x80000020, 0xd0000060, 0xd0000070, s16i
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dbreak_test 0, 0x80000020, 0xd0000060, 0xd0000074, s32i
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test_end
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test dbreak_invalid
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dbreak_test 0, 0x40000030, 0xd0000071, 0xd0000070, l16ui
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dbreak_test 1, 0x40000035, 0xd0000072, 0xd0000070, l32i
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test_end
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test_suite_end
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