2016-07-27 09:56:23 +03:00
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#define GEN_VR_LDX(name, opc2, opc3) \
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GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
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#define GEN_VR_STX(name, opc2, opc3) \
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GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
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#define GEN_VR_LVE(name, opc2, opc3) \
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GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
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#define GEN_VR_STVE(name, opc2, opc3) \
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GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
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GEN_VR_LDX(lvx, 0x07, 0x03),
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GEN_VR_LDX(lvxl, 0x07, 0x0B),
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GEN_VR_LVE(bx, 0x07, 0x00),
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GEN_VR_LVE(hx, 0x07, 0x01),
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GEN_VR_LVE(wx, 0x07, 0x02),
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GEN_VR_STX(svx, 0x07, 0x07),
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GEN_VR_STX(svxl, 0x07, 0x0F),
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GEN_VR_STVE(bx, 0x07, 0x04),
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GEN_VR_STVE(hx, 0x07, 0x05),
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GEN_VR_STVE(wx, 0x07, 0x06),
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#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
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GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
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#define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
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GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
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GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
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GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
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GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
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GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
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GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
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GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26),
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GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22),
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GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21),
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#define GEN_VXFORM(name, opc2, opc3) \
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GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
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#define GEN_VXFORM_207(name, opc2, opc3) \
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GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
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2016-07-28 21:14:16 +03:00
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#define GEN_VXFORM_300(name, opc2, opc3) \
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GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA300)
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2016-09-06 08:04:06 +03:00
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#define GEN_VXFORM_300_EXT(name, opc2, opc3, inval) \
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GEN_HANDLER_E(name, 0x04, opc2, opc3, inval, PPC_NONE, PPC2_ISA300)
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2016-09-06 08:04:08 +03:00
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#define GEN_VXFORM_300_EO(name, opc2, opc3, opc4) \
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GEN_HANDLER_E_2(name, 0x04, opc2, opc3, opc4, 0x00000000, PPC_NONE, \
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PPC2_ISA300)
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2020-07-02 02:43:40 +03:00
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#define GEN_VXFORM_310(name, opc2, opc3) \
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GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA310)
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2016-07-27 09:56:23 +03:00
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#define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
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GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
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#define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
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GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
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GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
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2016-10-24 12:14:58 +03:00
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GEN_VXFORM_DUAL(vaddubm, vmul10cuq, 0, 0, PPC_ALTIVEC, PPC_NONE),
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GEN_VXFORM_DUAL(vadduhm, vmul10ecuq, 0, 1, PPC_ALTIVEC, PPC_NONE),
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2016-07-27 09:56:23 +03:00
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GEN_VXFORM(vadduwm, 0, 2),
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GEN_VXFORM_207(vaddudm, 0, 3),
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GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
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GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
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2017-01-10 05:10:11 +03:00
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GEN_VXFORM_DUAL(vsubuwm, bcdus, 0, 18, PPC_ALTIVEC, PPC2_ISA300),
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2017-01-10 05:10:10 +03:00
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GEN_VXFORM_DUAL(vsubudm, bcds, 0, 19, PPC2_ALTIVEC_207, PPC2_ISA300),
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GEN_VXFORM_300(bcds, 0, 27),
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2016-07-27 09:56:23 +03:00
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GEN_VXFORM(vmaxub, 1, 0),
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GEN_VXFORM(vmaxuh, 1, 1),
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GEN_VXFORM(vmaxuw, 1, 2),
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GEN_VXFORM_207(vmaxud, 1, 3),
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GEN_VXFORM(vmaxsb, 1, 4),
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GEN_VXFORM(vmaxsh, 1, 5),
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GEN_VXFORM(vmaxsw, 1, 6),
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GEN_VXFORM_207(vmaxsd, 1, 7),
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GEN_VXFORM(vminub, 1, 8),
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GEN_VXFORM(vminuh, 1, 9),
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GEN_VXFORM(vminuw, 1, 10),
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GEN_VXFORM_207(vminud, 1, 11),
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GEN_VXFORM(vminsb, 1, 12),
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GEN_VXFORM(vminsh, 1, 13),
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GEN_VXFORM(vminsw, 1, 14),
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GEN_VXFORM_207(vminsd, 1, 15),
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2016-07-28 21:14:14 +03:00
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GEN_VXFORM_DUAL(vavgub, vabsdub, 1, 16, PPC_ALTIVEC, PPC_NONE),
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GEN_VXFORM_DUAL(vavguh, vabsduh, 1, 17, PPC_ALTIVEC, PPC_NONE),
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GEN_VXFORM_DUAL(vavguw, vabsduw, 1, 18, PPC_ALTIVEC, PPC_NONE),
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2016-07-27 09:56:23 +03:00
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GEN_VXFORM(vavgsb, 1, 20),
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GEN_VXFORM(vavgsh, 1, 21),
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GEN_VXFORM(vavgsw, 1, 22),
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GEN_VXFORM(vmrghb, 6, 0),
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GEN_VXFORM(vmrghh, 6, 1),
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GEN_VXFORM(vmrghw, 6, 2),
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GEN_VXFORM(vmrglb, 6, 4),
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GEN_VXFORM(vmrglh, 6, 5),
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GEN_VXFORM(vmrglw, 6, 6),
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2016-11-28 10:56:42 +03:00
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GEN_VXFORM_300(vextublx, 6, 24),
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GEN_VXFORM_300(vextuhlx, 6, 25),
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GEN_VXFORM_DUAL(vmrgow, vextuwlx, 6, 26, PPC_NONE, PPC2_ALTIVEC_207),
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GEN_VXFORM_300(vextubrx, 6, 28),
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GEN_VXFORM_300(vextuhrx, 6, 29),
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GEN_VXFORM_DUAL(vmrgew, vextuwrx, 6, 30, PPC_NONE, PPC2_ALTIVEC_207),
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target/ppc: moved vector even and odd multiplication to decodetree
Moved the instructions vmulesb, vmulosb, vmuleub, vmuloub,
vmulesh, vmulosh, vmuleuh, vmulouh, vmulesw, vmulosw,
muleuw and vmulouw from legacy to decodetree. Implemented
the instructions vmulesd, vmulosd, vmuleud, vmuloud.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-3-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02 08:51:36 +03:00
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GEN_VXFORM_207(vmuluwm, 4, 2),
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2016-07-28 21:14:17 +03:00
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GEN_VXFORM_300(vsrv, 2, 28),
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2016-07-28 21:14:16 +03:00
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GEN_VXFORM_300(vslv, 2, 29),
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2016-07-27 09:56:23 +03:00
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GEN_VXFORM(vslo, 6, 16),
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GEN_VXFORM(vsro, 6, 17),
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GEN_VXFORM(vaddcuw, 0, 6),
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2016-10-30 06:14:58 +03:00
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GEN_HANDLER_E_2(vprtybw, 0x4, 0x1, 0x18, 8, 0, PPC_NONE, PPC2_ISA300),
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GEN_HANDLER_E_2(vprtybd, 0x4, 0x1, 0x18, 9, 0, PPC_NONE, PPC2_ISA300),
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GEN_HANDLER_E_2(vprtybq, 0x4, 0x1, 0x18, 10, 0, PPC_NONE, PPC2_ISA300),
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2016-11-08 19:50:22 +03:00
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GEN_VXFORM_DUAL(vsubcuw, xpnd04_1, 0, 22, PPC_ALTIVEC, PPC_NONE),
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2017-01-10 05:10:12 +03:00
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GEN_VXFORM_300(bcdsr, 0, 23),
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GEN_VXFORM_300(bcdsr, 0, 31),
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2016-10-24 12:14:58 +03:00
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GEN_VXFORM_DUAL(vaddubs, vmul10uq, 0, 8, PPC_ALTIVEC, PPC_NONE),
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GEN_VXFORM_DUAL(vadduhs, vmul10euq, 0, 9, PPC_ALTIVEC, PPC_NONE),
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2016-07-27 09:56:23 +03:00
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GEN_VXFORM(vadduws, 0, 10),
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GEN_VXFORM(vaddsbs, 0, 12),
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2016-11-25 06:53:32 +03:00
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GEN_VXFORM_DUAL(vaddshs, bcdcpsgn, 0, 13, PPC_ALTIVEC, PPC_NONE),
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2016-07-27 09:56:23 +03:00
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GEN_VXFORM(vaddsws, 0, 14),
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GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
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GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
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GEN_VXFORM(vsubuws, 0, 26),
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2018-12-07 20:13:14 +03:00
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GEN_VXFORM_DUAL(vsubsbs, bcdtrunc, 0, 28, PPC_ALTIVEC, PPC2_ISA300),
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2016-07-27 09:56:23 +03:00
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GEN_VXFORM(vsubshs, 0, 29),
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2016-11-08 19:50:22 +03:00
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GEN_VXFORM_DUAL(vsubsws, xpnd04_2, 0, 30, PPC_ALTIVEC, PPC_NONE),
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2016-07-27 09:56:23 +03:00
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GEN_VXFORM_207(vadduqm, 0, 4),
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GEN_VXFORM_207(vaddcuq, 0, 5),
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GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
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2017-01-12 23:08:32 +03:00
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GEN_VXFORM_DUAL(vsubuqm, bcdtrunc, 0, 20, PPC2_ALTIVEC_207, PPC2_ISA300),
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2017-01-12 23:08:33 +03:00
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GEN_VXFORM_DUAL(vsubcuq, bcdutrunc, 0, 21, PPC2_ALTIVEC_207, PPC2_ISA300),
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2016-07-27 09:56:23 +03:00
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GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
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2022-03-02 08:51:37 +03:00
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GEN_VXFORM(vsl, 2, 7),
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2016-07-27 09:56:23 +03:00
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GEN_VXFORM(vsr, 2, 11),
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GEN_VXFORM(vpkuhum, 7, 0),
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GEN_VXFORM(vpkuwum, 7, 1),
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GEN_VXFORM_207(vpkudum, 7, 17),
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GEN_VXFORM(vpkuhus, 7, 2),
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GEN_VXFORM(vpkuwus, 7, 3),
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GEN_VXFORM_207(vpkudus, 7, 19),
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GEN_VXFORM(vpkshus, 7, 4),
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GEN_VXFORM(vpkswus, 7, 5),
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GEN_VXFORM_207(vpksdus, 7, 21),
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GEN_VXFORM(vpkshss, 7, 6),
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GEN_VXFORM(vpkswss, 7, 7),
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GEN_VXFORM_207(vpksdss, 7, 23),
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GEN_VXFORM(vpkpx, 7, 12),
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GEN_VXFORM(vsum4ubs, 4, 24),
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GEN_VXFORM(vsum4sbs, 4, 28),
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GEN_VXFORM(vsum4shs, 4, 25),
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GEN_VXFORM(vsum2sws, 4, 26),
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GEN_VXFORM(vsumsws, 4, 30),
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GEN_VXFORM(vaddfp, 5, 0),
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GEN_VXFORM(vsubfp, 5, 1),
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GEN_VXFORM(vmaxfp, 5, 16),
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GEN_VXFORM(vminfp, 5, 17),
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#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
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GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
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2016-07-28 21:14:15 +03:00
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#define GEN_VXRFORM1_300(opname, name, str, opc2, opc3) \
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GEN_HANDLER2_E(name, str, 0x4, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA300),
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2016-07-27 09:56:23 +03:00
|
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#define GEN_VXRFORM(name, opc2, opc3) \
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GEN_VXRFORM1(name, name, #name, opc2, opc3) \
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GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
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2016-07-28 21:14:15 +03:00
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#define GEN_VXRFORM_300(name, opc2, opc3) \
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GEN_VXRFORM1_300(name, name, #name, opc2, opc3) \
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GEN_VXRFORM1_300(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
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2022-03-02 08:51:37 +03:00
|
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GEN_VXRFORM(vcmpeqfp, 3, 3)
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2016-07-27 09:56:23 +03:00
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GEN_VXRFORM(vcmpgefp, 3, 7)
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2022-03-02 08:51:37 +03:00
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GEN_VXRFORM(vcmpgtfp, 3, 11)
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GEN_VXRFORM(vcmpbfp, 3, 15)
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2016-07-27 09:56:23 +03:00
|
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2016-09-06 08:04:06 +03:00
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#define GEN_VXFORM_DUAL_INV(name0, name1, opc2, opc3, inval0, inval1, type) \
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GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, \
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PPC_NONE)
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2016-09-06 08:04:07 +03:00
|
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GEN_VXFORM_DUAL_INV(vspltb, vextractub, 6, 8, 0x00000000, 0x100000,
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2016-09-29 13:22:37 +03:00
|
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PPC_ALTIVEC),
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2016-09-06 08:04:07 +03:00
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GEN_VXFORM_DUAL_INV(vsplth, vextractuh, 6, 9, 0x00000000, 0x100000,
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2016-09-29 13:22:37 +03:00
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PPC_ALTIVEC),
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2016-09-06 08:04:07 +03:00
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GEN_VXFORM_DUAL_INV(vspltw, vextractuw, 6, 10, 0x00000000, 0x100000,
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2016-09-29 13:22:37 +03:00
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PPC_ALTIVEC),
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2016-09-06 08:04:07 +03:00
|
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GEN_VXFORM_300_EXT(vextractd, 6, 11, 0x100000),
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2021-11-04 15:37:02 +03:00
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GEN_VXFORM(vspltisb, 6, 12),
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GEN_VXFORM(vspltish, 6, 13),
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GEN_VXFORM(vspltisw, 6, 14),
|
2016-10-19 09:06:46 +03:00
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GEN_VXFORM_300_EO(vnegw, 0x01, 0x18, 0x06),
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GEN_VXFORM_300_EO(vnegd, 0x01, 0x18, 0x07),
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2016-09-06 08:04:08 +03:00
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GEN_VXFORM_300_EO(vctzb, 0x01, 0x18, 0x1C),
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GEN_VXFORM_300_EO(vctzh, 0x01, 0x18, 0x1D),
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GEN_VXFORM_300_EO(vctzw, 0x01, 0x18, 0x1E),
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GEN_VXFORM_300_EO(vctzd, 0x01, 0x18, 0x1F),
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2016-09-28 08:45:18 +03:00
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GEN_VXFORM_300_EO(vclzlsbb, 0x01, 0x18, 0x0),
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GEN_VXFORM_300_EO(vctzlsbb, 0x01, 0x18, 0x1),
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2016-07-27 09:56:23 +03:00
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#define GEN_VXFORM_NOA(name, opc2, opc3) \
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GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
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GEN_VXFORM_NOA(vupkhsb, 7, 8),
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GEN_VXFORM_NOA(vupkhsh, 7, 9),
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GEN_VXFORM_207(vupkhsw, 7, 25),
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GEN_VXFORM_NOA(vupklsb, 7, 10),
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GEN_VXFORM_NOA(vupklsh, 7, 11),
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GEN_VXFORM_207(vupklsw, 7, 27),
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GEN_VXFORM_NOA(vupkhpx, 7, 13),
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GEN_VXFORM_NOA(vupklpx, 7, 15),
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GEN_VXFORM_NOA(vrefp, 5, 4),
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GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
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GEN_VXFORM_NOA(vexptefp, 5, 6),
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GEN_VXFORM_NOA(vlogefp, 5, 7),
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GEN_VXFORM_NOA(vrfim, 5, 11),
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GEN_VXFORM_NOA(vrfin, 5, 8),
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GEN_VXFORM_NOA(vrfip, 5, 10),
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GEN_VXFORM_NOA(vrfiz, 5, 9),
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#define GEN_VXFORM_UIMM(name, opc2, opc3) \
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GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
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GEN_VXFORM_UIMM(vcfux, 5, 12),
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GEN_VXFORM_UIMM(vcfsx, 5, 13),
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GEN_VXFORM_UIMM(vctuxs, 5, 14),
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GEN_VXFORM_UIMM(vctsxs, 5, 15),
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#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
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GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
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GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
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GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
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GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
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GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
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GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
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GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
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GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
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GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
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GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
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2016-09-06 08:04:09 +03:00
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GEN_VXFORM_300(vbpermd, 6, 23),
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2016-07-27 09:56:23 +03:00
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GEN_VXFORM_207(vbpermq, 6, 21),
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GEN_VXFORM_207(vgbbd, 6, 20),
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GEN_VXFORM_207(vpmsumb, 4, 16),
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GEN_VXFORM_207(vpmsumh, 4, 17),
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GEN_VXFORM_207(vpmsumw, 4, 18),
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GEN_VXFORM_207(vpmsumd, 4, 19),
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GEN_VXFORM_207(vsbox, 4, 23),
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GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207),
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GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
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GEN_VXFORM_207(vshasigmaw, 1, 26),
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GEN_VXFORM_207(vshasigmad, 1, 27),
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GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE),
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