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qemu/target/openrisc/insns.decode

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target/openrisc: Start conversion to decodetree.py Begin with the 0x08 major opcode, the system instructions. Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-19 23:28:12 +03:00
#
# OpenRISC instruction decode definitions.
#
# Copyright (c) 2018 Richard Henderson <rth@twiddle.net>
#
# This library is free software; you can redistribute it and/or
# modify it under the terms of the GNU Lesser General Public
# License as published by the Free Software Foundation; either
target/openrisc: Fix LGPL information in the file headers It's either "GNU *Library* General Public License version 2" or "GNU Lesser General Public License version *2.1*", but there was no "version 2.0" of the "Lesser" license. So assume that version 2.1 is meant here. Acked-by: Stafford Horne <shorne@gmail.com> Message-Id: <1550073577-4248-1-git-send-email-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-02-13 16:46:50 +03:00
# version 2.1 of the License, or (at your option) any later version.
target/openrisc: Start conversion to decodetree.py Begin with the 0x08 major opcode, the system instructions. Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-19 23:28:12 +03:00
#
# This library is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public
# License along with this library; if not, see <http://www.gnu.org/licenses/>.
#
target/openrisc: Convert dec_calc Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-20 21:04:14 +03:00
&dab d a b
&da d a
&ab a b
target/openrisc: Convert dec_logic Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-20 21:20:06 +03:00
&dal d a l
target/openrisc: Convert dec_compi Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-20 21:49:54 +03:00
&ai a i
target/openrisc: Add support for ORFPX64A32 This is hardware support for double-precision floating-point using pairs of 32-bit registers. Fix latent bugs in the heretofore unused helper_itofd and helper_ftoid. Include the bit for cpu "any". Change the default cpu for linux-user to "any". Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-07 00:49:25 +03:00
&dab_pair d a b dp ap bp
&ab_pair a b ap bp
&da_pair d a dp ap
target/openrisc: Convert dec_calc Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-20 21:04:14 +03:00
target/openrisc: Start conversion to decodetree.py Begin with the 0x08 major opcode, the system instructions. Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-19 23:28:12 +03:00
####
# System Instructions
####
l_sys 001000 0000000000 k:16
l_trap 001000 0100000000 k:16
l_msync 001000 1000000000 00000000 00000000
l_psync 001000 1010000000 00000000 00000000
l_csync 001000 1100000000 00000000 00000000
target/openrisc: Convert branch insns Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-19 23:52:43 +03:00
target/openrisc: Convert dec_calc Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-20 21:04:14 +03:00
l_rfe 001001 ----- ----- -------- --------
target/openrisc: Convert remainder of dec_misc insns Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-20 20:15:24 +03:00
target/openrisc: Convert branch insns Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-19 23:52:43 +03:00
####
# Branch Instructions
####
l_j 000000 n:s26
l_jal 000001 n:s26
l_bnf 000011 n:s26
l_bf 000100 n:s26
l_jr 010001 ---------- b:5 -----------
l_jalr 010010 ---------- b:5 -----------
target/openrisc: Convert memory insns Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-20 19:21:12 +03:00
####
# Memory Instructions
####
&load d a i
@load ...... d:5 a:5 i:s16 &load
%store_i 21:s5 0:11
&store a b i
@store ...... ..... a:5 b:5 ........... &store i=%store_i
l_lwa 011011 ..... ..... ........ ........ @load
l_lwz 100001 ..... ..... ........ ........ @load
l_lws 100010 ..... ..... ........ ........ @load
l_lbz 100011 ..... ..... ........ ........ @load
l_lbs 100100 ..... ..... ........ ........ @load
l_lhz 100101 ..... ..... ........ ........ @load
l_lhs 100110 ..... ..... ........ ........ @load
target/openrisc: Convert dec_calc Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-20 21:04:14 +03:00
l_swa 110011 ..... ..... ..... ........... @store
l_sw 110101 ..... ..... ..... ........... @store
l_sb 110110 ..... ..... ..... ........... @store
l_sh 110111 ..... ..... ..... ........... @store
target/openrisc: Convert remainder of dec_misc insns Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-20 20:15:24 +03:00
####
# Immediate Operand Instructions
####
target/openrisc: Convert dec_calc Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-20 21:04:14 +03:00
%mtspr_k 21:5 0:11
&rri d a i
&rrk d a k
@rri ...... d:5 a:5 i:s16 &rri
@rrk ...... d:5 a:5 k:16 &rrk
l_nop 000101 01--- ----- k:16
target/openrisc: Convert remainder of dec_misc insns Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-20 20:15:24 +03:00
target/openrisc: Convert dec_calc Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-20 21:04:14 +03:00
l_addi 100111 ..... ..... ........ ........ @rri
l_addic 101000 ..... ..... ........ ........ @rri
l_andi 101001 ..... ..... ........ ........ @rrk
l_ori 101010 ..... ..... ........ ........ @rrk
l_xori 101011 ..... ..... ........ ........ @rri
l_muli 101100 ..... ..... ........ ........ @rri
target/openrisc: Convert remainder of dec_misc insns Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-20 20:15:24 +03:00
target/openrisc: Convert dec_calc Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-20 21:04:14 +03:00
l_mfspr 101101 ..... ..... ........ ........ @rrk
l_mtspr 110000 ..... a:5 b:5 ........... k=%mtspr_k
target/openrisc: Convert remainder of dec_misc insns Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-20 20:15:24 +03:00
target/openrisc: Convert dec_calc Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-20 21:04:14 +03:00
l_maci 010011 ----- a:5 i:s16
target/openrisc: Convert remainder of dec_misc insns Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-20 20:15:24 +03:00
target/openrisc: Convert dec_M Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-20 21:28:01 +03:00
l_movhi 000110 d:5 ----0 k:16
l_macrc 000110 d:5 ----1 00000000 00000000
target/openrisc: Implement l.adrp This was added to the 1.3 spec. Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-08-26 03:31:30 +03:00
l_adrp 000010 d:5 i:s21
target/openrisc: Convert dec_calc Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-20 21:04:14 +03:00
####
# Arithmetic Instructions
####
target/openrisc: Convert remainder of dec_misc insns Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-20 20:15:24 +03:00
target/openrisc: Convert dec_calc Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-20 21:04:14 +03:00
l_exths 111000 d:5 a:5 ----- - 0000 -- 1100
l_extbs 111000 d:5 a:5 ----- - 0001 -- 1100
l_exthz 111000 d:5 a:5 ----- - 0010 -- 1100
l_extbz 111000 d:5 a:5 ----- - 0011 -- 1100
l_add 111000 d:5 a:5 b:5 - 00 ---- 0000
l_addc 111000 d:5 a:5 b:5 - 00 ---- 0001
l_sub 111000 d:5 a:5 b:5 - 00 ---- 0010
l_and 111000 d:5 a:5 b:5 - 00 ---- 0011
l_or 111000 d:5 a:5 b:5 - 00 ---- 0100
l_xor 111000 d:5 a:5 b:5 - 00 ---- 0101
l_cmov 111000 d:5 a:5 b:5 - 00 ---- 1110
l_ff1 111000 d:5 a:5 ----- - 00 ---- 1111
l_fl1 111000 d:5 a:5 ----- - 01 ---- 1111
l_sll 111000 d:5 a:5 b:5 - 0000 -- 1000
l_srl 111000 d:5 a:5 b:5 - 0001 -- 1000
l_sra 111000 d:5 a:5 b:5 - 0010 -- 1000
l_ror 111000 d:5 a:5 b:5 - 0011 -- 1000
l_mul 111000 d:5 a:5 b:5 - 11 ---- 0110
l_mulu 111000 d:5 a:5 b:5 - 11 ---- 1011
l_div 111000 d:5 a:5 b:5 - 11 ---- 1001
l_divu 111000 d:5 a:5 b:5 - 11 ---- 1010
l_muld 111000 ----- a:5 b:5 - 11 ---- 0111
l_muldu 111000 ----- a:5 b:5 - 11 ---- 1100
target/openrisc: Convert dec_mac Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-20 21:11:02 +03:00
l_mac 110001 ----- a:5 b:5 ------- 0001
l_macu 110001 ----- a:5 b:5 ------- 0011
l_msb 110001 ----- a:5 b:5 ------- 0010
l_msbu 110001 ----- a:5 b:5 ------- 0100
target/openrisc: Convert dec_logic Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-20 21:20:06 +03:00
l_slli 101110 d:5 a:5 -------- 00 l:6
l_srli 101110 d:5 a:5 -------- 01 l:6
l_srai 101110 d:5 a:5 -------- 10 l:6
l_rori 101110 d:5 a:5 -------- 11 l:6
target/openrisc: Convert dec_comp Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-20 21:41:47 +03:00
####
# Compare Instructions
####
l_sfeq 111001 00000 a:5 b:5 -----------
l_sfne 111001 00001 a:5 b:5 -----------
l_sfgtu 111001 00010 a:5 b:5 -----------
l_sfgeu 111001 00011 a:5 b:5 -----------
l_sfltu 111001 00100 a:5 b:5 -----------
l_sfleu 111001 00101 a:5 b:5 -----------
l_sfgts 111001 01010 a:5 b:5 -----------
l_sfges 111001 01011 a:5 b:5 -----------
l_sflts 111001 01100 a:5 b:5 -----------
l_sfles 111001 01101 a:5 b:5 -----------
target/openrisc: Convert dec_compi Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-20 21:49:54 +03:00
l_sfeqi 101111 00000 a:5 i:s16
l_sfnei 101111 00001 a:5 i:s16
l_sfgtui 101111 00010 a:5 i:s16
l_sfgeui 101111 00011 a:5 i:s16
l_sfltui 101111 00100 a:5 i:s16
l_sfleui 101111 00101 a:5 i:s16
l_sfgtsi 101111 01010 a:5 i:s16
l_sfgesi 101111 01011 a:5 i:s16
l_sfltsi 101111 01100 a:5 i:s16
l_sflesi 101111 01101 a:5 i:s16
target/openrisc: Convert dec_float Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-20 22:14:44 +03:00
####
# FP Instructions
####
lf_add_s 110010 d:5 a:5 b:5 --- 00000000
lf_sub_s 110010 d:5 a:5 b:5 --- 00000001
lf_mul_s 110010 d:5 a:5 b:5 --- 00000010
lf_div_s 110010 d:5 a:5 b:5 --- 00000011
lf_rem_s 110010 d:5 a:5 b:5 --- 00000110
lf_madd_s 110010 d:5 a:5 b:5 --- 00000111
lf_itof_s 110010 d:5 a:5 00000 --- 00000100
lf_ftoi_s 110010 d:5 a:5 00000 --- 00000101
lf_sfeq_s 110010 ----- a:5 b:5 --- 00001000
lf_sfne_s 110010 ----- a:5 b:5 --- 00001001
lf_sfgt_s 110010 ----- a:5 b:5 --- 00001010
lf_sfge_s 110010 ----- a:5 b:5 --- 00001011
lf_sflt_s 110010 ----- a:5 b:5 --- 00001100
lf_sfle_s 110010 ----- a:5 b:5 --- 00001101
target/openrisc: Implement unordered fp comparisons These were added to the 1.3 spec. For OF32S, validate AVR. But OF64A32 is itself new to 1.3 so no extra check needed. Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-14 16:39:47 +03:00
lf_sfueq_s 110010 ----- a:5 b:5 --- 00101000
lf_sfuge_s 110010 ----- a:5 b:5 --- 00101011
lf_sfugt_s 110010 ----- a:5 b:5 --- 00101010
lf_sfule_s 110010 ----- a:5 b:5 --- 00101101
lf_sfult_s 110010 ----- a:5 b:5 --- 00101100
lf_sfun_s 110010 ----- a:5 b:5 --- 00101110
target/openrisc: Add support for ORFPX64A32 This is hardware support for double-precision floating-point using pairs of 32-bit registers. Fix latent bugs in the heretofore unused helper_itofd and helper_ftoid. Include the bit for cpu "any". Change the default cpu for linux-user to "any". Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-07 00:49:25 +03:00
####
# DP Instructions
####
@dab_pair ...... d:5 a:5 b:5 dp:1 ap:1 bp:1 ........ &dab_pair
@ab_pair ...... ..... a:5 b:5 . ap:1 bp:1 ........ &ab_pair
@da_pair ...... d:5 a:5 ..... dp:1 ap:1 . ........ &da_pair
lf_add_d 110010 ..... ..... ..... ... 00010000 @dab_pair
lf_sub_d 110010 ..... ..... ..... ... 00010001 @dab_pair
lf_mul_d 110010 ..... ..... ..... ... 00010010 @dab_pair
lf_div_d 110010 ..... ..... ..... ... 00010011 @dab_pair
lf_rem_d 110010 ..... ..... ..... ... 00010110 @dab_pair
lf_madd_d 110010 ..... ..... ..... ... 00010111 @dab_pair
lf_itof_d 110010 ..... ..... 00000 ..0 00010100 @da_pair
lf_ftoi_d 110010 ..... ..... 00000 ..0 00010101 @da_pair
lf_stod_d 110010 d:5 a:5 00000 dp:1 0 0 00110100
lf_dtos_d 110010 d:5 a:5 00000 0 ap:1 0 00110101
lf_sfeq_d 110010 00000 ..... ..... 0.. 00011000 @ab_pair
lf_sfne_d 110010 00000 ..... ..... 0.. 00011001 @ab_pair
lf_sfgt_d 110010 00000 ..... ..... 0.. 00011010 @ab_pair
lf_sfge_d 110010 00000 ..... ..... 0.. 00011011 @ab_pair
lf_sflt_d 110010 00000 ..... ..... 0.. 00011100 @ab_pair
lf_sfle_d 110010 00000 ..... ..... 0.. 00011101 @ab_pair
target/openrisc: Implement unordered fp comparisons These were added to the 1.3 spec. For OF32S, validate AVR. But OF64A32 is itself new to 1.3 so no extra check needed. Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-14 16:39:47 +03:00
lf_sfueq_d 110010 00000 ..... ..... 0.. 00111000 @ab_pair
lf_sfuge_d 110010 00000 ..... ..... 0.. 00111011 @ab_pair
lf_sfugt_d 110010 00000 ..... ..... 0.. 00111010 @ab_pair
lf_sfule_d 110010 00000 ..... ..... 0.. 00111101 @ab_pair
lf_sfult_d 110010 00000 ..... ..... 0.. 00111100 @ab_pair
lf_sfun_d 110010 00000 ..... ..... 0.. 00111110 @ab_pair
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