2018-05-04 20:05:51 +03:00
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/*
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* Copyright (C) 2014-2016 Broadcom Corporation
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* Copyright (c) 2017 Red Hat, Inc.
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* Written by Prem Mallappa, Eric Auger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Author: Prem Mallappa <pmallapp@broadcom.com>
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*
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*/
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#include "qemu/osdep.h"
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#include "trace.h"
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#include "exec/target_page.h"
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2019-07-09 18:20:52 +03:00
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#include "hw/core/cpu.h"
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2018-05-04 20:05:51 +03:00
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#include "hw/qdev-properties.h"
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#include "qapi/error.h"
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2018-06-26 19:50:42 +03:00
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#include "qemu/jhash.h"
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2019-05-23 17:35:07 +03:00
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#include "qemu/module.h"
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2018-05-04 20:05:51 +03:00
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#include "qemu/error-report.h"
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#include "hw/arm/smmu-common.h"
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2018-05-04 20:05:51 +03:00
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#include "smmu-internal.h"
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2018-06-26 19:50:42 +03:00
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/* IOTLB Management */
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2020-07-28 18:08:07 +03:00
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static guint smmu_iotlb_key_hash(gconstpointer v)
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{
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SMMUIOTLBKey *key = (SMMUIOTLBKey *)v;
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uint32_t a, b, c;
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/* Jenkins hash */
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a = b = c = JHASH_INITVAL + sizeof(*key);
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2020-07-28 18:08:09 +03:00
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a += key->asid + key->level + key->tg;
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2020-07-28 18:08:07 +03:00
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b += extract64(key->iova, 0, 32);
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c += extract64(key->iova, 32, 32);
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__jhash_mix(a, b, c);
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__jhash_final(a, b, c);
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return c;
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}
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static gboolean smmu_iotlb_key_equal(gconstpointer v1, gconstpointer v2)
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{
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2020-07-28 18:08:09 +03:00
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SMMUIOTLBKey *k1 = (SMMUIOTLBKey *)v1, *k2 = (SMMUIOTLBKey *)v2;
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2020-07-28 18:08:07 +03:00
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2020-07-28 18:08:09 +03:00
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return (k1->asid == k2->asid) && (k1->iova == k2->iova) &&
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(k1->level == k2->level) && (k1->tg == k2->tg);
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2020-07-28 18:08:07 +03:00
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}
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2020-07-28 18:08:09 +03:00
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SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova,
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uint8_t tg, uint8_t level)
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2020-07-28 18:08:07 +03:00
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{
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2020-07-28 18:08:09 +03:00
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SMMUIOTLBKey key = {.asid = asid, .iova = iova, .tg = tg, .level = level};
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2020-07-28 18:08:07 +03:00
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return key;
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}
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2020-07-28 18:08:08 +03:00
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SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg,
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2020-07-28 18:08:09 +03:00
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SMMUTransTableInfo *tt, hwaddr iova)
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2020-07-28 18:08:06 +03:00
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{
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2020-07-28 18:08:09 +03:00
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uint8_t tg = (tt->granule_sz - 10) / 2;
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uint8_t inputsize = 64 - tt->tsz;
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uint8_t stride = tt->granule_sz - 3;
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uint8_t level = 4 - (inputsize - 4) / stride;
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SMMUTLBEntry *entry = NULL;
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while (level <= 3) {
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uint64_t subpage_size = 1ULL << level_shift(level, tt->granule_sz);
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uint64_t mask = subpage_size - 1;
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SMMUIOTLBKey key;
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key = smmu_get_iotlb_key(cfg->asid, iova & ~mask, tg, level);
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entry = g_hash_table_lookup(bs->iotlb, &key);
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if (entry) {
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break;
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}
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level++;
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}
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2020-07-28 18:08:06 +03:00
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if (entry) {
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cfg->iotlb_hits++;
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trace_smmu_iotlb_lookup_hit(cfg->asid, iova,
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cfg->iotlb_hits, cfg->iotlb_misses,
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100 * cfg->iotlb_hits /
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(cfg->iotlb_hits + cfg->iotlb_misses));
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} else {
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cfg->iotlb_misses++;
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trace_smmu_iotlb_lookup_miss(cfg->asid, iova,
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cfg->iotlb_hits, cfg->iotlb_misses,
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100 * cfg->iotlb_hits /
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(cfg->iotlb_hits + cfg->iotlb_misses));
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}
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return entry;
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}
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2020-07-28 18:08:08 +03:00
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void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *new)
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2020-07-28 18:08:06 +03:00
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{
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SMMUIOTLBKey *key = g_new0(SMMUIOTLBKey, 1);
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2020-07-28 18:08:09 +03:00
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uint8_t tg = (new->granule - 10) / 2;
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2020-07-28 18:08:06 +03:00
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if (g_hash_table_size(bs->iotlb) >= SMMU_IOTLB_MAX_SIZE) {
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smmu_iotlb_inv_all(bs);
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}
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2020-07-28 18:08:09 +03:00
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*key = smmu_get_iotlb_key(cfg->asid, new->entry.iova, tg, new->level);
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trace_smmu_iotlb_insert(cfg->asid, new->entry.iova, tg, new->level);
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2020-07-28 18:08:08 +03:00
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g_hash_table_insert(bs->iotlb, key, new);
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2020-07-28 18:08:06 +03:00
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}
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2018-06-26 19:50:42 +03:00
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inline void smmu_iotlb_inv_all(SMMUState *s)
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{
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trace_smmu_iotlb_inv_all();
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g_hash_table_remove_all(s->iotlb);
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}
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static gboolean smmu_hash_remove_by_asid(gpointer key, gpointer value,
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gpointer user_data)
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{
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uint16_t asid = *(uint16_t *)user_data;
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SMMUIOTLBKey *iotlb_key = (SMMUIOTLBKey *)key;
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2020-07-28 18:08:07 +03:00
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return SMMU_IOTLB_ASID(*iotlb_key) == asid;
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2018-06-26 19:50:42 +03:00
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}
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2020-07-28 18:08:09 +03:00
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static gboolean smmu_hash_remove_by_asid_iova(gpointer key, gpointer value,
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gpointer user_data)
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2018-06-26 19:50:42 +03:00
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{
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2020-07-28 18:08:09 +03:00
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SMMUTLBEntry *iter = (SMMUTLBEntry *)value;
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IOMMUTLBEntry *entry = &iter->entry;
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SMMUIOTLBPageInvInfo *info = (SMMUIOTLBPageInvInfo *)user_data;
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SMMUIOTLBKey iotlb_key = *(SMMUIOTLBKey *)key;
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if (info->asid >= 0 && info->asid != SMMU_IOTLB_ASID(iotlb_key)) {
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return false;
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}
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2020-07-28 18:08:11 +03:00
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return ((info->iova & ~entry->addr_mask) == entry->iova) ||
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((entry->iova & ~info->mask) == info->iova);
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2020-07-28 18:08:09 +03:00
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}
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2020-07-28 18:08:11 +03:00
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inline void
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smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
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uint8_t tg, uint64_t num_pages, uint8_t ttl)
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2020-07-28 18:08:09 +03:00
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{
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2021-03-09 13:27:40 +03:00
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/* if tg is not set we use 4KB range invalidation */
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uint8_t granule = tg ? tg * 2 + 10 : 12;
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2021-03-09 13:27:39 +03:00
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if (ttl && (num_pages == 1) && (asid >= 0)) {
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2020-07-28 18:08:11 +03:00
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SMMUIOTLBKey key = smmu_get_iotlb_key(asid, iova, tg, ttl);
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2018-06-26 19:50:42 +03:00
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2021-03-09 13:27:40 +03:00
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if (g_hash_table_remove(s->iotlb, &key)) {
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return;
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}
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/*
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* if the entry is not found, let's see if it does not
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* belong to a larger IOTLB entry
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*/
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}
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2020-07-28 18:08:11 +03:00
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2021-03-09 13:27:40 +03:00
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SMMUIOTLBPageInvInfo info = {
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.asid = asid, .iova = iova,
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.mask = (num_pages * 1 << granule) - 1};
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2020-07-28 18:08:11 +03:00
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2021-03-09 13:27:40 +03:00
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g_hash_table_foreach_remove(s->iotlb,
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smmu_hash_remove_by_asid_iova,
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&info);
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2018-06-26 19:50:42 +03:00
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}
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inline void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid)
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{
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trace_smmu_iotlb_inv_asid(asid);
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g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_asid, &asid);
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}
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2018-05-04 20:05:51 +03:00
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/* VMSAv8-64 Translation */
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/**
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* get_pte - Get the content of a page table entry located at
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* @base_addr[@index]
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*/
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static int get_pte(dma_addr_t baseaddr, uint32_t index, uint64_t *pte,
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SMMUPTWEventInfo *info)
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{
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int ret;
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dma_addr_t addr = baseaddr + index * sizeof(*pte);
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/* TODO: guarantee 64-bit single-copy atomicity */
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2020-02-20 12:39:00 +03:00
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ret = dma_memory_read(&address_space_memory, addr, pte, sizeof(*pte));
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2018-05-04 20:05:51 +03:00
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if (ret != MEMTX_OK) {
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info->type = SMMU_PTW_ERR_WALK_EABT;
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info->addr = addr;
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return -EINVAL;
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}
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trace_smmu_get_pte(baseaddr, index, addr, *pte);
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return 0;
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}
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/* VMSAv8-64 Translation Table Format Descriptor Decoding */
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/**
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* get_page_pte_address - returns the L3 descriptor output address,
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* ie. the page frame
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* ARM ARM spec: Figure D4-17 VMSAv8-64 level 3 descriptor format
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*/
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static inline hwaddr get_page_pte_address(uint64_t pte, int granule_sz)
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{
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return PTE_ADDRESS(pte, granule_sz);
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}
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/**
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* get_table_pte_address - return table descriptor output address,
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* ie. address of next level table
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* ARM ARM Figure D4-16 VMSAv8-64 level0, level1, and level 2 descriptor formats
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*/
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static inline hwaddr get_table_pte_address(uint64_t pte, int granule_sz)
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{
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return PTE_ADDRESS(pte, granule_sz);
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}
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/**
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* get_block_pte_address - return block descriptor output address and block size
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* ARM ARM Figure D4-16 VMSAv8-64 level0, level1, and level 2 descriptor formats
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*/
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static inline hwaddr get_block_pte_address(uint64_t pte, int level,
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int granule_sz, uint64_t *bsz)
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{
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2018-05-18 19:48:07 +03:00
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int n = level_shift(level, granule_sz);
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2018-05-04 20:05:51 +03:00
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2018-05-18 19:48:07 +03:00
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*bsz = 1ULL << n;
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2018-05-04 20:05:51 +03:00
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return PTE_ADDRESS(pte, n);
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}
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SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova)
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{
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bool tbi = extract64(iova, 55, 1) ? TBI1(cfg->tbi) : TBI0(cfg->tbi);
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uint8_t tbi_byte = tbi * 8;
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if (cfg->tt[0].tsz &&
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!extract64(iova, 64 - cfg->tt[0].tsz, cfg->tt[0].tsz - tbi_byte)) {
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/* there is a ttbr0 region and we are in it (high bits all zero) */
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return &cfg->tt[0];
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} else if (cfg->tt[1].tsz &&
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!extract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte)) {
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/* there is a ttbr1 region and we are in it (high bits all one) */
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return &cfg->tt[1];
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} else if (!cfg->tt[0].tsz) {
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/* ttbr0 region is "everything not in the ttbr1 region" */
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return &cfg->tt[0];
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} else if (!cfg->tt[1].tsz) {
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/* ttbr1 region is "everything not in the ttbr0 region" */
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return &cfg->tt[1];
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}
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/* in the gap between the two regions, this is a Translation fault */
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return NULL;
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}
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/**
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* smmu_ptw_64 - VMSAv8-64 Walk of the page tables for a given IOVA
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* @cfg: translation config
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* @iova: iova to translate
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* @perm: access type
|
2020-07-28 18:08:08 +03:00
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* @tlbe: SMMUTLBEntry (out)
|
2018-05-04 20:05:51 +03:00
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* @info: handle to an error info
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*
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* Return 0 on success, < 0 on error. In case of error, @info is filled
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* and tlbe->perm is set to IOMMU_NONE.
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* Upon success, @tlbe is filled with translated_addr and entry
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* permission rights.
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*/
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static int smmu_ptw_64(SMMUTransCfg *cfg,
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dma_addr_t iova, IOMMUAccessFlags perm,
|
2020-07-28 18:08:08 +03:00
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SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info)
|
2018-05-04 20:05:51 +03:00
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{
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dma_addr_t baseaddr, indexmask;
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int stage = cfg->stage;
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SMMUTransTableInfo *tt = select_tt(cfg, iova);
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uint8_t level, granule_sz, inputsize, stride;
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if (!tt || tt->disabled) {
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info->type = SMMU_PTW_ERR_TRANSLATION;
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goto error;
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}
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granule_sz = tt->granule_sz;
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stride = granule_sz - 3;
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inputsize = 64 - tt->tsz;
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level = 4 - (inputsize - 4) / stride;
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indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1;
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baseaddr = extract64(tt->ttb, 0, 48);
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baseaddr &= ~indexmask;
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while (level <= 3) {
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uint64_t subpage_size = 1ULL << level_shift(level, granule_sz);
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|
|
uint64_t mask = subpage_size - 1;
|
|
|
|
uint32_t offset = iova_level_offset(iova, inputsize, level, granule_sz);
|
2020-07-28 18:08:05 +03:00
|
|
|
uint64_t pte, gpa;
|
2018-05-04 20:05:51 +03:00
|
|
|
dma_addr_t pte_addr = baseaddr + offset * sizeof(pte);
|
|
|
|
uint8_t ap;
|
|
|
|
|
|
|
|
if (get_pte(baseaddr, offset, &pte, info)) {
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
trace_smmu_ptw_level(level, iova, subpage_size,
|
|
|
|
baseaddr, offset, pte);
|
|
|
|
|
|
|
|
if (is_invalid_pte(pte) || is_reserved_pte(pte, level)) {
|
|
|
|
trace_smmu_ptw_invalid_pte(stage, level, baseaddr,
|
|
|
|
pte_addr, offset, pte);
|
2020-07-28 18:08:05 +03:00
|
|
|
break;
|
2018-05-04 20:05:51 +03:00
|
|
|
}
|
|
|
|
|
2020-07-28 18:08:05 +03:00
|
|
|
if (is_table_pte(pte, level)) {
|
|
|
|
ap = PTE_APTABLE(pte);
|
2018-05-04 20:05:51 +03:00
|
|
|
|
2020-07-28 18:08:14 +03:00
|
|
|
if (is_permission_fault(ap, perm) && !tt->had) {
|
2018-05-04 20:05:51 +03:00
|
|
|
info->type = SMMU_PTW_ERR_PERMISSION;
|
|
|
|
goto error;
|
|
|
|
}
|
2020-07-28 18:08:05 +03:00
|
|
|
baseaddr = get_table_pte_address(pte, granule_sz);
|
|
|
|
level++;
|
|
|
|
continue;
|
|
|
|
} else if (is_page_pte(pte, level)) {
|
|
|
|
gpa = get_page_pte_address(pte, granule_sz);
|
2018-05-04 20:05:51 +03:00
|
|
|
trace_smmu_ptw_page_pte(stage, level, iova,
|
|
|
|
baseaddr, pte_addr, pte, gpa);
|
2020-07-28 18:08:05 +03:00
|
|
|
} else {
|
2018-05-04 20:05:51 +03:00
|
|
|
uint64_t block_size;
|
|
|
|
|
2020-07-28 18:08:05 +03:00
|
|
|
gpa = get_block_pte_address(pte, level, granule_sz,
|
|
|
|
&block_size);
|
2018-05-04 20:05:51 +03:00
|
|
|
trace_smmu_ptw_block_pte(stage, level, baseaddr,
|
|
|
|
pte_addr, pte, iova, gpa,
|
|
|
|
block_size >> 20);
|
|
|
|
}
|
2020-07-28 18:08:05 +03:00
|
|
|
ap = PTE_AP(pte);
|
2018-05-04 20:05:51 +03:00
|
|
|
if (is_permission_fault(ap, perm)) {
|
|
|
|
info->type = SMMU_PTW_ERR_PERMISSION;
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
2020-07-28 18:08:09 +03:00
|
|
|
tlbe->entry.translated_addr = gpa;
|
|
|
|
tlbe->entry.iova = iova & ~mask;
|
|
|
|
tlbe->entry.addr_mask = mask;
|
2020-07-28 18:08:08 +03:00
|
|
|
tlbe->entry.perm = PTE_AP_TO_PERM(ap);
|
|
|
|
tlbe->level = level;
|
|
|
|
tlbe->granule = granule_sz;
|
2020-07-28 18:08:05 +03:00
|
|
|
return 0;
|
|
|
|
}
|
2018-05-04 20:05:51 +03:00
|
|
|
info->type = SMMU_PTW_ERR_TRANSLATION;
|
|
|
|
|
|
|
|
error:
|
2020-07-28 18:08:08 +03:00
|
|
|
tlbe->entry.perm = IOMMU_NONE;
|
2018-05-04 20:05:51 +03:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* smmu_ptw - Walk the page tables for an IOVA, according to @cfg
|
|
|
|
*
|
|
|
|
* @cfg: translation configuration
|
|
|
|
* @iova: iova to translate
|
|
|
|
* @perm: tentative access type
|
|
|
|
* @tlbe: returned entry
|
|
|
|
* @info: ptw event handle
|
|
|
|
*
|
|
|
|
* return 0 on success
|
|
|
|
*/
|
|
|
|
inline int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm,
|
2020-07-28 18:08:08 +03:00
|
|
|
SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info)
|
2018-05-04 20:05:51 +03:00
|
|
|
{
|
|
|
|
if (!cfg->aa64) {
|
|
|
|
/*
|
|
|
|
* This code path is not entered as we check this while decoding
|
|
|
|
* the configuration data in the derived SMMU model.
|
|
|
|
*/
|
|
|
|
g_assert_not_reached();
|
|
|
|
}
|
|
|
|
|
|
|
|
return smmu_ptw_64(cfg, iova, perm, tlbe, info);
|
|
|
|
}
|
2018-05-04 20:05:51 +03:00
|
|
|
|
2018-05-04 20:05:51 +03:00
|
|
|
/**
|
|
|
|
* The bus number is used for lookup when SID based invalidation occurs.
|
|
|
|
* In that case we lazily populate the SMMUPciBus array from the bus hash
|
|
|
|
* table. At the time the SMMUPciBus is created (smmu_find_add_as), the bus
|
|
|
|
* numbers may not be always initialized yet.
|
|
|
|
*/
|
|
|
|
SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8_t bus_num)
|
|
|
|
{
|
|
|
|
SMMUPciBus *smmu_pci_bus = s->smmu_pcibus_by_bus_num[bus_num];
|
2020-03-05 19:09:14 +03:00
|
|
|
GHashTableIter iter;
|
2018-05-04 20:05:51 +03:00
|
|
|
|
2020-03-05 19:09:14 +03:00
|
|
|
if (smmu_pci_bus) {
|
|
|
|
return smmu_pci_bus;
|
|
|
|
}
|
2018-05-04 20:05:51 +03:00
|
|
|
|
2020-03-05 19:09:14 +03:00
|
|
|
g_hash_table_iter_init(&iter, s->smmu_pcibus_by_busptr);
|
|
|
|
while (g_hash_table_iter_next(&iter, NULL, (void **)&smmu_pci_bus)) {
|
|
|
|
if (pci_bus_num(smmu_pci_bus->bus) == bus_num) {
|
|
|
|
s->smmu_pcibus_by_bus_num[bus_num] = smmu_pci_bus;
|
|
|
|
return smmu_pci_bus;
|
2018-05-04 20:05:51 +03:00
|
|
|
}
|
|
|
|
}
|
2020-03-05 19:09:14 +03:00
|
|
|
|
|
|
|
return NULL;
|
2018-05-04 20:05:51 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn)
|
|
|
|
{
|
|
|
|
SMMUState *s = opaque;
|
|
|
|
SMMUPciBus *sbus = g_hash_table_lookup(s->smmu_pcibus_by_busptr, bus);
|
|
|
|
SMMUDevice *sdev;
|
2018-09-25 16:02:32 +03:00
|
|
|
static unsigned int index;
|
2018-05-04 20:05:51 +03:00
|
|
|
|
|
|
|
if (!sbus) {
|
|
|
|
sbus = g_malloc0(sizeof(SMMUPciBus) +
|
|
|
|
sizeof(SMMUDevice *) * SMMU_PCI_DEVFN_MAX);
|
|
|
|
sbus->bus = bus;
|
|
|
|
g_hash_table_insert(s->smmu_pcibus_by_busptr, bus, sbus);
|
|
|
|
}
|
|
|
|
|
|
|
|
sdev = sbus->pbdev[devfn];
|
|
|
|
if (!sdev) {
|
2018-09-25 16:02:32 +03:00
|
|
|
char *name = g_strdup_printf("%s-%d-%d", s->mrtypename, devfn, index++);
|
|
|
|
|
2018-05-04 20:05:51 +03:00
|
|
|
sdev = sbus->pbdev[devfn] = g_new0(SMMUDevice, 1);
|
|
|
|
|
|
|
|
sdev->smmu = s;
|
|
|
|
sdev->bus = bus;
|
|
|
|
sdev->devfn = devfn;
|
|
|
|
|
|
|
|
memory_region_init_iommu(&sdev->iommu, sizeof(sdev->iommu),
|
|
|
|
s->mrtypename,
|
|
|
|
OBJECT(s), name, 1ULL << SMMU_MAX_VA_BITS);
|
|
|
|
address_space_init(&sdev->as,
|
|
|
|
MEMORY_REGION(&sdev->iommu), name);
|
|
|
|
trace_smmu_add_mr(name);
|
|
|
|
g_free(name);
|
|
|
|
}
|
|
|
|
|
|
|
|
return &sdev->as;
|
|
|
|
}
|
|
|
|
|
2018-06-26 19:50:42 +03:00
|
|
|
IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid)
|
|
|
|
{
|
|
|
|
uint8_t bus_n, devfn;
|
|
|
|
SMMUPciBus *smmu_bus;
|
|
|
|
SMMUDevice *smmu;
|
|
|
|
|
|
|
|
bus_n = PCI_BUS_NUM(sid);
|
|
|
|
smmu_bus = smmu_find_smmu_pcibus(s, bus_n);
|
|
|
|
if (smmu_bus) {
|
2018-07-09 16:51:34 +03:00
|
|
|
devfn = SMMU_PCI_DEVFN(sid);
|
2018-06-26 19:50:42 +03:00
|
|
|
smmu = smmu_bus->pbdev[devfn];
|
|
|
|
if (smmu) {
|
|
|
|
return &smmu->iommu;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2018-06-26 19:50:42 +03:00
|
|
|
/* Unmap the whole notifier's range */
|
|
|
|
static void smmu_unmap_notifier_range(IOMMUNotifier *n)
|
|
|
|
{
|
2020-11-16 19:55:03 +03:00
|
|
|
IOMMUTLBEvent event;
|
2018-06-26 19:50:42 +03:00
|
|
|
|
2020-11-16 19:55:03 +03:00
|
|
|
event.type = IOMMU_NOTIFIER_UNMAP;
|
|
|
|
event.entry.target_as = &address_space_memory;
|
|
|
|
event.entry.iova = n->start;
|
|
|
|
event.entry.perm = IOMMU_NONE;
|
|
|
|
event.entry.addr_mask = n->end - n->start;
|
2018-06-26 19:50:42 +03:00
|
|
|
|
2020-11-16 19:55:03 +03:00
|
|
|
memory_region_notify_iommu_one(n, &event);
|
2018-06-26 19:50:42 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Unmap all notifiers attached to @mr */
|
|
|
|
inline void smmu_inv_notifiers_mr(IOMMUMemoryRegion *mr)
|
|
|
|
{
|
|
|
|
IOMMUNotifier *n;
|
|
|
|
|
|
|
|
trace_smmu_inv_notifiers_mr(mr->parent_obj.name);
|
|
|
|
IOMMU_NOTIFIER_FOREACH(n, mr) {
|
|
|
|
smmu_unmap_notifier_range(n);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Unmap all notifiers of all mr's */
|
|
|
|
void smmu_inv_notifiers_all(SMMUState *s)
|
|
|
|
{
|
2019-04-29 19:35:57 +03:00
|
|
|
SMMUDevice *sdev;
|
2018-06-26 19:50:42 +03:00
|
|
|
|
2019-04-29 19:35:57 +03:00
|
|
|
QLIST_FOREACH(sdev, &s->devices_with_notifiers, next) {
|
|
|
|
smmu_inv_notifiers_mr(&sdev->iommu);
|
2018-06-26 19:50:42 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-05-04 20:05:51 +03:00
|
|
|
static void smmu_base_realize(DeviceState *dev, Error **errp)
|
|
|
|
{
|
2018-05-04 20:05:51 +03:00
|
|
|
SMMUState *s = ARM_SMMU(dev);
|
2018-05-04 20:05:51 +03:00
|
|
|
SMMUBaseClass *sbc = ARM_SMMU_GET_CLASS(dev);
|
|
|
|
Error *local_err = NULL;
|
|
|
|
|
|
|
|
sbc->parent_realize(dev, &local_err);
|
|
|
|
if (local_err) {
|
|
|
|
error_propagate(errp, local_err);
|
|
|
|
return;
|
|
|
|
}
|
2018-06-26 19:50:42 +03:00
|
|
|
s->configs = g_hash_table_new_full(NULL, NULL, NULL, g_free);
|
2018-06-26 19:50:42 +03:00
|
|
|
s->iotlb = g_hash_table_new_full(smmu_iotlb_key_hash, smmu_iotlb_key_equal,
|
|
|
|
g_free, g_free);
|
2018-05-04 20:05:51 +03:00
|
|
|
s->smmu_pcibus_by_busptr = g_hash_table_new(NULL, NULL);
|
|
|
|
|
|
|
|
if (s->primary_bus) {
|
|
|
|
pci_setup_iommu(s->primary_bus, smmu_find_add_as, s);
|
|
|
|
} else {
|
|
|
|
error_setg(errp, "SMMU is not attached to any PCI bus!");
|
|
|
|
}
|
2018-05-04 20:05:51 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static void smmu_base_reset(DeviceState *dev)
|
|
|
|
{
|
2018-06-26 19:50:42 +03:00
|
|
|
SMMUState *s = ARM_SMMU(dev);
|
|
|
|
|
|
|
|
g_hash_table_remove_all(s->configs);
|
2018-06-26 19:50:42 +03:00
|
|
|
g_hash_table_remove_all(s->iotlb);
|
2018-05-04 20:05:51 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static Property smmu_dev_properties[] = {
|
|
|
|
DEFINE_PROP_UINT8("bus_num", SMMUState, bus_num, 0),
|
|
|
|
DEFINE_PROP_LINK("primary-bus", SMMUState, primary_bus, "PCI", PCIBus *),
|
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
};
|
|
|
|
|
|
|
|
static void smmu_base_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
SMMUBaseClass *sbc = ARM_SMMU_CLASS(klass);
|
|
|
|
|
2020-01-10 18:30:32 +03:00
|
|
|
device_class_set_props(dc, smmu_dev_properties);
|
2018-05-04 20:05:51 +03:00
|
|
|
device_class_set_parent_realize(dc, smmu_base_realize,
|
|
|
|
&sbc->parent_realize);
|
|
|
|
dc->reset = smmu_base_reset;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo smmu_base_info = {
|
|
|
|
.name = TYPE_ARM_SMMU,
|
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
|
|
.instance_size = sizeof(SMMUState),
|
|
|
|
.class_data = NULL,
|
|
|
|
.class_size = sizeof(SMMUBaseClass),
|
|
|
|
.class_init = smmu_base_class_init,
|
|
|
|
.abstract = true,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void smmu_base_register_types(void)
|
|
|
|
{
|
|
|
|
type_register_static(&smmu_base_info);
|
|
|
|
}
|
|
|
|
|
|
|
|
type_init(smmu_base_register_types)
|
|
|
|
|