2004-12-20 02:18:01 +03:00
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/*
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* QEMU Sparc SLAVIO serial port emulation
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*
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2005-04-07 00:42:35 +04:00
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* Copyright (c) 2003-2005 Fabrice Bellard
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2004-12-20 02:18:01 +03:00
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h"
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2005-04-07 00:42:35 +04:00
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/* debug serial */
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2004-12-20 02:18:01 +03:00
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//#define DEBUG_SERIAL
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/* debug keyboard */
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//#define DEBUG_KBD
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2005-04-07 00:42:35 +04:00
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/* debug mouse */
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2004-12-20 02:18:01 +03:00
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//#define DEBUG_MOUSE
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/*
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* This is the serial port, mouse and keyboard part of chip STP2001
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* (Slave I/O), also produced as NCR89C105. See
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
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*
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* The serial ports implement full AMD AM8530 or Zilog Z8530 chips,
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* mouse and keyboard ports don't implement all functions and they are
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* only asynchronous. There is no DMA.
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*
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*/
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2006-09-09 15:35:47 +04:00
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/*
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* Modifications:
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* 2006-Aug-10 Igor Kovalenko : Renamed KBDQueue to SERIOQueue, implemented
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* serial mouse queue.
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* Implemented serial mouse protocol.
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*/
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2005-04-07 00:42:35 +04:00
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#ifdef DEBUG_SERIAL
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#define SER_DPRINTF(fmt, args...) \
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do { printf("SER: " fmt , ##args); } while (0)
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#else
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#define SER_DPRINTF(fmt, args...)
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#endif
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#ifdef DEBUG_KBD
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#define KBD_DPRINTF(fmt, args...) \
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do { printf("KBD: " fmt , ##args); } while (0)
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#else
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#define KBD_DPRINTF(fmt, args...)
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#endif
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#ifdef DEBUG_MOUSE
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#define MS_DPRINTF(fmt, args...) \
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2006-09-09 15:35:47 +04:00
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do { printf("MSC: " fmt , ##args); } while (0)
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2005-04-07 00:42:35 +04:00
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#else
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#define MS_DPRINTF(fmt, args...)
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#endif
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typedef enum {
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chn_a, chn_b,
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} chn_id_t;
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2006-09-09 16:17:15 +04:00
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#define CHN_C(s) ((s)->chn == chn_b? 'b' : 'a')
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2005-04-07 00:42:35 +04:00
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typedef enum {
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ser, kbd, mouse,
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} chn_type_t;
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2006-09-09 15:35:47 +04:00
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#define SERIO_QUEUE_SIZE 256
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2005-04-07 00:42:35 +04:00
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typedef struct {
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2006-09-09 15:35:47 +04:00
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uint8_t data[SERIO_QUEUE_SIZE];
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2005-04-07 00:42:35 +04:00
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int rptr, wptr, count;
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2006-09-09 15:35:47 +04:00
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} SERIOQueue;
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2005-04-07 00:42:35 +04:00
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2004-12-20 02:18:01 +03:00
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typedef struct ChannelState {
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2007-04-07 22:14:41 +04:00
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qemu_irq irq;
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2004-12-20 02:18:01 +03:00
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int reg;
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2006-09-09 15:38:11 +04:00
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int rxint, txint, rxint_under_svc, txint_under_svc;
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2005-04-07 00:42:35 +04:00
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chn_id_t chn; // this channel, A (base+4) or B (base+0)
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chn_type_t type;
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struct ChannelState *otherchn;
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2004-12-20 02:18:01 +03:00
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uint8_t rx, tx, wregs[16], rregs[16];
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2006-09-09 15:35:47 +04:00
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SERIOQueue queue;
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2004-12-20 02:18:01 +03:00
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CharDriverState *chr;
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} ChannelState;
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struct SerialState {
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struct ChannelState chn[2];
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};
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#define SERIAL_MAXADDR 7
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2005-04-07 00:42:35 +04:00
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static void handle_kbd_command(ChannelState *s, int val);
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static int serial_can_receive(void *opaque);
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static void serial_receive_byte(ChannelState *s, int ch);
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2006-09-09 15:38:11 +04:00
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static inline void set_txint(ChannelState *s);
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2005-04-07 00:42:35 +04:00
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static void put_queue(void *opaque, int b)
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{
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ChannelState *s = opaque;
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2006-09-09 15:35:47 +04:00
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SERIOQueue *q = &s->queue;
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2005-04-07 00:42:35 +04:00
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2006-09-09 16:17:15 +04:00
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SER_DPRINTF("channel %c put: 0x%02x\n", CHN_C(s), b);
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2006-09-09 15:35:47 +04:00
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if (q->count >= SERIO_QUEUE_SIZE)
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2005-04-07 00:42:35 +04:00
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return;
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q->data[q->wptr] = b;
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2006-09-09 15:35:47 +04:00
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if (++q->wptr == SERIO_QUEUE_SIZE)
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2005-04-07 00:42:35 +04:00
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q->wptr = 0;
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q->count++;
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serial_receive_byte(s, 0);
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}
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static uint32_t get_queue(void *opaque)
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{
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ChannelState *s = opaque;
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2006-09-09 15:35:47 +04:00
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SERIOQueue *q = &s->queue;
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2005-04-07 00:42:35 +04:00
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int val;
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if (q->count == 0) {
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return 0;
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} else {
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val = q->data[q->rptr];
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2006-09-09 15:35:47 +04:00
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if (++q->rptr == SERIO_QUEUE_SIZE)
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2005-04-07 00:42:35 +04:00
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q->rptr = 0;
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q->count--;
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}
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2006-09-09 16:17:15 +04:00
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KBD_DPRINTF("channel %c get 0x%02x\n", CHN_C(s), val);
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2005-04-07 00:42:35 +04:00
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if (q->count > 0)
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serial_receive_byte(s, 0);
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return val;
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}
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2006-09-09 15:38:11 +04:00
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static int slavio_serial_update_irq_chn(ChannelState *s)
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2004-12-20 02:18:01 +03:00
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{
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if ((s->wregs[1] & 1) && // interrupts enabled
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(((s->wregs[1] & 2) && s->txint == 1) || // tx ints enabled, pending
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((((s->wregs[1] & 0x18) == 8) || ((s->wregs[1] & 0x18) == 0x10)) &&
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s->rxint == 1) || // rx ints enabled, pending
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((s->wregs[15] & 0x80) && (s->rregs[0] & 0x80)))) { // break int e&p
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2006-09-09 15:38:11 +04:00
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return 1;
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2004-12-20 02:18:01 +03:00
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}
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2006-09-09 15:38:11 +04:00
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return 0;
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}
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static void slavio_serial_update_irq(ChannelState *s)
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{
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int irq;
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irq = slavio_serial_update_irq_chn(s);
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irq |= slavio_serial_update_irq_chn(s->otherchn);
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2007-04-07 22:14:41 +04:00
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SER_DPRINTF("IRQ = %d\n", irq);
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qemu_set_irq(s->irq, irq);
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2004-12-20 02:18:01 +03:00
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}
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static void slavio_serial_reset_chn(ChannelState *s)
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{
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int i;
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s->reg = 0;
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for (i = 0; i < SERIAL_MAXADDR; i++) {
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s->rregs[i] = 0;
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s->wregs[i] = 0;
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}
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s->wregs[4] = 4;
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s->wregs[9] = 0xc0;
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s->wregs[11] = 8;
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s->wregs[14] = 0x30;
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s->wregs[15] = 0xf8;
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s->rregs[0] = 0x44;
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s->rregs[1] = 6;
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s->rx = s->tx = 0;
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s->rxint = s->txint = 0;
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2006-09-09 15:38:11 +04:00
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s->rxint_under_svc = s->txint_under_svc = 0;
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2004-12-20 02:18:01 +03:00
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}
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static void slavio_serial_reset(void *opaque)
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{
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SerialState *s = opaque;
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slavio_serial_reset_chn(&s->chn[0]);
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slavio_serial_reset_chn(&s->chn[1]);
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}
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2005-12-05 23:31:52 +03:00
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static inline void clr_rxint(ChannelState *s)
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{
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s->rxint = 0;
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2006-09-09 15:38:11 +04:00
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s->rxint_under_svc = 0;
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2006-09-09 16:17:15 +04:00
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if (s->chn == chn_a)
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2005-12-05 23:31:52 +03:00
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s->rregs[3] &= ~0x20;
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2006-09-09 16:17:15 +04:00
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else
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2005-12-05 23:31:52 +03:00
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s->otherchn->rregs[3] &= ~4;
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2006-09-09 15:38:11 +04:00
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if (s->txint)
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set_txint(s);
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else
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s->rregs[2] = 6;
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2005-12-05 23:31:52 +03:00
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slavio_serial_update_irq(s);
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}
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static inline void set_rxint(ChannelState *s)
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{
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s->rxint = 1;
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2006-09-09 15:38:11 +04:00
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if (!s->txint_under_svc) {
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s->rxint_under_svc = 1;
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2006-09-09 16:17:15 +04:00
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if (s->chn == chn_a)
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2006-09-09 15:38:11 +04:00
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s->rregs[3] |= 0x20;
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2006-09-09 16:17:15 +04:00
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else
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2006-09-09 15:38:11 +04:00
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s->otherchn->rregs[3] |= 4;
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s->rregs[2] = 4;
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slavio_serial_update_irq(s);
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2005-12-05 23:31:52 +03:00
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}
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}
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static inline void clr_txint(ChannelState *s)
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{
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s->txint = 0;
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2006-09-09 15:38:11 +04:00
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s->txint_under_svc = 0;
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2006-09-09 16:17:15 +04:00
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if (s->chn == chn_a)
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2005-12-05 23:31:52 +03:00
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s->rregs[3] &= ~0x10;
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2006-09-09 16:17:15 +04:00
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else
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2005-12-05 23:31:52 +03:00
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s->otherchn->rregs[3] &= ~2;
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2006-09-09 15:38:11 +04:00
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if (s->rxint)
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set_rxint(s);
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else
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s->rregs[2] = 6;
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2005-12-05 23:31:52 +03:00
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slavio_serial_update_irq(s);
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}
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static inline void set_txint(ChannelState *s)
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{
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s->txint = 1;
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2006-09-09 15:38:11 +04:00
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if (!s->rxint_under_svc) {
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s->txint_under_svc = 1;
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2006-09-09 16:17:15 +04:00
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if (s->chn == chn_a)
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2006-09-09 15:38:11 +04:00
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s->rregs[3] |= 0x10;
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2006-09-09 16:17:15 +04:00
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else
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2006-09-09 15:38:11 +04:00
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s->otherchn->rregs[3] |= 2;
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s->rregs[2] = 0;
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slavio_serial_update_irq(s);
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2005-12-05 23:31:52 +03:00
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}
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}
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2006-09-09 16:17:15 +04:00
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static void slavio_serial_update_parameters(ChannelState *s)
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{
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int speed, parity, data_bits, stop_bits;
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QEMUSerialSetParams ssp;
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if (!s->chr || s->type != ser)
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return;
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if (s->wregs[4] & 1) {
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if (s->wregs[4] & 2)
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parity = 'E';
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else
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parity = 'O';
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} else {
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parity = 'N';
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}
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if ((s->wregs[4] & 0x0c) == 0x0c)
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stop_bits = 2;
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else
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stop_bits = 1;
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switch (s->wregs[5] & 0x60) {
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case 0x00:
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data_bits = 5;
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break;
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case 0x20:
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data_bits = 7;
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break;
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case 0x40:
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data_bits = 6;
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break;
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default:
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case 0x60:
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data_bits = 8;
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break;
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}
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speed = 2457600 / ((s->wregs[12] | (s->wregs[13] << 8)) + 2);
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switch (s->wregs[4] & 0xc0) {
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case 0x00:
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break;
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case 0x40:
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speed /= 16;
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break;
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case 0x80:
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speed /= 32;
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break;
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default:
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case 0xc0:
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speed /= 64;
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break;
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}
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ssp.speed = speed;
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ssp.parity = parity;
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ssp.data_bits = data_bits;
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ssp.stop_bits = stop_bits;
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SER_DPRINTF("channel %c: speed=%d parity=%c data=%d stop=%d\n", CHN_C(s),
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speed, parity, data_bits, stop_bits);
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qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
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}
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2005-01-31 01:39:56 +03:00
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static void slavio_serial_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
|
2004-12-20 02:18:01 +03:00
|
|
|
{
|
|
|
|
SerialState *ser = opaque;
|
|
|
|
ChannelState *s;
|
|
|
|
uint32_t saddr;
|
|
|
|
int newreg, channel;
|
|
|
|
|
|
|
|
val &= 0xff;
|
|
|
|
saddr = (addr & 3) >> 1;
|
|
|
|
channel = (addr & SERIAL_MAXADDR) >> 2;
|
|
|
|
s = &ser->chn[channel];
|
|
|
|
switch (saddr) {
|
|
|
|
case 0:
|
2006-09-09 16:17:15 +04:00
|
|
|
SER_DPRINTF("Write channel %c, reg[%d] = %2.2x\n", CHN_C(s), s->reg, val & 0xff);
|
2004-12-20 02:18:01 +03:00
|
|
|
newreg = 0;
|
|
|
|
switch (s->reg) {
|
|
|
|
case 0:
|
|
|
|
newreg = val & 7;
|
|
|
|
val &= 0x38;
|
|
|
|
switch (val) {
|
|
|
|
case 8:
|
2005-10-30 20:05:44 +03:00
|
|
|
newreg |= 0x8;
|
2004-12-20 02:18:01 +03:00
|
|
|
break;
|
|
|
|
case 0x28:
|
2005-12-05 23:31:52 +03:00
|
|
|
clr_txint(s);
|
|
|
|
break;
|
|
|
|
case 0x38:
|
2006-09-09 15:38:11 +04:00
|
|
|
if (s->rxint_under_svc)
|
|
|
|
clr_rxint(s);
|
|
|
|
else if (s->txint_under_svc)
|
|
|
|
clr_txint(s);
|
2004-12-20 02:18:01 +03:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
2006-09-09 16:17:15 +04:00
|
|
|
case 1 ... 3:
|
|
|
|
case 6 ... 8:
|
|
|
|
case 10 ... 11:
|
|
|
|
case 14 ... 15:
|
|
|
|
s->wregs[s->reg] = val;
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
case 5:
|
|
|
|
case 12:
|
|
|
|
case 13:
|
2004-12-20 02:18:01 +03:00
|
|
|
s->wregs[s->reg] = val;
|
2006-09-09 16:17:15 +04:00
|
|
|
slavio_serial_update_parameters(s);
|
2004-12-20 02:18:01 +03:00
|
|
|
break;
|
|
|
|
case 9:
|
|
|
|
switch (val & 0xc0) {
|
|
|
|
case 0:
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
case 0x40:
|
|
|
|
slavio_serial_reset_chn(&ser->chn[1]);
|
|
|
|
return;
|
|
|
|
case 0x80:
|
|
|
|
slavio_serial_reset_chn(&ser->chn[0]);
|
|
|
|
return;
|
|
|
|
case 0xc0:
|
|
|
|
slavio_serial_reset(ser);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (s->reg == 0)
|
|
|
|
s->reg = newreg;
|
|
|
|
else
|
|
|
|
s->reg = 0;
|
|
|
|
break;
|
|
|
|
case 1:
|
2006-09-09 16:17:15 +04:00
|
|
|
SER_DPRINTF("Write channel %c, ch %d\n", CHN_C(s), val);
|
2004-12-20 02:18:01 +03:00
|
|
|
if (s->wregs[5] & 8) { // tx enabled
|
|
|
|
s->tx = val;
|
|
|
|
if (s->chr)
|
|
|
|
qemu_chr_write(s->chr, &s->tx, 1);
|
2005-04-07 00:42:35 +04:00
|
|
|
else if (s->type == kbd) {
|
|
|
|
handle_kbd_command(s, val);
|
|
|
|
}
|
2005-10-30 20:05:44 +03:00
|
|
|
s->rregs[0] |= 4; // Tx buffer empty
|
|
|
|
s->rregs[1] |= 1; // All sent
|
2005-12-05 23:31:52 +03:00
|
|
|
set_txint(s);
|
2004-12-20 02:18:01 +03:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2005-01-31 01:39:56 +03:00
|
|
|
static uint32_t slavio_serial_mem_readb(void *opaque, target_phys_addr_t addr)
|
2004-12-20 02:18:01 +03:00
|
|
|
{
|
|
|
|
SerialState *ser = opaque;
|
|
|
|
ChannelState *s;
|
|
|
|
uint32_t saddr;
|
|
|
|
uint32_t ret;
|
|
|
|
int channel;
|
|
|
|
|
|
|
|
saddr = (addr & 3) >> 1;
|
|
|
|
channel = (addr & SERIAL_MAXADDR) >> 2;
|
|
|
|
s = &ser->chn[channel];
|
|
|
|
switch (saddr) {
|
|
|
|
case 0:
|
2006-09-09 16:17:15 +04:00
|
|
|
SER_DPRINTF("Read channel %c, reg[%d] = %2.2x\n", CHN_C(s), s->reg, s->rregs[s->reg]);
|
2004-12-20 02:18:01 +03:00
|
|
|
ret = s->rregs[s->reg];
|
|
|
|
s->reg = 0;
|
|
|
|
return ret;
|
|
|
|
case 1:
|
|
|
|
s->rregs[0] &= ~1;
|
2005-12-05 23:31:52 +03:00
|
|
|
clr_rxint(s);
|
2006-09-09 15:35:47 +04:00
|
|
|
if (s->type == kbd || s->type == mouse)
|
2005-04-07 00:42:35 +04:00
|
|
|
ret = get_queue(s);
|
|
|
|
else
|
|
|
|
ret = s->rx;
|
2006-09-09 16:17:15 +04:00
|
|
|
SER_DPRINTF("Read channel %c, ch %d\n", CHN_C(s), ret);
|
2005-04-07 00:42:35 +04:00
|
|
|
return ret;
|
2004-12-20 02:18:01 +03:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int serial_can_receive(void *opaque)
|
|
|
|
{
|
|
|
|
ChannelState *s = opaque;
|
2006-09-09 15:38:11 +04:00
|
|
|
int ret;
|
|
|
|
|
2004-12-20 02:18:01 +03:00
|
|
|
if (((s->wregs[3] & 1) == 0) // Rx not enabled
|
|
|
|
|| ((s->rregs[0] & 1) == 1)) // char already available
|
2006-09-09 15:38:11 +04:00
|
|
|
ret = 0;
|
2004-12-20 02:18:01 +03:00
|
|
|
else
|
2006-09-09 15:38:11 +04:00
|
|
|
ret = 1;
|
2006-09-09 16:17:15 +04:00
|
|
|
//SER_DPRINTF("channel %c can receive %d\n", CHN_C(s), ret);
|
2006-09-09 15:38:11 +04:00
|
|
|
return ret;
|
2004-12-20 02:18:01 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static void serial_receive_byte(ChannelState *s, int ch)
|
|
|
|
{
|
2006-09-09 16:17:15 +04:00
|
|
|
SER_DPRINTF("channel %c put ch %d\n", CHN_C(s), ch);
|
2004-12-20 02:18:01 +03:00
|
|
|
s->rregs[0] |= 1;
|
|
|
|
s->rx = ch;
|
2005-12-05 23:31:52 +03:00
|
|
|
set_rxint(s);
|
2004-12-20 02:18:01 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static void serial_receive_break(ChannelState *s)
|
|
|
|
{
|
|
|
|
s->rregs[0] |= 0x80;
|
|
|
|
slavio_serial_update_irq(s);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void serial_receive1(void *opaque, const uint8_t *buf, int size)
|
|
|
|
{
|
|
|
|
ChannelState *s = opaque;
|
|
|
|
serial_receive_byte(s, buf[0]);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void serial_event(void *opaque, int event)
|
|
|
|
{
|
|
|
|
ChannelState *s = opaque;
|
|
|
|
if (event == CHR_EVENT_BREAK)
|
|
|
|
serial_receive_break(s);
|
|
|
|
}
|
|
|
|
|
|
|
|
static CPUReadMemoryFunc *slavio_serial_mem_read[3] = {
|
|
|
|
slavio_serial_mem_readb,
|
|
|
|
slavio_serial_mem_readb,
|
|
|
|
slavio_serial_mem_readb,
|
|
|
|
};
|
|
|
|
|
|
|
|
static CPUWriteMemoryFunc *slavio_serial_mem_write[3] = {
|
|
|
|
slavio_serial_mem_writeb,
|
|
|
|
slavio_serial_mem_writeb,
|
|
|
|
slavio_serial_mem_writeb,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void slavio_serial_save_chn(QEMUFile *f, ChannelState *s)
|
|
|
|
{
|
2007-04-07 22:14:41 +04:00
|
|
|
int tmp;
|
|
|
|
tmp = 0;
|
|
|
|
qemu_put_be32s(f, &tmp); /* unused, was IRQ. */
|
2004-12-20 02:18:01 +03:00
|
|
|
qemu_put_be32s(f, &s->reg);
|
|
|
|
qemu_put_be32s(f, &s->rxint);
|
|
|
|
qemu_put_be32s(f, &s->txint);
|
2006-09-09 15:38:11 +04:00
|
|
|
qemu_put_be32s(f, &s->rxint_under_svc);
|
|
|
|
qemu_put_be32s(f, &s->txint_under_svc);
|
2004-12-20 02:18:01 +03:00
|
|
|
qemu_put_8s(f, &s->rx);
|
|
|
|
qemu_put_8s(f, &s->tx);
|
|
|
|
qemu_put_buffer(f, s->wregs, 16);
|
|
|
|
qemu_put_buffer(f, s->rregs, 16);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void slavio_serial_save(QEMUFile *f, void *opaque)
|
|
|
|
{
|
|
|
|
SerialState *s = opaque;
|
|
|
|
|
|
|
|
slavio_serial_save_chn(f, &s->chn[0]);
|
|
|
|
slavio_serial_save_chn(f, &s->chn[1]);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int slavio_serial_load_chn(QEMUFile *f, ChannelState *s, int version_id)
|
|
|
|
{
|
2007-04-07 22:14:41 +04:00
|
|
|
int tmp;
|
|
|
|
|
2006-09-09 15:38:11 +04:00
|
|
|
if (version_id > 2)
|
2004-12-20 02:18:01 +03:00
|
|
|
return -EINVAL;
|
|
|
|
|
2007-04-07 22:14:41 +04:00
|
|
|
qemu_get_be32s(f, &tmp); /* unused */
|
2004-12-20 02:18:01 +03:00
|
|
|
qemu_get_be32s(f, &s->reg);
|
|
|
|
qemu_get_be32s(f, &s->rxint);
|
|
|
|
qemu_get_be32s(f, &s->txint);
|
2006-09-09 15:38:11 +04:00
|
|
|
if (version_id >= 2) {
|
|
|
|
qemu_get_be32s(f, &s->rxint_under_svc);
|
|
|
|
qemu_get_be32s(f, &s->txint_under_svc);
|
|
|
|
}
|
2004-12-20 02:18:01 +03:00
|
|
|
qemu_get_8s(f, &s->rx);
|
|
|
|
qemu_get_8s(f, &s->tx);
|
|
|
|
qemu_get_buffer(f, s->wregs, 16);
|
|
|
|
qemu_get_buffer(f, s->rregs, 16);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int slavio_serial_load(QEMUFile *f, void *opaque, int version_id)
|
|
|
|
{
|
|
|
|
SerialState *s = opaque;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = slavio_serial_load_chn(f, &s->chn[0], version_id);
|
|
|
|
if (ret != 0)
|
|
|
|
return ret;
|
|
|
|
ret = slavio_serial_load_chn(f, &s->chn[1], version_id);
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2007-04-07 22:14:41 +04:00
|
|
|
SerialState *slavio_serial_init(int base, qemu_irq irq, CharDriverState *chr1,
|
|
|
|
CharDriverState *chr2)
|
2004-12-20 02:18:01 +03:00
|
|
|
{
|
2005-04-07 00:42:35 +04:00
|
|
|
int slavio_serial_io_memory, i;
|
2004-12-20 02:18:01 +03:00
|
|
|
SerialState *s;
|
|
|
|
|
|
|
|
s = qemu_mallocz(sizeof(SerialState));
|
|
|
|
if (!s)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
slavio_serial_io_memory = cpu_register_io_memory(0, slavio_serial_mem_read, slavio_serial_mem_write, s);
|
|
|
|
cpu_register_physical_memory(base, SERIAL_MAXADDR, slavio_serial_io_memory);
|
|
|
|
|
2005-04-07 00:42:35 +04:00
|
|
|
s->chn[0].chr = chr1;
|
|
|
|
s->chn[1].chr = chr2;
|
|
|
|
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
|
|
s->chn[i].irq = irq;
|
|
|
|
s->chn[i].chn = 1 - i;
|
|
|
|
s->chn[i].type = ser;
|
|
|
|
if (s->chn[i].chr) {
|
2007-01-28 02:46:43 +03:00
|
|
|
qemu_chr_add_handlers(s->chn[i].chr, serial_can_receive,
|
|
|
|
serial_receive1, serial_event, &s->chn[i]);
|
2005-04-07 00:42:35 +04:00
|
|
|
}
|
2004-12-20 02:18:01 +03:00
|
|
|
}
|
2005-04-07 00:42:35 +04:00
|
|
|
s->chn[0].otherchn = &s->chn[1];
|
|
|
|
s->chn[1].otherchn = &s->chn[0];
|
2006-09-09 15:38:11 +04:00
|
|
|
register_savevm("slavio_serial", base, 2, slavio_serial_save, slavio_serial_load, s);
|
2004-12-20 02:18:01 +03:00
|
|
|
qemu_register_reset(slavio_serial_reset, s);
|
|
|
|
slavio_serial_reset(s);
|
|
|
|
return s;
|
|
|
|
}
|
|
|
|
|
2005-04-07 00:42:35 +04:00
|
|
|
static const uint8_t keycodes[128] = {
|
|
|
|
127, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 43, 53,
|
|
|
|
54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 89, 76, 77, 78,
|
|
|
|
79, 80, 81, 82, 83, 84, 85, 86, 87, 42, 99, 88, 100, 101, 102, 103,
|
|
|
|
104, 105, 106, 107, 108, 109, 110, 47, 19, 121, 119, 5, 6, 8, 10, 12,
|
|
|
|
14, 16, 17, 18, 7, 98, 23, 68, 69, 70, 71, 91, 92, 93, 125, 112,
|
|
|
|
113, 114, 94, 50, 0, 0, 124, 9, 11, 0, 0, 0, 0, 0, 0, 0,
|
|
|
|
90, 0, 46, 22, 13, 111, 52, 20, 96, 24, 28, 74, 27, 123, 44, 66,
|
|
|
|
0, 45, 2, 4, 48, 0, 0, 21, 0, 0, 0, 0, 0, 120, 122, 67,
|
|
|
|
};
|
|
|
|
|
2004-12-20 02:18:01 +03:00
|
|
|
static void sunkbd_event(void *opaque, int ch)
|
|
|
|
{
|
|
|
|
ChannelState *s = opaque;
|
2005-04-07 00:42:35 +04:00
|
|
|
int release = ch & 0x80;
|
|
|
|
|
|
|
|
ch = keycodes[ch & 0x7f];
|
|
|
|
KBD_DPRINTF("Keycode %d (%s)\n", ch, release? "release" : "press");
|
|
|
|
put_queue(s, ch | release);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void handle_kbd_command(ChannelState *s, int val)
|
|
|
|
{
|
|
|
|
KBD_DPRINTF("Command %d\n", val);
|
|
|
|
switch (val) {
|
|
|
|
case 1: // Reset, return type code
|
|
|
|
put_queue(s, 0xff);
|
|
|
|
put_queue(s, 5); // Type 5
|
|
|
|
break;
|
|
|
|
case 7: // Query layout
|
|
|
|
put_queue(s, 0xfe);
|
|
|
|
put_queue(s, 0x20); // XXX, layout?
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
2004-12-20 02:18:01 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static void sunmouse_event(void *opaque,
|
|
|
|
int dx, int dy, int dz, int buttons_state)
|
|
|
|
{
|
|
|
|
ChannelState *s = opaque;
|
|
|
|
int ch;
|
|
|
|
|
2006-09-09 15:38:11 +04:00
|
|
|
/* XXX: SDL sometimes generates nul events: we delete them */
|
|
|
|
if (dx == 0 && dy == 0 && dz == 0 && buttons_state == 0)
|
|
|
|
return;
|
2006-09-09 15:35:47 +04:00
|
|
|
MS_DPRINTF("dx=%d dy=%d buttons=%01x\n", dx, dy, buttons_state);
|
|
|
|
|
|
|
|
ch = 0x80 | 0x7; /* protocol start byte, no buttons pressed */
|
|
|
|
|
|
|
|
if (buttons_state & MOUSE_EVENT_LBUTTON)
|
|
|
|
ch ^= 0x4;
|
|
|
|
if (buttons_state & MOUSE_EVENT_MBUTTON)
|
|
|
|
ch ^= 0x2;
|
|
|
|
if (buttons_state & MOUSE_EVENT_RBUTTON)
|
|
|
|
ch ^= 0x1;
|
|
|
|
|
|
|
|
put_queue(s, ch);
|
|
|
|
|
|
|
|
ch = dx;
|
|
|
|
|
|
|
|
if (ch > 127)
|
|
|
|
ch=127;
|
|
|
|
else if (ch < -127)
|
|
|
|
ch=-127;
|
|
|
|
|
|
|
|
put_queue(s, ch & 0xff);
|
|
|
|
|
|
|
|
ch = -dy;
|
|
|
|
|
|
|
|
if (ch > 127)
|
|
|
|
ch=127;
|
|
|
|
else if (ch < -127)
|
|
|
|
ch=-127;
|
|
|
|
|
|
|
|
put_queue(s, ch & 0xff);
|
|
|
|
|
|
|
|
// MSC protocol specify two extra motion bytes
|
|
|
|
|
|
|
|
put_queue(s, 0);
|
|
|
|
put_queue(s, 0);
|
2004-12-20 02:18:01 +03:00
|
|
|
}
|
|
|
|
|
2007-04-07 22:14:41 +04:00
|
|
|
void slavio_serial_ms_kbd_init(int base, qemu_irq irq)
|
2004-12-20 02:18:01 +03:00
|
|
|
{
|
2005-04-07 00:42:35 +04:00
|
|
|
int slavio_serial_io_memory, i;
|
2004-12-20 02:18:01 +03:00
|
|
|
SerialState *s;
|
|
|
|
|
|
|
|
s = qemu_mallocz(sizeof(SerialState));
|
|
|
|
if (!s)
|
|
|
|
return;
|
2005-04-07 00:42:35 +04:00
|
|
|
for (i = 0; i < 2; i++) {
|
|
|
|
s->chn[i].irq = irq;
|
|
|
|
s->chn[i].chn = 1 - i;
|
|
|
|
s->chn[i].chr = NULL;
|
|
|
|
}
|
|
|
|
s->chn[0].otherchn = &s->chn[1];
|
|
|
|
s->chn[1].otherchn = &s->chn[0];
|
|
|
|
s->chn[0].type = mouse;
|
|
|
|
s->chn[1].type = kbd;
|
2004-12-20 02:18:01 +03:00
|
|
|
|
|
|
|
slavio_serial_io_memory = cpu_register_io_memory(0, slavio_serial_mem_read, slavio_serial_mem_write, s);
|
|
|
|
cpu_register_physical_memory(base, SERIAL_MAXADDR, slavio_serial_io_memory);
|
|
|
|
|
2007-01-05 19:42:13 +03:00
|
|
|
qemu_add_mouse_event_handler(sunmouse_event, &s->chn[0], 0, "QEMU Sun Mouse");
|
2005-04-07 00:42:35 +04:00
|
|
|
qemu_add_kbd_event_handler(sunkbd_event, &s->chn[1]);
|
2007-04-13 23:24:07 +04:00
|
|
|
register_savevm("slavio_serial_mouse", base, 2, slavio_serial_save, slavio_serial_load, s);
|
2004-12-20 02:18:01 +03:00
|
|
|
qemu_register_reset(slavio_serial_reset, s);
|
|
|
|
slavio_serial_reset(s);
|
|
|
|
}
|