2021-05-07 14:55:12 +03:00
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/*
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* PowerPC emulation for qemu: read/write callbacks for SPRs
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*
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* Copyright (C) 2021 Instituto de Pesquisas Eldorado
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef SPR_TCG_H
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#define SPR_TCG_H
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2021-05-07 14:55:51 +03:00
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#define SPR_NOACCESS (&spr_noaccess)
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2021-05-07 14:55:12 +03:00
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/* prototypes for readers and writers for SPRs */
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void spr_noaccess(DisasContext *ctx, int gprn, int sprn);
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void spr_read_generic(DisasContext *ctx, int gprn, int sprn);
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void spr_write_generic(DisasContext *ctx, int sprn, int gprn);
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target/ppc: PMU basic cycle count for pseries TCG
This patch adds the barebones of the PMU logic by enabling cycle
counting. The overall logic goes as follows:
- MMCR0 reg initial value is set to 0x80000000 (MMCR0_FC set) to avoid
having to spin the PMU right at system init;
- to retrieve the events that are being profiled, pmc_get_event() will
check the current MMCR0 and MMCR1 value and return the appropriate
PMUEventType. For PMCs 1-4, event 0x2 is the implementation dependent
value of PMU_EVENT_INSTRUCTIONS and event 0x1E is the implementation
dependent value of PMU_EVENT_CYCLES. These events are supported by IBM
Power chips since Power8, at least, and the Linux Perf driver makes use
of these events until kernel v5.15. For PMC1, event 0xF0 is the
architected PowerISA event for cycles. Event 0xFE is the architected
PowerISA event for instructions;
- if the counter is frozen, either via the global MMCR0_FC bit or its
individual frozen counter bits, PMU_EVENT_INACTIVE is returned;
- pmu_update_cycles() will go through each counter and update the
values of all PMCs that are counting cycles. This function will be
called every time a MMCR0 update is done to keep counters values
up to date. Upcoming patches will use this function to allow the
counters to be properly updated during read/write of the PMCs
and MMCR1 writes.
Given that the base CPU frequency is fixed at 1Ghz for both powernv and
pseries clock, cycle calculation assumes that 1 nanosecond equals 1 CPU
cycle. Cycle value is then calculated by adding the elapsed time, in
nanoseconds, of the last cycle update done via pmu_update_cycles().
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-3-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17 19:57:18 +03:00
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void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn);
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2021-12-17 19:57:18 +03:00
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void spr_write_PMC(DisasContext *ctx, int sprn, int gprn);
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2021-05-07 14:55:12 +03:00
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void spr_read_xer(DisasContext *ctx, int gprn, int sprn);
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void spr_write_xer(DisasContext *ctx, int sprn, int gprn);
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void spr_read_lr(DisasContext *ctx, int gprn, int sprn);
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void spr_write_lr(DisasContext *ctx, int sprn, int gprn);
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void spr_read_ctr(DisasContext *ctx, int gprn, int sprn);
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void spr_write_ctr(DisasContext *ctx, int sprn, int gprn);
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void spr_read_ureg(DisasContext *ctx, int gprn, int sprn);
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2021-10-18 04:01:20 +03:00
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void spr_read_MMCR0_ureg(DisasContext *ctx, int gprn, int sprn);
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2021-10-18 04:01:21 +03:00
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void spr_read_MMCR2_ureg(DisasContext *ctx, int gprn, int sprn);
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2021-12-17 19:57:18 +03:00
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void spr_read_PMC(DisasContext *ctx, int gprn, int sprn);
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2021-10-18 04:01:22 +03:00
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void spr_read_PMC14_ureg(DisasContext *ctx, int gprn, int sprn);
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void spr_read_PMC56_ureg(DisasContext *ctx, int gprn, int sprn);
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2021-05-07 14:55:12 +03:00
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void spr_read_tbl(DisasContext *ctx, int gprn, int sprn);
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void spr_read_tbu(DisasContext *ctx, int gprn, int sprn);
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void spr_read_atbl(DisasContext *ctx, int gprn, int sprn);
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void spr_read_atbu(DisasContext *ctx, int gprn, int sprn);
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void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn);
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void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn);
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void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn);
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void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn);
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2021-10-18 04:01:20 +03:00
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void spr_write_MMCR0_ureg(DisasContext *ctx, int sprn, int gprn);
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2021-10-18 04:01:21 +03:00
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void spr_write_MMCR2_ureg(DisasContext *ctx, int sprn, int gprn);
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2021-10-18 04:01:22 +03:00
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void spr_write_PMC14_ureg(DisasContext *ctx, int sprn, int gprn);
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void spr_write_PMC56_ureg(DisasContext *ctx, int sprn, int gprn);
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2021-05-07 14:55:12 +03:00
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#ifndef CONFIG_USER_ONLY
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void spr_write_generic32(DisasContext *ctx, int sprn, int gprn);
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void spr_write_clear(DisasContext *ctx, int sprn, int gprn);
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void spr_access_nop(DisasContext *ctx, int sprn, int gprn);
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void spr_read_decr(DisasContext *ctx, int gprn, int sprn);
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void spr_write_decr(DisasContext *ctx, int sprn, int gprn);
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void spr_write_tbl(DisasContext *ctx, int sprn, int gprn);
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void spr_write_tbu(DisasContext *ctx, int sprn, int gprn);
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void spr_write_atbl(DisasContext *ctx, int sprn, int gprn);
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void spr_write_atbu(DisasContext *ctx, int sprn, int gprn);
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void spr_read_ibat(DisasContext *ctx, int gprn, int sprn);
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void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn);
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void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn);
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void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn);
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void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn);
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void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn);
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void spr_read_dbat(DisasContext *ctx, int gprn, int sprn);
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void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn);
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void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn);
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void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn);
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void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn);
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void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn);
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void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn);
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void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn);
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void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn);
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void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn);
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void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn);
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void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn);
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void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn);
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void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn);
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void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn);
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void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn);
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void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn);
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void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn);
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void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn);
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void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn);
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void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn);
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void spr_write_pir(DisasContext *ctx, int sprn, int gprn);
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void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn);
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void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn);
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void spr_read_thrm(DisasContext *ctx, int gprn, int sprn);
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void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn);
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void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn);
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void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn);
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void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn);
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void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn);
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void spr_write_eplc(DisasContext *ctx, int sprn, int gprn);
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void spr_write_epsc(DisasContext *ctx, int sprn, int gprn);
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void spr_write_mas73(DisasContext *ctx, int sprn, int gprn);
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void spr_read_mas73(DisasContext *ctx, int gprn, int sprn);
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#ifdef TARGET_PPC64
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void spr_read_cfar(DisasContext *ctx, int gprn, int sprn);
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void spr_write_cfar(DisasContext *ctx, int sprn, int gprn);
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void spr_write_ureg(DisasContext *ctx, int sprn, int gprn);
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void spr_read_purr(DisasContext *ctx, int gprn, int sprn);
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void spr_write_purr(DisasContext *ctx, int sprn, int gprn);
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void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn);
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void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn);
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void spr_read_vtb(DisasContext *ctx, int gprn, int sprn);
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void spr_write_vtb(DisasContext *ctx, int sprn, int gprn);
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void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn);
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void spr_write_pidr(DisasContext *ctx, int sprn, int gprn);
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void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn);
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void spr_read_hior(DisasContext *ctx, int gprn, int sprn);
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void spr_write_hior(DisasContext *ctx, int sprn, int gprn);
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void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn);
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void spr_write_pcr(DisasContext *ctx, int sprn, int gprn);
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void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn);
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void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn);
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void spr_write_amr(DisasContext *ctx, int sprn, int gprn);
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void spr_write_uamor(DisasContext *ctx, int sprn, int gprn);
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void spr_write_iamr(DisasContext *ctx, int sprn, int gprn);
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#endif
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#endif
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#ifdef TARGET_PPC64
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void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn);
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void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn);
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void spr_read_tar(DisasContext *ctx, int gprn, int sprn);
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void spr_write_tar(DisasContext *ctx, int sprn, int gprn);
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void spr_read_tm(DisasContext *ctx, int gprn, int sprn);
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void spr_write_tm(DisasContext *ctx, int sprn, int gprn);
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void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn);
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void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn);
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void spr_read_ebb(DisasContext *ctx, int gprn, int sprn);
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void spr_write_ebb(DisasContext *ctx, int sprn, int gprn);
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void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn);
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void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn);
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void spr_write_hmer(DisasContext *ctx, int sprn, int gprn);
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void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn);
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#endif
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#endif
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