2007-09-17 01:08:06 +04:00
|
|
|
/*
|
2006-09-23 21:40:58 +04:00
|
|
|
* ARM RealView Baseboard System emulation.
|
|
|
|
*
|
2007-04-06 20:49:48 +04:00
|
|
|
* Copyright (c) 2006-2007 CodeSourcery.
|
2006-09-23 21:40:58 +04:00
|
|
|
* Written by Paul Brook
|
|
|
|
*
|
2011-06-26 06:21:35 +04:00
|
|
|
* This code is licensed under the GPL.
|
2006-09-23 21:40:58 +04:00
|
|
|
*/
|
|
|
|
|
2015-12-07 19:23:45 +03:00
|
|
|
#include "qemu/osdep.h"
|
include/qemu/osdep.h: Don't include qapi/error.h
Commit 57cb38b included qapi/error.h into qemu/osdep.h to get the
Error typedef. Since then, we've moved to include qemu/osdep.h
everywhere. Its file comment explains: "To avoid getting into
possible circular include dependencies, this file should not include
any other QEMU headers, with the exceptions of config-host.h,
compiler.h, os-posix.h and os-win32.h, all of which are doing a
similar job to this file and are under similar constraints."
qapi/error.h doesn't do a similar job, and it doesn't adhere to
similar constraints: it includes qapi-types.h. That's in excess of
100KiB of crap most .c files don't actually need.
Add the typedef to qemu/typedefs.h, and include that instead of
qapi/error.h. Include qapi/error.h in .c files that need it and don't
get it now. Include qapi-types.h in qom/object.h for uint16List.
Update scripts/clean-includes accordingly. Update it further to match
reality: replace config.h by config-target.h, add sysemu/os-posix.h,
sysemu/os-win32.h. Update the list of includes in the qemu/osdep.h
comment quoted above similarly.
This reduces the number of objects depending on qapi/error.h from "all
of them" to less than a third. Unfortunately, the number depending on
qapi-types.h shrinks only a little. More work is needed for that one.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
[Fix compilation without the spice devel packages. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-14 11:01:28 +03:00
|
|
|
#include "qapi/error.h"
|
2016-01-19 23:51:44 +03:00
|
|
|
#include "qemu-common.h"
|
|
|
|
#include "cpu.h"
|
2013-02-04 18:40:22 +04:00
|
|
|
#include "hw/sysbus.h"
|
2019-05-23 16:47:43 +03:00
|
|
|
#include "hw/arm/boot.h"
|
2013-02-05 20:06:20 +04:00
|
|
|
#include "hw/arm/primecell.h"
|
2019-04-12 19:54:13 +03:00
|
|
|
#include "hw/net/lan9118.h"
|
2019-04-12 19:54:16 +03:00
|
|
|
#include "hw/net/smc91c111.h"
|
2013-02-04 18:40:22 +04:00
|
|
|
#include "hw/pci/pci.h"
|
2012-10-24 10:43:34 +04:00
|
|
|
#include "net/net.h"
|
2012-12-17 21:20:04 +04:00
|
|
|
#include "sysemu/sysemu.h"
|
2013-02-04 18:40:22 +04:00
|
|
|
#include "hw/boards.h"
|
2013-02-05 20:06:20 +04:00
|
|
|
#include "hw/i2c/i2c.h"
|
2012-12-17 21:19:49 +04:00
|
|
|
#include "exec/address-spaces.h"
|
2014-03-17 20:31:45 +04:00
|
|
|
#include "qemu/error-report.h"
|
2016-06-06 18:59:31 +03:00
|
|
|
#include "hw/char/pl011.h"
|
2017-09-04 17:21:53 +03:00
|
|
|
#include "hw/cpu/a9mpcore.h"
|
|
|
|
#include "hw/intc/realview_gic.h"
|
2006-09-23 21:40:58 +04:00
|
|
|
|
2009-11-16 20:06:43 +03:00
|
|
|
#define SMP_BOOT_ADDR 0xe0000000
|
2012-01-14 00:52:40 +04:00
|
|
|
#define SMP_BOOTREG_ADDR 0x10000030
|
2009-11-20 03:45:54 +03:00
|
|
|
|
2006-09-23 21:40:58 +04:00
|
|
|
/* Board init. */
|
|
|
|
|
2008-04-15 00:27:51 +04:00
|
|
|
static struct arm_boot_info realview_binfo = {
|
2009-11-16 20:06:43 +03:00
|
|
|
.smp_loader_start = SMP_BOOT_ADDR,
|
2012-01-14 00:52:40 +04:00
|
|
|
.smp_bootreg_addr = SMP_BOOTREG_ADDR,
|
2008-04-15 00:27:51 +04:00
|
|
|
};
|
|
|
|
|
2009-11-19 19:45:21 +03:00
|
|
|
/* The following two lists must be consistent. */
|
2009-11-13 07:31:22 +03:00
|
|
|
enum realview_board_type {
|
|
|
|
BOARD_EB,
|
2009-11-16 20:06:43 +03:00
|
|
|
BOARD_EB_MPCORE,
|
2009-11-19 19:45:21 +03:00
|
|
|
BOARD_PB_A8,
|
|
|
|
BOARD_PBX_A9,
|
|
|
|
};
|
|
|
|
|
2009-12-04 23:44:44 +03:00
|
|
|
static const int realview_board_id[] = {
|
2009-11-19 19:45:21 +03:00
|
|
|
0x33b,
|
|
|
|
0x33b,
|
|
|
|
0x769,
|
|
|
|
0x76d
|
2009-11-13 07:31:22 +03:00
|
|
|
};
|
|
|
|
|
2014-05-07 18:42:57 +04:00
|
|
|
static void realview_init(MachineState *machine,
|
2012-10-30 11:45:07 +04:00
|
|
|
enum realview_board_type board_type)
|
2006-09-23 21:40:58 +04:00
|
|
|
{
|
2012-05-14 05:50:56 +04:00
|
|
|
ARMCPU *cpu = NULL;
|
|
|
|
CPUARMState *env;
|
2011-10-02 19:04:26 +04:00
|
|
|
MemoryRegion *sysmem = get_system_memory();
|
2014-12-11 15:07:52 +03:00
|
|
|
MemoryRegion *ram_lo;
|
2011-10-02 19:04:26 +04:00
|
|
|
MemoryRegion *ram_hi = g_new(MemoryRegion, 1);
|
|
|
|
MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
|
|
|
|
MemoryRegion *ram_hack = g_new(MemoryRegion, 1);
|
2011-10-28 13:55:38 +04:00
|
|
|
DeviceState *dev, *sysctl, *gpio2, *pl041;
|
2009-11-13 07:31:22 +03:00
|
|
|
SysBusDevice *busdev;
|
2009-05-15 01:35:08 +04:00
|
|
|
qemu_irq pic[64];
|
2011-02-21 23:57:53 +03:00
|
|
|
qemu_irq mmc_irq[2];
|
2013-06-06 12:48:51 +04:00
|
|
|
PCIBus *pci_bus = NULL;
|
2006-09-23 21:40:58 +04:00
|
|
|
NICInfo *nd;
|
2013-08-03 02:18:51 +04:00
|
|
|
I2CBus *i2c;
|
2006-09-23 21:40:58 +04:00
|
|
|
int n;
|
2009-11-16 20:06:43 +03:00
|
|
|
int done_nic = 0;
|
2007-11-11 03:04:49 +03:00
|
|
|
qemu_irq cpu_irq[4];
|
2009-11-19 19:45:21 +03:00
|
|
|
int is_mpcore = 0;
|
|
|
|
int is_pb = 0;
|
2009-11-13 06:30:33 +03:00
|
|
|
uint32_t proc_id = 0;
|
2009-11-16 20:06:43 +03:00
|
|
|
uint32_t sys_id;
|
|
|
|
ram_addr_t low_ram_size;
|
2014-05-07 18:42:57 +04:00
|
|
|
ram_addr_t ram_size = machine->ram_size;
|
2014-03-17 20:31:45 +04:00
|
|
|
hwaddr periphbase = 0;
|
2006-09-23 21:40:58 +04:00
|
|
|
|
2009-11-19 19:45:21 +03:00
|
|
|
switch (board_type) {
|
|
|
|
case BOARD_EB:
|
|
|
|
break;
|
|
|
|
case BOARD_EB_MPCORE:
|
|
|
|
is_mpcore = 1;
|
2014-03-17 20:31:45 +04:00
|
|
|
periphbase = 0x10100000;
|
2009-11-19 19:45:21 +03:00
|
|
|
break;
|
|
|
|
case BOARD_PB_A8:
|
|
|
|
is_pb = 1;
|
|
|
|
break;
|
|
|
|
case BOARD_PBX_A9:
|
|
|
|
is_mpcore = 1;
|
|
|
|
is_pb = 1;
|
2014-03-17 20:31:45 +04:00
|
|
|
periphbase = 0x1f000000;
|
2009-11-19 19:45:21 +03:00
|
|
|
break;
|
|
|
|
}
|
2014-03-17 20:31:45 +04:00
|
|
|
|
2009-11-13 07:31:22 +03:00
|
|
|
for (n = 0; n < smp_cpus; n++) {
|
2017-09-13 19:04:57 +03:00
|
|
|
Object *cpuobj = object_new(machine->cpu_type);
|
2014-03-17 20:31:45 +04:00
|
|
|
|
2014-12-16 02:09:51 +03:00
|
|
|
/* By default A9,A15 and ARM1176 CPUs have EL3 enabled. This board
|
|
|
|
* does not currently support EL3 so the CPU EL3 property is disabled
|
|
|
|
* before realization.
|
|
|
|
*/
|
|
|
|
if (object_property_find(cpuobj, "has_el3", NULL)) {
|
2015-09-11 16:04:45 +03:00
|
|
|
object_property_set_bool(cpuobj, false, "has_el3", &error_fatal);
|
2014-12-16 02:09:51 +03:00
|
|
|
}
|
|
|
|
|
2014-03-17 20:31:45 +04:00
|
|
|
if (is_pb && is_mpcore) {
|
2015-09-11 16:04:45 +03:00
|
|
|
object_property_set_int(cpuobj, periphbase, "reset-cbar",
|
|
|
|
&error_fatal);
|
2014-03-17 20:31:45 +04:00
|
|
|
}
|
|
|
|
|
2015-09-11 16:04:45 +03:00
|
|
|
object_property_set_bool(cpuobj, true, "realized", &error_fatal);
|
2014-03-17 20:31:45 +04:00
|
|
|
|
|
|
|
cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpuobj), ARM_CPU_IRQ);
|
2007-11-10 18:15:54 +03:00
|
|
|
}
|
2014-03-17 20:31:45 +04:00
|
|
|
cpu = ARM_CPU(first_cpu);
|
2012-05-14 05:50:56 +04:00
|
|
|
env = &cpu->env;
|
2009-11-13 06:30:33 +03:00
|
|
|
if (arm_feature(env, ARM_FEATURE_V7)) {
|
2009-11-19 19:45:21 +03:00
|
|
|
if (is_mpcore) {
|
|
|
|
proc_id = 0x0c000000;
|
|
|
|
} else {
|
|
|
|
proc_id = 0x0e000000;
|
|
|
|
}
|
2009-11-13 06:30:33 +03:00
|
|
|
} else if (arm_feature(env, ARM_FEATURE_V6K)) {
|
|
|
|
proc_id = 0x06000000;
|
|
|
|
} else if (arm_feature(env, ARM_FEATURE_V6)) {
|
|
|
|
proc_id = 0x04000000;
|
|
|
|
} else {
|
|
|
|
proc_id = 0x02000000;
|
|
|
|
}
|
2007-11-10 18:15:54 +03:00
|
|
|
|
2009-12-21 23:19:12 +03:00
|
|
|
if (is_pb && ram_size > 0x20000000) {
|
|
|
|
/* Core tile RAM. */
|
2014-12-11 15:07:52 +03:00
|
|
|
ram_lo = g_new(MemoryRegion, 1);
|
2009-12-21 23:19:12 +03:00
|
|
|
low_ram_size = ram_size - 0x20000000;
|
|
|
|
ram_size = 0x20000000;
|
2017-07-07 17:42:53 +03:00
|
|
|
memory_region_init_ram(ram_lo, NULL, "realview.lowmem", low_ram_size,
|
Fix bad error handling after memory_region_init_ram()
Symptom:
$ qemu-system-x86_64 -m 10000000
Unexpected error in ram_block_add() at /work/armbru/qemu/exec.c:1456:
upstream-qemu: cannot set up guest memory 'pc.ram': Cannot allocate memory
Aborted (core dumped)
Root cause: commit ef701d7 screwed up handling of out-of-memory
conditions. Before the commit, we report the error and exit(1), in
one place, ram_block_add(). The commit lifts the error handling up
the call chain some, to three places. Fine. Except it uses
&error_abort in these places, changing the behavior from exit(1) to
abort(), and thus undoing the work of commit 3922825 "exec: Don't
abort when we can't allocate guest memory".
The three places are:
* memory_region_init_ram()
Commit 4994653 (right after commit ef701d7) lifted the error
handling further, through memory_region_init_ram(), multiplying the
incorrect use of &error_abort. Later on, imitation of existing
(bad) code may have created more.
* memory_region_init_ram_ptr()
The &error_abort is still there.
* memory_region_init_rom_device()
Doesn't need fixing, because commit 33e0eb5 (soon after commit
ef701d7) lifted the error handling further, and in the process
changed it from &error_abort to passing it up the call chain.
Correct, because the callers are realize() methods.
Fix the error handling after memory_region_init_ram() with a
Coccinelle semantic patch:
@r@
expression mr, owner, name, size, err;
position p;
@@
memory_region_init_ram(mr, owner, name, size,
(
- &error_abort
+ &error_fatal
|
err@p
)
);
@script:python@
p << r.p;
@@
print "%s:%s:%s" % (p[0].file, p[0].line, p[0].column)
When the last argument is &error_abort, it gets replaced by
&error_fatal. This is the fix.
If the last argument is anything else, its position is reported. This
lets us check the fix is complete. Four positions get reported:
* ram_backend_memory_alloc()
Error is passed up the call chain, ultimately through
user_creatable_complete(). As far as I can tell, it's callers all
handle the error sanely.
* fsl_imx25_realize(), fsl_imx31_realize(), dp8393x_realize()
DeviceClass.realize() methods, errors handled sanely further up the
call chain.
We're good. Test case again behaves:
$ qemu-system-x86_64 -m 10000000
qemu-system-x86_64: cannot set up guest memory 'pc.ram': Cannot allocate memory
[Exit 1 ]
The next commits will repair the rest of commit ef701d7's damage.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <1441983105-26376-3-git-send-email-armbru@redhat.com>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
2015-09-11 17:51:43 +03:00
|
|
|
&error_fatal);
|
2011-10-02 19:04:26 +04:00
|
|
|
memory_region_add_subregion(sysmem, 0x20000000, ram_lo);
|
2009-12-21 23:19:12 +03:00
|
|
|
}
|
|
|
|
|
2017-07-07 17:42:53 +03:00
|
|
|
memory_region_init_ram(ram_hi, NULL, "realview.highmem", ram_size,
|
Fix bad error handling after memory_region_init_ram()
Symptom:
$ qemu-system-x86_64 -m 10000000
Unexpected error in ram_block_add() at /work/armbru/qemu/exec.c:1456:
upstream-qemu: cannot set up guest memory 'pc.ram': Cannot allocate memory
Aborted (core dumped)
Root cause: commit ef701d7 screwed up handling of out-of-memory
conditions. Before the commit, we report the error and exit(1), in
one place, ram_block_add(). The commit lifts the error handling up
the call chain some, to three places. Fine. Except it uses
&error_abort in these places, changing the behavior from exit(1) to
abort(), and thus undoing the work of commit 3922825 "exec: Don't
abort when we can't allocate guest memory".
The three places are:
* memory_region_init_ram()
Commit 4994653 (right after commit ef701d7) lifted the error
handling further, through memory_region_init_ram(), multiplying the
incorrect use of &error_abort. Later on, imitation of existing
(bad) code may have created more.
* memory_region_init_ram_ptr()
The &error_abort is still there.
* memory_region_init_rom_device()
Doesn't need fixing, because commit 33e0eb5 (soon after commit
ef701d7) lifted the error handling further, and in the process
changed it from &error_abort to passing it up the call chain.
Correct, because the callers are realize() methods.
Fix the error handling after memory_region_init_ram() with a
Coccinelle semantic patch:
@r@
expression mr, owner, name, size, err;
position p;
@@
memory_region_init_ram(mr, owner, name, size,
(
- &error_abort
+ &error_fatal
|
err@p
)
);
@script:python@
p << r.p;
@@
print "%s:%s:%s" % (p[0].file, p[0].line, p[0].column)
When the last argument is &error_abort, it gets replaced by
&error_fatal. This is the fix.
If the last argument is anything else, its position is reported. This
lets us check the fix is complete. Four positions get reported:
* ram_backend_memory_alloc()
Error is passed up the call chain, ultimately through
user_creatable_complete(). As far as I can tell, it's callers all
handle the error sanely.
* fsl_imx25_realize(), fsl_imx31_realize(), dp8393x_realize()
DeviceClass.realize() methods, errors handled sanely further up the
call chain.
We're good. Test case again behaves:
$ qemu-system-x86_64 -m 10000000
qemu-system-x86_64: cannot set up guest memory 'pc.ram': Cannot allocate memory
[Exit 1 ]
The next commits will repair the rest of commit ef701d7's damage.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <1441983105-26376-3-git-send-email-armbru@redhat.com>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
2015-09-11 17:51:43 +03:00
|
|
|
&error_fatal);
|
2009-11-16 20:06:43 +03:00
|
|
|
low_ram_size = ram_size;
|
|
|
|
if (low_ram_size > 0x10000000)
|
|
|
|
low_ram_size = 0x10000000;
|
2006-09-23 21:40:58 +04:00
|
|
|
/* SDRAM at address zero. */
|
2013-06-06 13:41:28 +04:00
|
|
|
memory_region_init_alias(ram_alias, NULL, "realview.alias",
|
2011-10-02 19:04:26 +04:00
|
|
|
ram_hi, 0, low_ram_size);
|
|
|
|
memory_region_add_subregion(sysmem, 0, ram_alias);
|
2009-11-16 20:06:43 +03:00
|
|
|
if (is_pb) {
|
|
|
|
/* And again at a high address. */
|
2011-10-02 19:04:26 +04:00
|
|
|
memory_region_add_subregion(sysmem, 0x70000000, ram_hi);
|
2009-11-16 20:06:43 +03:00
|
|
|
} else {
|
|
|
|
ram_size = low_ram_size;
|
|
|
|
}
|
2006-09-23 21:40:58 +04:00
|
|
|
|
2009-11-16 20:06:43 +03:00
|
|
|
sys_id = is_pb ? 0x01780500 : 0xc1400400;
|
2011-02-21 23:57:53 +03:00
|
|
|
sysctl = qdev_create(NULL, "realview_sysctl");
|
|
|
|
qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
|
|
|
|
qdev_prop_set_uint32(sysctl, "proc_id", proc_id);
|
2012-02-09 10:11:16 +04:00
|
|
|
qdev_init_nofail(sysctl);
|
2013-01-20 05:47:33 +04:00
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000);
|
2007-11-11 03:04:49 +03:00
|
|
|
|
2009-11-13 07:31:22 +03:00
|
|
|
if (is_mpcore) {
|
2017-09-04 17:21:53 +03:00
|
|
|
dev = qdev_create(NULL, is_pb ? TYPE_A9MPCORE_PRIV : "realview_mpcore");
|
2009-11-13 07:31:22 +03:00
|
|
|
qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
|
|
|
|
qdev_init_nofail(dev);
|
2013-01-20 05:47:33 +04:00
|
|
|
busdev = SYS_BUS_DEVICE(dev);
|
2012-02-16 13:56:09 +04:00
|
|
|
sysbus_mmio_map(busdev, 0, periphbase);
|
2009-11-13 07:31:22 +03:00
|
|
|
for (n = 0; n < smp_cpus; n++) {
|
|
|
|
sysbus_connect_irq(busdev, n, cpu_irq[n]);
|
|
|
|
}
|
2012-02-16 13:56:09 +04:00
|
|
|
sysbus_create_varargs("l2x0", periphbase + 0x2000, NULL);
|
|
|
|
/* Both A9 and 11MPCore put the GIC CPU i/f at base + 0x100 */
|
|
|
|
realview_binfo.gic_cpu_if_addr = periphbase + 0x100;
|
2007-11-11 03:04:49 +03:00
|
|
|
} else {
|
2009-11-16 20:06:43 +03:00
|
|
|
uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000;
|
|
|
|
/* For now just create the nIRQ GIC, and ignore the others. */
|
2017-09-04 17:21:53 +03:00
|
|
|
dev = sysbus_create_simple(TYPE_REALVIEW_GIC, gic_addr, cpu_irq[0]);
|
2009-05-15 01:35:08 +04:00
|
|
|
}
|
|
|
|
for (n = 0; n < 64; n++) {
|
2009-05-26 17:56:11 +04:00
|
|
|
pic[n] = qdev_get_gpio_in(dev, n);
|
2007-11-11 03:04:49 +03:00
|
|
|
}
|
|
|
|
|
2011-10-28 13:55:38 +04:00
|
|
|
pl041 = qdev_create(NULL, "pl041");
|
|
|
|
qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
|
|
|
|
qdev_init_nofail(pl041);
|
2013-01-20 05:47:33 +04:00
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000);
|
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[19]);
|
2011-10-28 13:55:38 +04:00
|
|
|
|
2009-05-15 01:35:07 +04:00
|
|
|
sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]);
|
|
|
|
sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]);
|
2006-09-23 21:40:58 +04:00
|
|
|
|
2018-04-20 17:52:43 +03:00
|
|
|
pl011_create(0x10009000, pic[12], serial_hd(0));
|
|
|
|
pl011_create(0x1000a000, pic[13], serial_hd(1));
|
|
|
|
pl011_create(0x1000b000, pic[14], serial_hd(2));
|
|
|
|
pl011_create(0x1000c000, pic[15], serial_hd(3));
|
2006-09-23 21:40:58 +04:00
|
|
|
|
|
|
|
/* DMA controller is optional, apparently. */
|
2018-08-20 13:24:33 +03:00
|
|
|
dev = qdev_create(NULL, "pl081");
|
|
|
|
object_property_set_link(OBJECT(dev), OBJECT(sysmem), "downstream",
|
|
|
|
&error_fatal);
|
|
|
|
qdev_init_nofail(dev);
|
|
|
|
busdev = SYS_BUS_DEVICE(dev);
|
|
|
|
sysbus_mmio_map(busdev, 0, 0x10030000);
|
|
|
|
sysbus_connect_irq(busdev, 0, pic[24]);
|
2006-09-23 21:40:58 +04:00
|
|
|
|
2009-05-15 01:35:07 +04:00
|
|
|
sysbus_create_simple("sp804", 0x10011000, pic[4]);
|
|
|
|
sysbus_create_simple("sp804", 0x10012000, pic[5]);
|
2006-09-23 21:40:58 +04:00
|
|
|
|
2011-02-21 23:57:53 +03:00
|
|
|
sysbus_create_simple("pl061", 0x10013000, pic[6]);
|
|
|
|
sysbus_create_simple("pl061", 0x10014000, pic[7]);
|
|
|
|
gpio2 = sysbus_create_simple("pl061", 0x10015000, pic[8]);
|
|
|
|
|
2011-07-22 19:36:54 +04:00
|
|
|
sysbus_create_simple("pl111", 0x10020000, pic[23]);
|
2006-09-23 21:40:58 +04:00
|
|
|
|
2011-02-21 23:57:53 +03:00
|
|
|
dev = sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL);
|
|
|
|
/* Wire up MMC card detect and read-only signals. These have
|
|
|
|
* to go to both the PL061 GPIO and the sysctl register.
|
|
|
|
* Note that the PL181 orders these lines (readonly,inserted)
|
|
|
|
* and the PL061 has them the other way about. Also the card
|
|
|
|
* detect line is inverted.
|
|
|
|
*/
|
|
|
|
mmc_irq[0] = qemu_irq_split(
|
|
|
|
qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT),
|
|
|
|
qdev_get_gpio_in(gpio2, 1));
|
|
|
|
mmc_irq[1] = qemu_irq_split(
|
|
|
|
qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN),
|
|
|
|
qemu_irq_invert(qdev_get_gpio_in(gpio2, 0)));
|
|
|
|
qdev_connect_gpio_out(dev, 0, mmc_irq[0]);
|
|
|
|
qdev_connect_gpio_out(dev, 1, mmc_irq[1]);
|
2007-04-06 20:49:48 +04:00
|
|
|
|
2009-05-15 01:35:07 +04:00
|
|
|
sysbus_create_simple("pl031", 0x10017000, pic[10]);
|
2007-06-30 21:32:17 +04:00
|
|
|
|
2009-11-16 20:06:43 +03:00
|
|
|
if (!is_pb) {
|
2011-09-01 21:36:53 +04:00
|
|
|
dev = qdev_create(NULL, "realview_pci");
|
2013-01-20 05:47:33 +04:00
|
|
|
busdev = SYS_BUS_DEVICE(dev);
|
2011-09-01 21:36:53 +04:00
|
|
|
qdev_init_nofail(dev);
|
2013-04-19 14:15:20 +04:00
|
|
|
sysbus_mmio_map(busdev, 0, 0x10019000); /* PCI controller registers */
|
2013-04-19 14:15:20 +04:00
|
|
|
sysbus_mmio_map(busdev, 1, 0x60000000); /* PCI self-config */
|
|
|
|
sysbus_mmio_map(busdev, 2, 0x61000000); /* PCI config */
|
|
|
|
sysbus_mmio_map(busdev, 3, 0x62000000); /* PCI I/O */
|
2013-04-19 14:15:20 +04:00
|
|
|
sysbus_mmio_map(busdev, 4, 0x63000000); /* PCI memory window 1 */
|
|
|
|
sysbus_mmio_map(busdev, 5, 0x64000000); /* PCI memory window 2 */
|
|
|
|
sysbus_mmio_map(busdev, 6, 0x68000000); /* PCI memory window 3 */
|
2011-09-01 21:36:53 +04:00
|
|
|
sysbus_connect_irq(busdev, 0, pic[48]);
|
|
|
|
sysbus_connect_irq(busdev, 1, pic[49]);
|
|
|
|
sysbus_connect_irq(busdev, 2, pic[50]);
|
|
|
|
sysbus_connect_irq(busdev, 3, pic[51]);
|
2009-11-16 20:06:43 +03:00
|
|
|
pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
|
2016-06-08 23:50:25 +03:00
|
|
|
if (machine_usb(machine)) {
|
2012-03-07 18:06:32 +04:00
|
|
|
pci_create_simple(pci_bus, -1, "pci-ohci");
|
2009-11-16 20:06:43 +03:00
|
|
|
}
|
|
|
|
n = drive_get_max_bus(IF_SCSI);
|
|
|
|
while (n >= 0) {
|
2018-09-19 20:20:58 +03:00
|
|
|
dev = DEVICE(pci_create_simple(pci_bus, -1, "lsi53c895a"));
|
|
|
|
lsi53c8xx_handle_legacy_cmdline(dev);
|
2009-11-16 20:06:43 +03:00
|
|
|
n--;
|
|
|
|
}
|
2006-09-23 21:40:58 +04:00
|
|
|
}
|
|
|
|
for(n = 0; n < nb_nics; n++) {
|
|
|
|
nd = &nd_table[n];
|
2009-01-13 22:39:36 +03:00
|
|
|
|
2011-03-22 21:21:58 +03:00
|
|
|
if (!done_nic && (!nd->model ||
|
|
|
|
strcmp(nd->model, is_pb ? "lan9118" : "smc91c111") == 0)) {
|
2009-11-16 20:06:43 +03:00
|
|
|
if (is_pb) {
|
|
|
|
lan9118_init(nd, 0x4e000000, pic[28]);
|
|
|
|
} else {
|
|
|
|
smc91c111_init(nd, 0x4e000000, pic[28]);
|
|
|
|
}
|
|
|
|
done_nic = 1;
|
2006-09-23 21:40:58 +04:00
|
|
|
} else {
|
2013-06-06 12:48:51 +04:00
|
|
|
if (pci_bus) {
|
|
|
|
pci_nic_init_nofail(nd, pci_bus, "rtl8139", NULL);
|
|
|
|
}
|
2006-09-23 21:40:58 +04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-04-20 19:38:52 +04:00
|
|
|
dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL);
|
2013-08-03 02:18:51 +04:00
|
|
|
i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
|
2009-11-20 03:45:54 +03:00
|
|
|
i2c_create_slave(i2c, "ds1338", 0x68);
|
|
|
|
|
2006-09-23 21:40:58 +04:00
|
|
|
/* Memory map for RealView Emulation Baseboard: */
|
|
|
|
/* 0x10000000 System registers. */
|
|
|
|
/* 0x10001000 System controller. */
|
2009-11-20 03:45:54 +03:00
|
|
|
/* 0x10002000 Two-Wire Serial Bus. */
|
2006-09-23 21:40:58 +04:00
|
|
|
/* 0x10003000 Reserved. */
|
|
|
|
/* 0x10004000 AACI. */
|
|
|
|
/* 0x10005000 MCI. */
|
|
|
|
/* 0x10006000 KMI0. */
|
|
|
|
/* 0x10007000 KMI1. */
|
2009-11-16 20:06:43 +03:00
|
|
|
/* 0x10008000 Character LCD. (EB) */
|
2006-09-23 21:40:58 +04:00
|
|
|
/* 0x10009000 UART0. */
|
|
|
|
/* 0x1000a000 UART1. */
|
|
|
|
/* 0x1000b000 UART2. */
|
|
|
|
/* 0x1000c000 UART3. */
|
|
|
|
/* 0x1000d000 SSPI. */
|
|
|
|
/* 0x1000e000 SCI. */
|
|
|
|
/* 0x1000f000 Reserved. */
|
|
|
|
/* 0x10010000 Watchdog. */
|
|
|
|
/* 0x10011000 Timer 0+1. */
|
|
|
|
/* 0x10012000 Timer 2+3. */
|
|
|
|
/* 0x10013000 GPIO 0. */
|
|
|
|
/* 0x10014000 GPIO 1. */
|
|
|
|
/* 0x10015000 GPIO 2. */
|
2009-11-16 20:06:43 +03:00
|
|
|
/* 0x10002000 Two-Wire Serial Bus - DVI. (PB) */
|
2007-06-30 21:32:17 +04:00
|
|
|
/* 0x10017000 RTC. */
|
2006-09-23 21:40:58 +04:00
|
|
|
/* 0x10018000 DMC. */
|
|
|
|
/* 0x10019000 PCI controller config. */
|
|
|
|
/* 0x10020000 CLCD. */
|
|
|
|
/* 0x10030000 DMA Controller. */
|
2009-11-16 20:06:43 +03:00
|
|
|
/* 0x10040000 GIC1. (EB) */
|
|
|
|
/* 0x10050000 GIC2. (EB) */
|
|
|
|
/* 0x10060000 GIC3. (EB) */
|
|
|
|
/* 0x10070000 GIC4. (EB) */
|
2006-09-23 21:40:58 +04:00
|
|
|
/* 0x10080000 SMC. */
|
2009-11-16 20:06:43 +03:00
|
|
|
/* 0x1e000000 GIC1. (PB) */
|
|
|
|
/* 0x1e001000 GIC2. (PB) */
|
|
|
|
/* 0x1e002000 GIC3. (PB) */
|
|
|
|
/* 0x1e003000 GIC4. (PB) */
|
2006-09-23 21:40:58 +04:00
|
|
|
/* 0x40000000 NOR flash. */
|
|
|
|
/* 0x44000000 DoC flash. */
|
|
|
|
/* 0x48000000 SRAM. */
|
|
|
|
/* 0x4c000000 Configuration flash. */
|
|
|
|
/* 0x4e000000 Ethernet. */
|
|
|
|
/* 0x4f000000 USB. */
|
|
|
|
/* 0x50000000 PISMO. */
|
|
|
|
/* 0x54000000 PISMO. */
|
|
|
|
/* 0x58000000 PISMO. */
|
|
|
|
/* 0x5c000000 PISMO. */
|
|
|
|
/* 0x60000000 PCI. */
|
2013-04-19 14:15:20 +04:00
|
|
|
/* 0x60000000 PCI Self Config. */
|
|
|
|
/* 0x61000000 PCI Config. */
|
|
|
|
/* 0x62000000 PCI IO. */
|
|
|
|
/* 0x63000000 PCI mem 0. */
|
|
|
|
/* 0x64000000 PCI mem 1. */
|
|
|
|
/* 0x68000000 PCI mem 2. */
|
2006-09-23 21:40:58 +04:00
|
|
|
|
2009-04-09 21:15:18 +04:00
|
|
|
/* ??? Hack to map an additional page of ram for the secondary CPU
|
|
|
|
startup code. I guess this works on real hardware because the
|
|
|
|
BootROM happens to be in ROM/flash or in memory that isn't clobbered
|
|
|
|
until after Linux boots the secondary CPUs. */
|
2017-07-07 17:42:53 +03:00
|
|
|
memory_region_init_ram(ram_hack, NULL, "realview.hack", 0x1000,
|
Fix bad error handling after memory_region_init_ram()
Symptom:
$ qemu-system-x86_64 -m 10000000
Unexpected error in ram_block_add() at /work/armbru/qemu/exec.c:1456:
upstream-qemu: cannot set up guest memory 'pc.ram': Cannot allocate memory
Aborted (core dumped)
Root cause: commit ef701d7 screwed up handling of out-of-memory
conditions. Before the commit, we report the error and exit(1), in
one place, ram_block_add(). The commit lifts the error handling up
the call chain some, to three places. Fine. Except it uses
&error_abort in these places, changing the behavior from exit(1) to
abort(), and thus undoing the work of commit 3922825 "exec: Don't
abort when we can't allocate guest memory".
The three places are:
* memory_region_init_ram()
Commit 4994653 (right after commit ef701d7) lifted the error
handling further, through memory_region_init_ram(), multiplying the
incorrect use of &error_abort. Later on, imitation of existing
(bad) code may have created more.
* memory_region_init_ram_ptr()
The &error_abort is still there.
* memory_region_init_rom_device()
Doesn't need fixing, because commit 33e0eb5 (soon after commit
ef701d7) lifted the error handling further, and in the process
changed it from &error_abort to passing it up the call chain.
Correct, because the callers are realize() methods.
Fix the error handling after memory_region_init_ram() with a
Coccinelle semantic patch:
@r@
expression mr, owner, name, size, err;
position p;
@@
memory_region_init_ram(mr, owner, name, size,
(
- &error_abort
+ &error_fatal
|
err@p
)
);
@script:python@
p << r.p;
@@
print "%s:%s:%s" % (p[0].file, p[0].line, p[0].column)
When the last argument is &error_abort, it gets replaced by
&error_fatal. This is the fix.
If the last argument is anything else, its position is reported. This
lets us check the fix is complete. Four positions get reported:
* ram_backend_memory_alloc()
Error is passed up the call chain, ultimately through
user_creatable_complete(). As far as I can tell, it's callers all
handle the error sanely.
* fsl_imx25_realize(), fsl_imx31_realize(), dp8393x_realize()
DeviceClass.realize() methods, errors handled sanely further up the
call chain.
We're good. Test case again behaves:
$ qemu-system-x86_64 -m 10000000
qemu-system-x86_64: cannot set up guest memory 'pc.ram': Cannot allocate memory
[Exit 1 ]
The next commits will repair the rest of commit ef701d7's damage.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <1441983105-26376-3-git-send-email-armbru@redhat.com>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
2015-09-11 17:51:43 +03:00
|
|
|
&error_fatal);
|
2011-10-02 19:04:26 +04:00
|
|
|
memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, ram_hack);
|
2009-04-09 21:15:18 +04:00
|
|
|
|
2008-04-15 00:27:51 +04:00
|
|
|
realview_binfo.ram_size = ram_size;
|
2014-05-07 18:42:57 +04:00
|
|
|
realview_binfo.kernel_filename = machine->kernel_filename;
|
|
|
|
realview_binfo.kernel_cmdline = machine->kernel_cmdline;
|
|
|
|
realview_binfo.initrd_filename = machine->initrd_filename;
|
2009-11-13 07:31:22 +03:00
|
|
|
realview_binfo.nb_cpus = smp_cpus;
|
2009-11-19 19:45:21 +03:00
|
|
|
realview_binfo.board_id = realview_board_id[board_type];
|
2009-12-21 23:19:12 +03:00
|
|
|
realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0);
|
2013-05-30 00:29:20 +04:00
|
|
|
arm_load_kernel(ARM_CPU(first_cpu), &realview_binfo);
|
2006-09-23 21:40:58 +04:00
|
|
|
}
|
|
|
|
|
2014-05-07 18:42:57 +04:00
|
|
|
static void realview_eb_init(MachineState *machine)
|
2009-11-13 07:31:22 +03:00
|
|
|
{
|
2014-05-07 18:42:57 +04:00
|
|
|
realview_init(machine, BOARD_EB);
|
2009-11-13 07:31:22 +03:00
|
|
|
}
|
|
|
|
|
2014-05-07 18:42:57 +04:00
|
|
|
static void realview_eb_mpcore_init(MachineState *machine)
|
2009-11-13 07:31:22 +03:00
|
|
|
{
|
2014-05-07 18:42:57 +04:00
|
|
|
realview_init(machine, BOARD_EB_MPCORE);
|
2009-11-13 07:31:22 +03:00
|
|
|
}
|
|
|
|
|
2014-05-07 18:42:57 +04:00
|
|
|
static void realview_pb_a8_init(MachineState *machine)
|
2009-11-16 20:06:43 +03:00
|
|
|
{
|
2014-05-07 18:42:57 +04:00
|
|
|
realview_init(machine, BOARD_PB_A8);
|
2009-11-16 20:06:43 +03:00
|
|
|
}
|
|
|
|
|
2014-05-07 18:42:57 +04:00
|
|
|
static void realview_pbx_a9_init(MachineState *machine)
|
2009-11-19 19:45:21 +03:00
|
|
|
{
|
2014-05-07 18:42:57 +04:00
|
|
|
realview_init(machine, BOARD_PBX_A9);
|
2009-11-19 19:45:21 +03:00
|
|
|
}
|
|
|
|
|
2015-09-19 11:49:44 +03:00
|
|
|
static void realview_eb_class_init(ObjectClass *oc, void *data)
|
2015-09-04 21:37:08 +03:00
|
|
|
{
|
2015-09-19 11:49:44 +03:00
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
|
2015-09-04 21:37:08 +03:00
|
|
|
mc->desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)";
|
|
|
|
mc->init = realview_eb_init;
|
|
|
|
mc->block_default_type = IF_SCSI;
|
2017-09-07 15:54:54 +03:00
|
|
|
mc->ignore_memory_transaction_failures = true;
|
2017-09-13 19:04:57 +03:00
|
|
|
mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
|
2015-09-04 21:37:08 +03:00
|
|
|
}
|
2009-11-13 07:31:22 +03:00
|
|
|
|
2015-09-19 11:49:44 +03:00
|
|
|
static const TypeInfo realview_eb_type = {
|
|
|
|
.name = MACHINE_TYPE_NAME("realview-eb"),
|
|
|
|
.parent = TYPE_MACHINE,
|
|
|
|
.class_init = realview_eb_class_init,
|
|
|
|
};
|
2009-05-21 03:38:09 +04:00
|
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2015-09-19 11:49:44 +03:00
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static void realview_eb_mpcore_class_init(ObjectClass *oc, void *data)
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2015-09-04 21:37:08 +03:00
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{
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2015-09-19 11:49:44 +03:00
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MachineClass *mc = MACHINE_CLASS(oc);
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2015-09-04 21:37:08 +03:00
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mc->desc = "ARM RealView Emulation Baseboard (ARM11MPCore)";
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mc->init = realview_eb_mpcore_init;
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mc->block_default_type = IF_SCSI;
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mc->max_cpus = 4;
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2017-09-07 15:54:54 +03:00
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mc->ignore_memory_transaction_failures = true;
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2017-09-13 19:04:57 +03:00
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mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm11mpcore");
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2015-09-04 21:37:08 +03:00
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}
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2009-11-19 19:45:21 +03:00
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2015-09-19 11:49:44 +03:00
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static const TypeInfo realview_eb_mpcore_type = {
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.name = MACHINE_TYPE_NAME("realview-eb-mpcore"),
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.parent = TYPE_MACHINE,
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.class_init = realview_eb_mpcore_class_init,
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};
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2015-09-04 21:37:08 +03:00
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2015-09-19 11:49:44 +03:00
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static void realview_pb_a8_class_init(ObjectClass *oc, void *data)
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2015-09-04 21:37:08 +03:00
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{
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2015-09-19 11:49:44 +03:00
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MachineClass *mc = MACHINE_CLASS(oc);
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2015-09-04 21:37:08 +03:00
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mc->desc = "ARM RealView Platform Baseboard for Cortex-A8";
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mc->init = realview_pb_a8_init;
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2017-09-07 15:54:54 +03:00
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mc->ignore_memory_transaction_failures = true;
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2017-09-13 19:04:57 +03:00
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mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a8");
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2015-09-04 21:37:08 +03:00
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}
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2015-09-19 11:49:44 +03:00
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static const TypeInfo realview_pb_a8_type = {
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.name = MACHINE_TYPE_NAME("realview-pb-a8"),
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.parent = TYPE_MACHINE,
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.class_init = realview_pb_a8_class_init,
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};
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2009-11-16 20:06:43 +03:00
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2015-09-19 11:49:44 +03:00
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static void realview_pbx_a9_class_init(ObjectClass *oc, void *data)
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2009-05-21 03:38:09 +04:00
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{
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2015-09-19 11:49:44 +03:00
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MachineClass *mc = MACHINE_CLASS(oc);
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2015-09-04 21:37:08 +03:00
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mc->desc = "ARM RealView Platform Baseboard Explore for Cortex-A9";
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mc->init = realview_pbx_a9_init;
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mc->max_cpus = 4;
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2017-09-07 15:54:54 +03:00
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mc->ignore_memory_transaction_failures = true;
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2017-09-13 19:04:57 +03:00
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mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
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2009-05-21 03:38:09 +04:00
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}
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2015-09-19 11:49:44 +03:00
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static const TypeInfo realview_pbx_a9_type = {
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.name = MACHINE_TYPE_NAME("realview-pbx-a9"),
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.parent = TYPE_MACHINE,
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.class_init = realview_pbx_a9_class_init,
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};
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static void realview_machine_init(void)
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{
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type_register_static(&realview_eb_type);
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type_register_static(&realview_eb_mpcore_type);
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type_register_static(&realview_pb_a8_type);
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type_register_static(&realview_pbx_a9_type);
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}
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2016-02-16 23:59:04 +03:00
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type_init(realview_machine_init)
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