2014-09-01 15:59:46 +04:00
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/*
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* Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdlib.h>
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#include "cpu.h"
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#include "qemu/host-utils.h"
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#include "exec/helper-proto.h"
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#include "exec/cpu_ldst.h"
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2014-09-26 23:36:09 +04:00
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/* Addressing mode helper */
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static uint16_t reverse16(uint16_t val)
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{
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uint8_t high = (uint8_t)(val >> 8);
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uint8_t low = (uint8_t)(val & 0xff);
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uint16_t rh, rl;
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rl = (uint16_t)((high * 0x0202020202ULL & 0x010884422010ULL) % 1023);
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rh = (uint16_t)((low * 0x0202020202ULL & 0x010884422010ULL) % 1023);
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return (rh << 8) | rl;
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}
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uint32_t helper_br_update(uint32_t reg)
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{
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uint32_t index = reg & 0xffff;
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uint32_t incr = reg >> 16;
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uint32_t new_index = reverse16(reverse16(index) + reverse16(incr));
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return reg - index + new_index;
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}
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uint32_t helper_circ_update(uint32_t reg, uint32_t off)
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{
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uint32_t index = reg & 0xffff;
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uint32_t length = reg >> 16;
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int32_t new_index = index + off;
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if (new_index < 0) {
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new_index += length;
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} else {
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new_index %= length;
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}
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return reg - index + new_index;
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}
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2014-09-01 15:59:52 +04:00
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#define SSOV(env, ret, arg, len) do { \
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int64_t max_pos = INT##len ##_MAX; \
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int64_t max_neg = INT##len ##_MIN; \
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if (arg > max_pos) { \
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env->PSW_USB_V = (1 << 31); \
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env->PSW_USB_SV = (1 << 31); \
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ret = (target_ulong)max_pos; \
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} else { \
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if (arg < max_neg) { \
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env->PSW_USB_V = (1 << 31); \
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env->PSW_USB_SV = (1 << 31); \
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ret = (target_ulong)max_neg; \
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} else { \
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env->PSW_USB_V = 0; \
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ret = (target_ulong)arg; \
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} \
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} \
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env->PSW_USB_AV = arg ^ arg * 2u; \
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env->PSW_USB_SAV |= env->PSW_USB_AV; \
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} while (0)
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target_ulong helper_add_ssov(CPUTriCoreState *env, target_ulong r1,
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target_ulong r2)
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{
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target_ulong ret;
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int64_t t1 = sextract64(r1, 0, 32);
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int64_t t2 = sextract64(r2, 0, 32);
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int64_t result = t1 + t2;
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SSOV(env, ret, result, 32);
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return ret;
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}
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target_ulong helper_sub_ssov(CPUTriCoreState *env, target_ulong r1,
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target_ulong r2)
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{
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target_ulong ret;
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int64_t t1 = sextract64(r1, 0, 32);
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int64_t t2 = sextract64(r2, 0, 32);
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int64_t result = t1 - t2;
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SSOV(env, ret, result, 32);
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return ret;
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}
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2014-09-01 15:59:55 +04:00
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/* context save area (CSA) related helpers */
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static int cdc_increment(target_ulong *psw)
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{
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if ((*psw & MASK_PSW_CDC) == 0x7f) {
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return 0;
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}
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(*psw)++;
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/* check for overflow */
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int lo = clo32((*psw & MASK_PSW_CDC) << (32 - 7));
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int mask = (1u << (7 - lo)) - 1;
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int count = *psw & mask;
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if (count == 0) {
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(*psw)--;
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return 1;
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}
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return 0;
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}
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static int cdc_decrement(target_ulong *psw)
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{
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if ((*psw & MASK_PSW_CDC) == 0x7f) {
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return 0;
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}
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/* check for underflow */
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int lo = clo32((*psw & MASK_PSW_CDC) << (32 - 7));
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int mask = (1u << (7 - lo)) - 1;
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int count = *psw & mask;
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if (count == 0) {
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return 1;
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}
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(*psw)--;
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return 0;
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}
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2014-09-01 16:00:00 +04:00
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static bool cdc_zero(target_ulong *psw)
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{
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int cdc = *psw & MASK_PSW_CDC;
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/* Returns TRUE if PSW.CDC.COUNT == 0 or if PSW.CDC ==
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7'b1111111, otherwise returns FALSE. */
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if (cdc == 0x7f) {
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return true;
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}
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/* find CDC.COUNT */
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int lo = clo32((*psw & MASK_PSW_CDC) << (32 - 7));
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int mask = (1u << (7 - lo)) - 1;
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int count = *psw & mask;
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return count == 0;
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}
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2014-09-26 23:04:51 +04:00
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static void save_context_upper(CPUTriCoreState *env, int ea)
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2014-09-01 15:59:55 +04:00
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{
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cpu_stl_data(env, ea, env->PCXI);
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cpu_stl_data(env, ea+4, env->PSW);
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cpu_stl_data(env, ea+8, env->gpr_a[10]);
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cpu_stl_data(env, ea+12, env->gpr_a[11]);
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cpu_stl_data(env, ea+16, env->gpr_d[8]);
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cpu_stl_data(env, ea+20, env->gpr_d[9]);
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cpu_stl_data(env, ea+24, env->gpr_d[10]);
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cpu_stl_data(env, ea+28, env->gpr_d[11]);
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cpu_stl_data(env, ea+32, env->gpr_a[12]);
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cpu_stl_data(env, ea+36, env->gpr_a[13]);
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cpu_stl_data(env, ea+40, env->gpr_a[14]);
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cpu_stl_data(env, ea+44, env->gpr_a[15]);
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cpu_stl_data(env, ea+48, env->gpr_d[12]);
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cpu_stl_data(env, ea+52, env->gpr_d[13]);
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cpu_stl_data(env, ea+56, env->gpr_d[14]);
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cpu_stl_data(env, ea+60, env->gpr_d[15]);
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}
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2014-09-26 23:04:51 +04:00
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static void save_context_lower(CPUTriCoreState *env, int ea)
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2014-09-01 15:59:58 +04:00
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{
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cpu_stl_data(env, ea, env->PCXI);
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2014-09-26 23:04:51 +04:00
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cpu_stl_data(env, ea+4, env->gpr_a[11]);
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2014-09-01 15:59:58 +04:00
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cpu_stl_data(env, ea+8, env->gpr_a[2]);
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cpu_stl_data(env, ea+12, env->gpr_a[3]);
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cpu_stl_data(env, ea+16, env->gpr_d[0]);
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cpu_stl_data(env, ea+20, env->gpr_d[1]);
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cpu_stl_data(env, ea+24, env->gpr_d[2]);
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cpu_stl_data(env, ea+28, env->gpr_d[3]);
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cpu_stl_data(env, ea+32, env->gpr_a[4]);
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cpu_stl_data(env, ea+36, env->gpr_a[5]);
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cpu_stl_data(env, ea+40, env->gpr_a[6]);
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cpu_stl_data(env, ea+44, env->gpr_a[7]);
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cpu_stl_data(env, ea+48, env->gpr_d[4]);
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cpu_stl_data(env, ea+52, env->gpr_d[5]);
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cpu_stl_data(env, ea+56, env->gpr_d[6]);
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cpu_stl_data(env, ea+60, env->gpr_d[7]);
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}
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2014-09-01 15:59:55 +04:00
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static void restore_context_upper(CPUTriCoreState *env, int ea,
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target_ulong *new_PCXI, target_ulong *new_PSW)
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{
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*new_PCXI = cpu_ldl_data(env, ea);
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*new_PSW = cpu_ldl_data(env, ea+4);
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env->gpr_a[10] = cpu_ldl_data(env, ea+8);
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env->gpr_a[11] = cpu_ldl_data(env, ea+12);
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env->gpr_d[8] = cpu_ldl_data(env, ea+16);
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env->gpr_d[9] = cpu_ldl_data(env, ea+20);
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env->gpr_d[10] = cpu_ldl_data(env, ea+24);
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env->gpr_d[11] = cpu_ldl_data(env, ea+28);
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env->gpr_a[12] = cpu_ldl_data(env, ea+32);
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env->gpr_a[13] = cpu_ldl_data(env, ea+36);
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env->gpr_a[14] = cpu_ldl_data(env, ea+40);
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env->gpr_a[15] = cpu_ldl_data(env, ea+44);
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env->gpr_d[12] = cpu_ldl_data(env, ea+48);
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env->gpr_d[13] = cpu_ldl_data(env, ea+52);
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env->gpr_d[14] = cpu_ldl_data(env, ea+56);
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env->gpr_d[15] = cpu_ldl_data(env, ea+60);
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}
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2014-09-26 23:26:31 +04:00
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static void restore_context_lower(CPUTriCoreState *env, int ea,
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target_ulong *ra, target_ulong *pcxi)
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{
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*pcxi = cpu_ldl_data(env, ea);
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*ra = cpu_ldl_data(env, ea+4);
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env->gpr_a[2] = cpu_ldl_data(env, ea+8);
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env->gpr_a[3] = cpu_ldl_data(env, ea+12);
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env->gpr_d[0] = cpu_ldl_data(env, ea+16);
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env->gpr_d[1] = cpu_ldl_data(env, ea+20);
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env->gpr_d[2] = cpu_ldl_data(env, ea+24);
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env->gpr_d[3] = cpu_ldl_data(env, ea+28);
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env->gpr_a[4] = cpu_ldl_data(env, ea+32);
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env->gpr_a[5] = cpu_ldl_data(env, ea+36);
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env->gpr_a[6] = cpu_ldl_data(env, ea+40);
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env->gpr_a[7] = cpu_ldl_data(env, ea+44);
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env->gpr_d[4] = cpu_ldl_data(env, ea+48);
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env->gpr_d[5] = cpu_ldl_data(env, ea+52);
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env->gpr_d[6] = cpu_ldl_data(env, ea+56);
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env->gpr_d[7] = cpu_ldl_data(env, ea+60);
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}
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2014-09-01 15:59:55 +04:00
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void helper_call(CPUTriCoreState *env, uint32_t next_pc)
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{
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target_ulong tmp_FCX;
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target_ulong ea;
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target_ulong new_FCX;
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target_ulong psw;
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psw = psw_read(env);
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/* if (FCX == 0) trap(FCU); */
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if (env->FCX == 0) {
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/* FCU trap */
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}
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/* if (PSW.CDE) then if (cdc_increment()) then trap(CDO); */
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if (psw & MASK_PSW_CDE) {
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if (cdc_increment(&psw)) {
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/* CDO trap */
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}
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}
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/* PSW.CDE = 1;*/
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psw |= MASK_PSW_CDE;
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/* tmp_FCX = FCX; */
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tmp_FCX = env->FCX;
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/* EA = {FCX.FCXS, 6'b0, FCX.FCXO, 6'b0}; */
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ea = ((env->FCX & MASK_FCX_FCXS) << 12) +
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((env->FCX & MASK_FCX_FCXO) << 6);
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2014-09-26 23:04:51 +04:00
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/* new_FCX = M(EA, word); */
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new_FCX = cpu_ldl_data(env, ea);
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/* M(EA, 16 * word) = {PCXI, PSW, A[10], A[11], D[8], D[9], D[10], D[11],
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A[12], A[13], A[14], A[15], D[12], D[13], D[14],
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D[15]}; */
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save_context_upper(env, ea);
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2014-09-01 15:59:55 +04:00
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/* PCXI.PCPN = ICR.CCPN; */
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env->PCXI = (env->PCXI & 0xffffff) +
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((env->ICR & MASK_ICR_CCPN) << 24);
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/* PCXI.PIE = ICR.IE; */
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env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE) +
|
|
|
|
|
((env->ICR & MASK_ICR_IE) << 15));
|
|
|
|
|
/* PCXI.UL = 1; */
|
|
|
|
|
env->PCXI |= MASK_PCXI_UL;
|
|
|
|
|
|
|
|
|
|
/* PCXI[19: 0] = FCX[19: 0]; */
|
|
|
|
|
env->PCXI = (env->PCXI & 0xfff00000) + (env->FCX & 0xfffff);
|
|
|
|
|
/* FCX[19: 0] = new_FCX[19: 0]; */
|
|
|
|
|
env->FCX = (env->FCX & 0xfff00000) + (new_FCX & 0xfffff);
|
|
|
|
|
/* A[11] = next_pc[31: 0]; */
|
|
|
|
|
env->gpr_a[11] = next_pc;
|
|
|
|
|
|
|
|
|
|
/* if (tmp_FCX == LCX) trap(FCD);*/
|
|
|
|
|
if (tmp_FCX == env->LCX) {
|
|
|
|
|
/* FCD trap */
|
|
|
|
|
}
|
|
|
|
|
psw_write(env, psw);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void helper_ret(CPUTriCoreState *env)
|
|
|
|
|
{
|
|
|
|
|
target_ulong ea;
|
|
|
|
|
target_ulong new_PCXI;
|
|
|
|
|
target_ulong new_PSW, psw;
|
|
|
|
|
|
|
|
|
|
psw = psw_read(env);
|
|
|
|
|
/* if (PSW.CDE) then if (cdc_decrement()) then trap(CDU);*/
|
|
|
|
|
if (env->PSW & MASK_PSW_CDE) {
|
|
|
|
|
if (cdc_decrement(&(env->PSW))) {
|
|
|
|
|
/* CDU trap */
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
/* if (PCXI[19: 0] == 0) then trap(CSU); */
|
|
|
|
|
if ((env->PCXI & 0xfffff) == 0) {
|
|
|
|
|
/* CSU trap */
|
|
|
|
|
}
|
|
|
|
|
/* if (PCXI.UL == 0) then trap(CTYP); */
|
|
|
|
|
if ((env->PCXI & MASK_PCXI_UL) == 0) {
|
|
|
|
|
/* CTYP trap */
|
|
|
|
|
}
|
|
|
|
|
/* PC = {A11 [31: 1], 1’b0}; */
|
|
|
|
|
env->PC = env->gpr_a[11] & 0xfffffffe;
|
|
|
|
|
|
|
|
|
|
/* EA = {PCXI.PCXS, 6'b0, PCXI.PCXO, 6'b0}; */
|
|
|
|
|
ea = ((env->PCXI & MASK_PCXI_PCXS) << 12) +
|
|
|
|
|
((env->PCXI & MASK_PCXI_PCXO) << 6);
|
|
|
|
|
/* {new_PCXI, new_PSW, A[10], A[11], D[8], D[9], D[10], D[11], A[12],
|
2014-09-26 23:04:51 +04:00
|
|
|
|
A[13], A[14], A[15], D[12], D[13], D[14], D[15]} = M(EA, 16 * word); */
|
2014-09-01 15:59:55 +04:00
|
|
|
|
restore_context_upper(env, ea, &new_PCXI, &new_PSW);
|
2014-09-26 23:04:51 +04:00
|
|
|
|
/* M(EA, word) = FCX; */
|
|
|
|
|
cpu_stl_data(env, ea, env->FCX);
|
2014-09-01 15:59:55 +04:00
|
|
|
|
/* FCX[19: 0] = PCXI[19: 0]; */
|
|
|
|
|
env->FCX = (env->FCX & 0xfff00000) + (env->PCXI & 0x000fffff);
|
|
|
|
|
/* PCXI = new_PCXI; */
|
|
|
|
|
env->PCXI = new_PCXI;
|
|
|
|
|
|
|
|
|
|
if (tricore_feature(env, TRICORE_FEATURE_13)) {
|
|
|
|
|
/* PSW = new_PSW */
|
|
|
|
|
psw_write(env, new_PSW);
|
|
|
|
|
} else {
|
|
|
|
|
/* PSW = {new_PSW[31:26], PSW[25:24], new_PSW[23:0]}; */
|
|
|
|
|
psw_write(env, (new_PSW & ~(0x3000000)) + (psw & (0x3000000)));
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2014-09-01 15:59:58 +04:00
|
|
|
|
void helper_bisr(CPUTriCoreState *env, uint32_t const9)
|
|
|
|
|
{
|
|
|
|
|
target_ulong tmp_FCX;
|
|
|
|
|
target_ulong ea;
|
|
|
|
|
target_ulong new_FCX;
|
|
|
|
|
|
|
|
|
|
if (env->FCX == 0) {
|
|
|
|
|
/* FCU trap */
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
tmp_FCX = env->FCX;
|
|
|
|
|
ea = ((env->FCX & 0xf0000) << 12) + ((env->FCX & 0xffff) << 6);
|
|
|
|
|
|
2014-09-26 23:04:51 +04:00
|
|
|
|
/* new_FCX = M(EA, word); */
|
|
|
|
|
new_FCX = cpu_ldl_data(env, ea);
|
|
|
|
|
/* M(EA, 16 * word) = {PCXI, A[11], A[2], A[3], D[0], D[1], D[2], D[3], A[4]
|
|
|
|
|
, A[5], A[6], A[7], D[4], D[5], D[6], D[7]}; */
|
|
|
|
|
save_context_lower(env, ea);
|
|
|
|
|
|
2014-09-01 15:59:58 +04:00
|
|
|
|
|
|
|
|
|
/* PCXI.PCPN = ICR.CCPN */
|
|
|
|
|
env->PCXI = (env->PCXI & 0xffffff) +
|
|
|
|
|
((env->ICR & MASK_ICR_CCPN) << 24);
|
|
|
|
|
/* PCXI.PIE = ICR.IE */
|
|
|
|
|
env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE) +
|
|
|
|
|
((env->ICR & MASK_ICR_IE) << 15));
|
|
|
|
|
/* PCXI.UL = 0 */
|
|
|
|
|
env->PCXI &= ~(MASK_PCXI_UL);
|
|
|
|
|
/* PCXI[19: 0] = FCX[19: 0] */
|
|
|
|
|
env->PCXI = (env->PCXI & 0xfff00000) + (env->FCX & 0xfffff);
|
|
|
|
|
/* FXC[19: 0] = new_FCX[19: 0] */
|
|
|
|
|
env->FCX = (env->FCX & 0xfff00000) + (new_FCX & 0xfffff);
|
|
|
|
|
/* ICR.IE = 1 */
|
|
|
|
|
env->ICR |= MASK_ICR_IE;
|
|
|
|
|
|
|
|
|
|
env->ICR |= const9; /* ICR.CCPN = const9[7: 0];*/
|
|
|
|
|
|
|
|
|
|
if (tmp_FCX == env->LCX) {
|
|
|
|
|
/* FCD trap */
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2014-09-01 16:00:00 +04:00
|
|
|
|
void helper_rfe(CPUTriCoreState *env)
|
|
|
|
|
{
|
|
|
|
|
target_ulong ea;
|
|
|
|
|
target_ulong new_PCXI;
|
|
|
|
|
target_ulong new_PSW;
|
|
|
|
|
/* if (PCXI[19: 0] == 0) then trap(CSU); */
|
|
|
|
|
if ((env->PCXI & 0xfffff) == 0) {
|
|
|
|
|
/* raise csu trap */
|
|
|
|
|
}
|
|
|
|
|
/* if (PCXI.UL == 0) then trap(CTYP); */
|
|
|
|
|
if ((env->PCXI & MASK_PCXI_UL) == 0) {
|
|
|
|
|
/* raise CTYP trap */
|
|
|
|
|
}
|
|
|
|
|
/* if (!cdc_zero() AND PSW.CDE) then trap(NEST); */
|
|
|
|
|
if (!cdc_zero(&(env->PSW)) && (env->PSW & MASK_PSW_CDE)) {
|
|
|
|
|
/* raise MNG trap */
|
|
|
|
|
}
|
|
|
|
|
/* ICR.IE = PCXI.PIE; */
|
|
|
|
|
env->ICR = (env->ICR & ~MASK_ICR_IE) + ((env->PCXI & MASK_PCXI_PIE) >> 15);
|
|
|
|
|
/* ICR.CCPN = PCXI.PCPN; */
|
|
|
|
|
env->ICR = (env->ICR & ~MASK_ICR_CCPN) +
|
|
|
|
|
((env->PCXI & MASK_PCXI_PCPN) >> 24);
|
|
|
|
|
/*EA = {PCXI.PCXS, 6'b0, PCXI.PCXO, 6'b0};*/
|
|
|
|
|
ea = ((env->PCXI & MASK_PCXI_PCXS) << 12) +
|
|
|
|
|
((env->PCXI & MASK_PCXI_PCXO) << 6);
|
|
|
|
|
/*{new_PCXI, PSW, A[10], A[11], D[8], D[9], D[10], D[11], A[12],
|
2014-09-26 23:04:51 +04:00
|
|
|
|
A[13], A[14], A[15], D[12], D[13], D[14], D[15]} = M(EA, 16 * word); */
|
2014-09-01 16:00:00 +04:00
|
|
|
|
restore_context_upper(env, ea, &new_PCXI, &new_PSW);
|
2014-09-26 23:04:51 +04:00
|
|
|
|
/* M(EA, word) = FCX;*/
|
|
|
|
|
cpu_stl_data(env, ea, env->FCX);
|
2014-09-01 16:00:00 +04:00
|
|
|
|
/* FCX[19: 0] = PCXI[19: 0]; */
|
|
|
|
|
env->FCX = (env->FCX & 0xfff00000) + (env->PCXI & 0x000fffff);
|
|
|
|
|
/* PCXI = new_PCXI; */
|
|
|
|
|
env->PCXI = new_PCXI;
|
|
|
|
|
/* write psw */
|
|
|
|
|
psw_write(env, new_PSW);
|
|
|
|
|
}
|
|
|
|
|
|
2014-09-26 23:26:31 +04:00
|
|
|
|
void helper_ldlcx(CPUTriCoreState *env, uint32_t ea)
|
|
|
|
|
{
|
|
|
|
|
uint32_t dummy;
|
|
|
|
|
/* insn doesn't load PCXI and RA */
|
|
|
|
|
restore_context_lower(env, ea, &dummy, &dummy);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void helper_lducx(CPUTriCoreState *env, uint32_t ea)
|
|
|
|
|
{
|
|
|
|
|
uint32_t dummy;
|
|
|
|
|
/* insn doesn't load PCXI and PSW */
|
|
|
|
|
restore_context_upper(env, ea, &dummy, &dummy);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void helper_stlcx(CPUTriCoreState *env, uint32_t ea)
|
|
|
|
|
{
|
|
|
|
|
save_context_lower(env, ea);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void helper_stucx(CPUTriCoreState *env, uint32_t ea)
|
|
|
|
|
{
|
|
|
|
|
save_context_upper(env, ea);
|
|
|
|
|
}
|
|
|
|
|
|
2014-09-01 15:59:48 +04:00
|
|
|
|
static inline void QEMU_NORETURN do_raise_exception_err(CPUTriCoreState *env,
|
|
|
|
|
uint32_t exception,
|
|
|
|
|
int error_code,
|
|
|
|
|
uintptr_t pc)
|
|
|
|
|
{
|
|
|
|
|
CPUState *cs = CPU(tricore_env_get_cpu(env));
|
|
|
|
|
cs->exception_index = exception;
|
|
|
|
|
env->error_code = error_code;
|
|
|
|
|
|
|
|
|
|
if (pc) {
|
|
|
|
|
/* now we have a real cpu fault */
|
|
|
|
|
cpu_restore_state(cs, pc);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
cpu_loop_exit(cs);
|
|
|
|
|
}
|
|
|
|
|
|
2014-09-01 15:59:46 +04:00
|
|
|
|
void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
|
|
|
|
|
uintptr_t retaddr)
|
|
|
|
|
{
|
2014-09-01 15:59:48 +04:00
|
|
|
|
int ret;
|
|
|
|
|
ret = cpu_tricore_handle_mmu_fault(cs, addr, is_write, mmu_idx);
|
|
|
|
|
if (ret) {
|
|
|
|
|
TriCoreCPU *cpu = TRICORE_CPU(cs);
|
|
|
|
|
CPUTriCoreState *env = &cpu->env;
|
|
|
|
|
do_raise_exception_err(env, cs->exception_index,
|
|
|
|
|
env->error_code, retaddr);
|
|
|
|
|
}
|
2014-09-01 15:59:46 +04:00
|
|
|
|
}
|