2013-02-28 22:23:14 +04:00
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/*
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* SD Association Host Standard Specification v2.0 controller emulation
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd.
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* Mitsyanko Igor <i.mitsyanko@samsung.com>
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* Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com>
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*
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* Based on MMC controller for Samsung S5PC1xx-based board emulation
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* by Alexey Merkulov and Vladimir Monakhov.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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2015-10-08 16:21:02 +03:00
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#ifndef SDHCI_INTERNAL_H
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#define SDHCI_INTERNAL_H
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2013-02-28 22:23:14 +04:00
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2018-02-08 19:47:57 +03:00
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#include "hw/registerfields.h"
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2013-02-28 22:23:14 +04:00
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/* R/W SDMA System Address register 0x0 */
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#define SDHC_SYSAD 0x00
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/* R/W Host DMA Buffer Boundary and Transfer Block Size Register 0x0 */
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#define SDHC_BLKSIZE 0x04
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/* R/W Blocks count for current transfer 0x0 */
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#define SDHC_BLKCNT 0x06
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/* R/W Command Argument Register 0x0 */
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#define SDHC_ARGUMENT 0x08
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/* R/W Transfer Mode Setting Register 0x0 */
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#define SDHC_TRNMOD 0x0C
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#define SDHC_TRNS_DMA 0x0001
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#define SDHC_TRNS_BLK_CNT_EN 0x0002
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#define SDHC_TRNS_ACMD12 0x0004
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2018-02-08 19:48:05 +03:00
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#define SDHC_TRNS_ACMD23 0x0008 /* since v3 */
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2013-02-28 22:23:14 +04:00
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#define SDHC_TRNS_READ 0x0010
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#define SDHC_TRNS_MULTI 0x0020
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2018-01-16 16:28:19 +03:00
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#define SDHC_TRNMOD_MASK 0x0037
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2013-02-28 22:23:14 +04:00
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/* R/W Command Register 0x0 */
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#define SDHC_CMDREG 0x0E
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#define SDHC_CMD_RSP_WITH_BUSY (3 << 0)
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#define SDHC_CMD_DATA_PRESENT (1 << 5)
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#define SDHC_CMD_SUSPEND (1 << 6)
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#define SDHC_CMD_RESUME (1 << 7)
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#define SDHC_CMD_ABORT ((1 << 6)|(1 << 7))
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#define SDHC_CMD_TYPE_MASK ((1 << 6)|(1 << 7))
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#define SDHC_COMMAND_TYPE(x) ((x) & SDHC_CMD_TYPE_MASK)
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/* ROC Response Register 0 0x0 */
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#define SDHC_RSPREG0 0x10
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/* ROC Response Register 1 0x0 */
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#define SDHC_RSPREG1 0x14
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/* ROC Response Register 2 0x0 */
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#define SDHC_RSPREG2 0x18
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/* ROC Response Register 3 0x0 */
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#define SDHC_RSPREG3 0x1C
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/* R/W Buffer Data Register 0x0 */
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#define SDHC_BDATA 0x20
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/* R/ROC Present State Register 0x000A0000 */
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#define SDHC_PRNSTS 0x24
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#define SDHC_CMD_INHIBIT 0x00000001
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#define SDHC_DATA_INHIBIT 0x00000002
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#define SDHC_DAT_LINE_ACTIVE 0x00000004
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2020-06-16 12:32:29 +03:00
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#define SDHC_IMX_CLOCK_GATE_OFF 0x00000080
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2013-02-28 22:23:14 +04:00
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#define SDHC_DOING_WRITE 0x00000100
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#define SDHC_DOING_READ 0x00000200
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#define SDHC_SPACE_AVAILABLE 0x00000400
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#define SDHC_DATA_AVAILABLE 0x00000800
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#define SDHC_CARD_PRESENT 0x00010000
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#define SDHC_CARD_DETECT 0x00040000
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#define SDHC_WRITE_PROTECT 0x00080000
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2018-02-08 19:48:10 +03:00
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FIELD(SDHC_PRNSTS, DAT_LVL, 20, 4);
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FIELD(SDHC_PRNSTS, CMD_LVL, 24, 1);
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2013-02-28 22:23:14 +04:00
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#define TRANSFERRING_DATA(x) \
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((x) & (SDHC_DOING_READ | SDHC_DOING_WRITE))
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/* R/W Host control Register 0x0 */
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#define SDHC_HOSTCTL 0x28
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2018-02-09 13:40:29 +03:00
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#define SDHC_CTRL_LED 0x01
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2018-02-08 19:47:58 +03:00
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#define SDHC_CTRL_DATATRANSFERWIDTH 0x02 /* SD mode only */
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#define SDHC_CTRL_HIGH_SPEED 0x04
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2013-02-28 22:23:14 +04:00
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#define SDHC_CTRL_DMA_CHECK_MASK 0x18
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#define SDHC_CTRL_SDMA 0x00
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2018-02-08 19:48:01 +03:00
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#define SDHC_CTRL_ADMA1_32 0x08 /* NOT ALLOWED since v2 */
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2013-02-28 22:23:14 +04:00
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#define SDHC_CTRL_ADMA2_32 0x10
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#define SDHC_CTRL_ADMA2_64 0x18
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#define SDHC_DMA_TYPE(x) ((x) & SDHC_CTRL_DMA_CHECK_MASK)
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2018-02-09 13:40:29 +03:00
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#define SDHC_CTRL_4BITBUS 0x02
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#define SDHC_CTRL_8BITBUS 0x20
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#define SDHC_CTRL_CDTEST_INS 0x40
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#define SDHC_CTRL_CDTEST_EN 0x80
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2013-02-28 22:23:14 +04:00
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/* R/W Power Control Register 0x0 */
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#define SDHC_PWRCON 0x29
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#define SDHC_POWER_ON (1 << 0)
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2018-02-08 19:47:58 +03:00
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FIELD(SDHC_PWRCON, BUS_VOLTAGE, 1, 3);
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2013-02-28 22:23:14 +04:00
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/* R/W Block Gap Control Register 0x0 */
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#define SDHC_BLKGAP 0x2A
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#define SDHC_STOP_AT_GAP_REQ 0x01
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#define SDHC_CONTINUE_REQ 0x02
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/* R/W WakeUp Control Register 0x0 */
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#define SDHC_WAKCON 0x2B
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#define SDHC_WKUP_ON_INS (1 << 1)
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#define SDHC_WKUP_ON_RMV (1 << 2)
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/* CLKCON */
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#define SDHC_CLKCON 0x2C
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#define SDHC_CLOCK_INT_STABLE 0x0002
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#define SDHC_CLOCK_INT_EN 0x0001
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#define SDHC_CLOCK_SDCLK_EN (1 << 2)
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#define SDHC_CLOCK_CHK_MASK 0x0007
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#define SDHC_CLOCK_IS_ON(x) \
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(((x) & SDHC_CLOCK_CHK_MASK) == SDHC_CLOCK_CHK_MASK)
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/* R/W Timeout Control Register 0x0 */
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#define SDHC_TIMEOUTCON 0x2E
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2018-02-08 19:47:58 +03:00
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FIELD(SDHC_TIMEOUTCON, COUNTER, 0, 4);
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2013-02-28 22:23:14 +04:00
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/* R/W Software Reset Register 0x0 */
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#define SDHC_SWRST 0x2F
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#define SDHC_RESET_ALL 0x01
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#define SDHC_RESET_CMD 0x02
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#define SDHC_RESET_DATA 0x04
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/* ROC/RW1C Normal Interrupt Status Register 0x0 */
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#define SDHC_NORINTSTS 0x30
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#define SDHC_NIS_ERR 0x8000
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#define SDHC_NIS_CMDCMP 0x0001
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#define SDHC_NIS_TRSCMP 0x0002
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#define SDHC_NIS_BLKGAP 0x0004
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#define SDHC_NIS_DMA 0x0008
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#define SDHC_NIS_WBUFRDY 0x0010
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#define SDHC_NIS_RBUFRDY 0x0020
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#define SDHC_NIS_INSERT 0x0040
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#define SDHC_NIS_REMOVE 0x0080
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#define SDHC_NIS_CARDINT 0x0100
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/* ROC/RW1C Error Interrupt Status Register 0x0 */
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#define SDHC_ERRINTSTS 0x32
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#define SDHC_EIS_CMDTIMEOUT 0x0001
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#define SDHC_EIS_BLKGAP 0x0004
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#define SDHC_EIS_CMDIDX 0x0008
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#define SDHC_EIS_CMD12ERR 0x0100
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#define SDHC_EIS_ADMAERR 0x0200
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/* R/W Normal Interrupt Status Enable Register 0x0 */
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#define SDHC_NORINTSTSEN 0x34
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#define SDHC_NISEN_CMDCMP 0x0001
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#define SDHC_NISEN_TRSCMP 0x0002
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#define SDHC_NISEN_DMA 0x0008
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#define SDHC_NISEN_WBUFRDY 0x0010
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#define SDHC_NISEN_RBUFRDY 0x0020
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#define SDHC_NISEN_INSERT 0x0040
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#define SDHC_NISEN_REMOVE 0x0080
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#define SDHC_NISEN_CARDINT 0x0100
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/* R/W Error Interrupt Status Enable Register 0x0 */
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#define SDHC_ERRINTSTSEN 0x36
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#define SDHC_EISEN_CMDTIMEOUT 0x0001
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#define SDHC_EISEN_BLKGAP 0x0004
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#define SDHC_EISEN_CMDIDX 0x0008
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#define SDHC_EISEN_ADMAERR 0x0200
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/* R/W Normal Interrupt Signal Enable Register 0x0 */
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#define SDHC_NORINTSIGEN 0x38
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#define SDHC_NORINTSIG_INSERT (1 << 6)
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#define SDHC_NORINTSIG_REMOVE (1 << 7)
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/* R/W Error Interrupt Signal Enable Register 0x0 */
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#define SDHC_ERRINTSIGEN 0x3A
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/* ROC Auto CMD12 error status register 0x0 */
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#define SDHC_ACMD12ERRSTS 0x3C
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2018-02-08 19:47:58 +03:00
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FIELD(SDHC_ACMD12ERRSTS, TIMEOUT_ERR, 1, 1);
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FIELD(SDHC_ACMD12ERRSTS, CRC_ERR, 2, 1);
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FIELD(SDHC_ACMD12ERRSTS, INDEX_ERR, 4, 1);
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2013-02-28 22:23:14 +04:00
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2018-02-08 19:48:07 +03:00
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/* Host Control Register 2 (since v3) */
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#define SDHC_HOSTCTL2 0x3E
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FIELD(SDHC_HOSTCTL2, UHS_MODE_SEL, 0, 3);
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FIELD(SDHC_HOSTCTL2, V18_ENA, 3, 1); /* UHS-I only */
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FIELD(SDHC_HOSTCTL2, DRIVER_STRENGTH, 4, 2); /* UHS-I only */
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FIELD(SDHC_HOSTCTL2, EXECUTE_TUNING, 6, 1); /* UHS-I only */
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FIELD(SDHC_HOSTCTL2, SAMPLING_CLKSEL, 7, 1); /* UHS-I only */
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2018-02-08 19:48:18 +03:00
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FIELD(SDHC_HOSTCTL2, UHS_II_ENA, 8, 1); /* since v4 */
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FIELD(SDHC_HOSTCTL2, ADMA2_LENGTH, 10, 1); /* since v4 */
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FIELD(SDHC_HOSTCTL2, CMD23_ENA, 11, 1); /* since v4 */
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FIELD(SDHC_HOSTCTL2, VERSION4, 12, 1); /* since v4 */
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2018-02-08 19:48:07 +03:00
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FIELD(SDHC_HOSTCTL2, ASYNC_INT, 14, 1);
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FIELD(SDHC_HOSTCTL2, PRESET_ENA, 15, 1);
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2013-02-28 22:23:14 +04:00
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/* HWInit Capabilities Register 0x05E80080 */
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2018-01-16 16:28:19 +03:00
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#define SDHC_CAPAB 0x40
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2018-02-08 19:47:58 +03:00
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FIELD(SDHC_CAPAB, TOCLKFREQ, 0, 6);
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FIELD(SDHC_CAPAB, TOUNIT, 7, 1);
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FIELD(SDHC_CAPAB, BASECLKFREQ, 8, 8);
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2018-02-08 19:47:57 +03:00
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FIELD(SDHC_CAPAB, MAXBLOCKLENGTH, 16, 2);
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2018-02-08 19:48:05 +03:00
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FIELD(SDHC_CAPAB, EMBEDDED_8BIT, 18, 1); /* since v3 */
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2018-02-08 19:48:01 +03:00
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FIELD(SDHC_CAPAB, ADMA2, 19, 1); /* since v2 */
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FIELD(SDHC_CAPAB, ADMA1, 20, 1); /* v1 only? */
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2018-02-08 19:47:58 +03:00
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FIELD(SDHC_CAPAB, HIGHSPEED, 21, 1);
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FIELD(SDHC_CAPAB, SDMA, 22, 1);
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FIELD(SDHC_CAPAB, SUSPRESUME, 23, 1);
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FIELD(SDHC_CAPAB, V33, 24, 1);
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FIELD(SDHC_CAPAB, V30, 25, 1);
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FIELD(SDHC_CAPAB, V18, 26, 1);
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2018-02-08 19:48:18 +03:00
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FIELD(SDHC_CAPAB, BUS64BIT_V4, 27, 1); /* since v4.10 */
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2018-02-08 19:48:01 +03:00
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FIELD(SDHC_CAPAB, BUS64BIT, 28, 1); /* since v2 */
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2018-02-08 19:48:05 +03:00
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FIELD(SDHC_CAPAB, ASYNC_INT, 29, 1); /* since v3 */
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FIELD(SDHC_CAPAB, SLOT_TYPE, 30, 2); /* since v3 */
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FIELD(SDHC_CAPAB, BUS_SPEED, 32, 3); /* since v3 */
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2018-02-08 19:48:18 +03:00
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FIELD(SDHC_CAPAB, UHS_II, 35, 8); /* since v4.20 */
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2018-02-08 19:48:05 +03:00
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FIELD(SDHC_CAPAB, DRIVER_STRENGTH, 36, 3); /* since v3 */
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FIELD(SDHC_CAPAB, DRIVER_TYPE_A, 36, 1); /* since v3 */
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FIELD(SDHC_CAPAB, DRIVER_TYPE_C, 37, 1); /* since v3 */
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FIELD(SDHC_CAPAB, DRIVER_TYPE_D, 38, 1); /* since v3 */
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FIELD(SDHC_CAPAB, TIMER_RETUNING, 40, 4); /* since v3 */
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FIELD(SDHC_CAPAB, SDR50_TUNING, 45, 1); /* since v3 */
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FIELD(SDHC_CAPAB, RETUNING_MODE, 46, 2); /* since v3 */
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FIELD(SDHC_CAPAB, CLOCK_MULT, 48, 8); /* since v3 */
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2018-02-08 19:48:18 +03:00
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FIELD(SDHC_CAPAB, ADMA3, 59, 1); /* since v4.20 */
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FIELD(SDHC_CAPAB, V18_VDD2, 60, 1); /* since v4.20 */
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2013-02-28 22:23:14 +04:00
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/* HWInit Maximum Current Capabilities Register 0x0 */
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#define SDHC_MAXCURR 0x48
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2018-02-08 19:47:58 +03:00
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FIELD(SDHC_MAXCURR, V33_VDD1, 0, 8);
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FIELD(SDHC_MAXCURR, V30_VDD1, 8, 8);
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FIELD(SDHC_MAXCURR, V18_VDD1, 16, 8);
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2018-02-08 19:48:18 +03:00
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FIELD(SDHC_MAXCURR, V18_VDD2, 32, 8); /* since v4.20 */
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2013-02-28 22:23:14 +04:00
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/* W Force Event Auto CMD12 Error Interrupt Register 0x0000 */
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#define SDHC_FEAER 0x50
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/* W Force Event Error Interrupt Register Error Interrupt 0x0000 */
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#define SDHC_FEERR 0x52
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/* R/W ADMA Error Status Register 0x00 */
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#define SDHC_ADMAERR 0x54
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#define SDHC_ADMAERR_LENGTH_MISMATCH (1 << 2)
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#define SDHC_ADMAERR_STATE_ST_STOP (0 << 0)
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#define SDHC_ADMAERR_STATE_ST_FDS (1 << 0)
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#define SDHC_ADMAERR_STATE_ST_TFR (3 << 0)
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#define SDHC_ADMAERR_STATE_MASK (3 << 0)
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/* R/W ADMA System Address Register 0x00 */
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#define SDHC_ADMASYSADDR 0x58
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#define SDHC_ADMA_ATTR_SET_LEN (1 << 4)
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#define SDHC_ADMA_ATTR_ACT_TRAN (1 << 5)
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#define SDHC_ADMA_ATTR_ACT_LINK (3 << 4)
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#define SDHC_ADMA_ATTR_INT (1 << 2)
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#define SDHC_ADMA_ATTR_END (1 << 1)
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#define SDHC_ADMA_ATTR_VALID (1 << 0)
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#define SDHC_ADMA_ATTR_ACT_MASK ((1 << 4)|(1 << 5))
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/* Slot interrupt status */
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#define SDHC_SLOT_INT_STATUS 0xFC
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2018-02-08 19:47:55 +03:00
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/* HWInit Host Controller Version Register */
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2013-02-28 22:23:14 +04:00
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#define SDHC_HCVER 0xFE
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2018-02-08 19:47:55 +03:00
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#define SDHC_HCVER_VENDOR 0x24
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2013-02-28 22:23:14 +04:00
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#define SDHC_REGISTERS_MAP_SIZE 0x100
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2016-03-21 19:02:30 +03:00
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#define SDHC_INSERTION_DELAY (NANOSECONDS_PER_SECOND)
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2013-02-28 22:23:14 +04:00
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#define SDHC_TRANSFER_DELAY 100
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#define SDHC_ADMA_DESCS_PER_DELAY 5
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#define SDHC_CMD_RESPONSE (3 << 0)
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enum {
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sdhc_not_stopped = 0, /* normal SDHC state */
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sdhc_gap_read = 1, /* SDHC stopped at block gap during read operation */
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sdhc_gap_write = 2 /* SDHC stopped at block gap during write operation */
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};
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2018-02-09 13:40:29 +03:00
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extern const VMStateDescription sdhci_vmstate;
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2019-02-20 14:19:14 +03:00
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/*
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* Default SD/MMC host controller features information, which will be
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* presented in CAPABILITIES register of generic SD host controller at reset.
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*
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* support:
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* - 3.3v and 1.8v voltages
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* - SDMA/ADMA1/ADMA2
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* - high-speed
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* max host controller R/W buffers size: 512B
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* max clock frequency for SDclock: 52 MHz
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* timeout clock frequency: 52 MHz
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*
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* does not support:
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* - 3.0v voltage
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* - 64-bit system bus
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* - suspend/resume
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*/
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#define SDHC_CAPAB_REG_DEFAULT 0x057834b4
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#define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \
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|
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DEFINE_PROP_UINT8("sd-spec-version", _state, sd_spec_version, 2), \
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|
|
DEFINE_PROP_UINT8("uhs", _state, uhs_mode, UHS_NOT_SUPPORTED), \
|
2020-06-16 12:32:29 +03:00
|
|
|
DEFINE_PROP_UINT8("vendor", _state, vendor, SDHCI_VENDOR_NONE), \
|
2019-02-20 14:19:14 +03:00
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\
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|
|
/* Capabilities registers provide information on supported
|
|
|
|
|
* features of this specific host controller implementation */ \
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|
|
DEFINE_PROP_UINT64("capareg", _state, capareg, SDHC_CAPAB_REG_DEFAULT), \
|
|
|
|
|
DEFINE_PROP_UINT64("maxcurr", _state, maxcurr, 0)
|
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|
|
void sdhci_initfn(SDHCIState *s);
|
|
|
|
|
void sdhci_uninitfn(SDHCIState *s);
|
|
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|
|
void sdhci_common_realize(SDHCIState *s, Error **errp);
|
qdev: Unrealize must not fail
Devices may have component devices and buses.
Device realization may fail. Realization is recursive: a device's
realize() method realizes its components, and device_set_realized()
realizes its buses (which should in turn realize the devices on that
bus, except bus_set_realized() doesn't implement that, yet).
When realization of a component or bus fails, we need to roll back:
unrealize everything we realized so far. If any of these unrealizes
failed, the device would be left in an inconsistent state. Must not
happen.
device_set_realized() lets it happen: it ignores errors in the roll
back code starting at label child_realize_fail.
Since realization is recursive, unrealization must be recursive, too.
But how could a partly failed unrealize be rolled back? We'd have to
re-realize, which can fail. This design is fundamentally broken.
device_set_realized() does not roll back at all. Instead, it keeps
unrealizing, ignoring further errors.
It can screw up even for a device with no buses: if the lone
dc->unrealize() fails, it still unregisters vmstate, and calls
listeners' unrealize() callback.
bus_set_realized() does not roll back either. Instead, it stops
unrealizing.
Fortunately, no unrealize method can fail, as we'll see below.
To fix the design error, drop parameter @errp from all the unrealize
methods.
Any unrealize method that uses @errp now needs an update. This leads
us to unrealize() methods that can fail. Merely passing it to another
unrealize method cannot cause failure, though. Here are the ones that
do other things with @errp:
* virtio_serial_device_unrealize()
Fails when qbus_set_hotplug_handler() fails, but still does all the
other work. On failure, the device would stay realized with its
resources completely gone. Oops. Can't happen, because
qbus_set_hotplug_handler() can't actually fail here. Pass
&error_abort to qbus_set_hotplug_handler() instead.
* hw/ppc/spapr_drc.c's unrealize()
Fails when object_property_del() fails, but all the other work is
already done. On failure, the device would stay realized with its
vmstate registration gone. Oops. Can't happen, because
object_property_del() can't actually fail here. Pass &error_abort
to object_property_del() instead.
* spapr_phb_unrealize()
Fails and bails out when remove_drcs() fails, but other work is
already done. On failure, the device would stay realized with some
of its resources gone. Oops. remove_drcs() fails only when
chassis_from_bus()'s object_property_get_uint() fails, and it can't
here. Pass &error_abort to remove_drcs() instead.
Therefore, no unrealize method can fail before this patch.
device_set_realized()'s recursive unrealization via bus uses
object_property_set_bool(). Can't drop @errp there, so pass
&error_abort.
We similarly unrealize with object_property_set_bool() elsewhere,
always ignoring errors. Pass &error_abort instead.
Several unrealize methods no longer handle errors from other unrealize
methods: virtio_9p_device_unrealize(),
virtio_input_device_unrealize(), scsi_qdev_unrealize(), ...
Much of the deleted error handling looks wrong anyway.
One unrealize methods no longer ignore such errors:
usb_ehci_pci_exit().
Several realize methods no longer ignore errors when rolling back:
v9fs_device_realize_common(), pci_qdev_unrealize(),
spapr_phb_realize(), usb_qdev_realize(), vfio_ccw_realize(),
virtio_device_realize().
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200505152926.18877-17-armbru@redhat.com>
2020-05-05 18:29:24 +03:00
|
|
|
void sdhci_common_unrealize(SDHCIState *s);
|
2019-02-20 14:19:14 +03:00
|
|
|
void sdhci_common_class_init(ObjectClass *klass, void *data);
|
|
|
|
|
|
2015-10-08 16:21:02 +03:00
|
|
|
#endif
|