247 lines
9.8 KiB
C
247 lines
9.8 KiB
C
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/*
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* Infineon tc27x SoC System emulation.
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*
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* Copyright (c) 2020 Andreas Konopik <andreas.konopik@efs-auto.de>
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* Copyright (c) 2020 David Brenken <david.brenken@efs-auto.de>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/sysbus.h"
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#include "hw/boards.h"
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#include "hw/loader.h"
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#include "qemu/units.h"
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#include "hw/misc/unimp.h"
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#include "exec/address-spaces.h"
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#include "qemu/log.h"
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#include "cpu.h"
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#include "hw/tricore/tc27x_soc.h"
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#include "hw/tricore/triboard.h"
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const MemmapEntry tc27x_soc_memmap[] = {
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[TC27XD_DSPR2] = { 0x50000000, 120 * KiB },
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[TC27XD_DCACHE2] = { 0x5001E000, 8 * KiB },
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[TC27XD_DTAG2] = { 0x500C0000, 0xC00 },
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[TC27XD_PSPR2] = { 0x50100000, 32 * KiB },
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[TC27XD_PCACHE2] = { 0x50108000, 16 * KiB },
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[TC27XD_PTAG2] = { 0x501C0000, 0x1800 },
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[TC27XD_DSPR1] = { 0x60000000, 120 * KiB },
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[TC27XD_DCACHE1] = { 0x6001E000, 8 * KiB },
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[TC27XD_DTAG1] = { 0x600C0000, 0xC00 },
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[TC27XD_PSPR1] = { 0x60100000, 32 * KiB },
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[TC27XD_PCACHE1] = { 0x60108000, 16 * KiB },
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[TC27XD_PTAG1] = { 0x601C0000, 0x1800 },
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[TC27XD_DSPR0] = { 0x70000000, 112 * KiB },
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[TC27XD_PSPR0] = { 0x70100000, 24 * KiB },
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[TC27XD_PCACHE0] = { 0x70106000, 8 * KiB },
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[TC27XD_PTAG0] = { 0x701C0000, 0xC00 },
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[TC27XD_PFLASH0_C] = { 0x80000000, 2 * MiB },
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[TC27XD_PFLASH1_C] = { 0x80200000, 2 * MiB },
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[TC27XD_OLDA_C] = { 0x8FE70000, 32 * KiB },
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[TC27XD_BROM_C] = { 0x8FFF8000, 32 * KiB },
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[TC27XD_LMURAM_C] = { 0x90000000, 32 * KiB },
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[TC27XD_EMEM_C] = { 0x9F000000, 1 * MiB },
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[TC27XD_PFLASH0_U] = { 0xA0000000, 0x0 },
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[TC27XD_PFLASH1_U] = { 0xA0200000, 0x0 },
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[TC27XD_DFLASH0] = { 0xAF000000, 1 * MiB + 16 * KiB },
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[TC27XD_DFLASH1] = { 0xAF110000, 64 * KiB },
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[TC27XD_OLDA_U] = { 0xAFE70000, 0x0 },
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[TC27XD_BROM_U] = { 0xAFFF8000, 0x0 },
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[TC27XD_LMURAM_U] = { 0xB0000000, 0x0 },
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[TC27XD_EMEM_U] = { 0xBF000000, 0x0 },
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[TC27XD_PSPRX] = { 0xC0000000, 0x0 },
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[TC27XD_DSPRX] = { 0xD0000000, 0x0 },
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};
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/*
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* Initialize the auxiliary ROM region @mr and map it into
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* the memory map at @base.
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*/
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static void make_rom(MemoryRegion *mr, const char *name,
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hwaddr base, hwaddr size)
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{
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memory_region_init_rom(mr, NULL, name, size, &error_fatal);
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memory_region_add_subregion(get_system_memory(), base, mr);
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}
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/*
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* Initialize the auxiliary RAM region @mr and map it into
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* the memory map at @base.
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*/
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static void make_ram(MemoryRegion *mr, const char *name,
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hwaddr base, hwaddr size)
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{
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memory_region_init_ram(mr, NULL, name, size, &error_fatal);
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memory_region_add_subregion(get_system_memory(), base, mr);
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}
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/*
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* Create an alias of an entire original MemoryRegion @orig
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* located at @base in the memory map.
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*/
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static void make_alias(MemoryRegion *mr, const char *name,
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MemoryRegion *orig, hwaddr base)
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{
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memory_region_init_alias(mr, NULL, name, orig, 0,
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memory_region_size(orig));
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memory_region_add_subregion(get_system_memory(), base, mr);
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}
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static void tc27x_soc_init_memory_mapping(DeviceState *dev_soc)
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{
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TC27XSoCState *s = TC27X_SOC(dev_soc);
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TC27XSoCClass *sc = TC27X_SOC_GET_CLASS(s);
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make_ram(&s->cpu0mem.dspr, "CPU0.DSPR",
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sc->memmap[TC27XD_DSPR0].base, sc->memmap[TC27XD_DSPR0].size);
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make_ram(&s->cpu0mem.pspr, "CPU0.PSPR",
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sc->memmap[TC27XD_PSPR0].base, sc->memmap[TC27XD_PSPR0].size);
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make_ram(&s->cpu1mem.dspr, "CPU1.DSPR",
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sc->memmap[TC27XD_DSPR1].base, sc->memmap[TC27XD_DSPR1].size);
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make_ram(&s->cpu1mem.pspr, "CPU1.PSPR",
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sc->memmap[TC27XD_PSPR1].base, sc->memmap[TC27XD_PSPR1].size);
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make_ram(&s->cpu2mem.dspr, "CPU2.DSPR",
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sc->memmap[TC27XD_DSPR2].base, sc->memmap[TC27XD_DSPR2].size);
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make_ram(&s->cpu2mem.pspr, "CPU2.PSPR",
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sc->memmap[TC27XD_PSPR2].base, sc->memmap[TC27XD_PSPR2].size);
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/* TODO: Control Cache mapping with Memory Test Unit (MTU) */
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make_ram(&s->cpu2mem.dcache, "CPU2.DCACHE",
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sc->memmap[TC27XD_DCACHE2].base, sc->memmap[TC27XD_DCACHE2].size);
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make_ram(&s->cpu2mem.dtag, "CPU2.DTAG",
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sc->memmap[TC27XD_DTAG2].base, sc->memmap[TC27XD_DTAG2].size);
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make_ram(&s->cpu2mem.pcache, "CPU2.PCACHE",
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sc->memmap[TC27XD_PCACHE2].base, sc->memmap[TC27XD_PCACHE2].size);
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make_ram(&s->cpu2mem.ptag, "CPU2.PTAG",
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sc->memmap[TC27XD_PTAG2].base, sc->memmap[TC27XD_PTAG2].size);
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make_ram(&s->cpu1mem.dcache, "CPU1.DCACHE",
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sc->memmap[TC27XD_DCACHE1].base, sc->memmap[TC27XD_DCACHE1].size);
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make_ram(&s->cpu1mem.dtag, "CPU1.DTAG",
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sc->memmap[TC27XD_DTAG1].base, sc->memmap[TC27XD_DTAG1].size);
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make_ram(&s->cpu1mem.pcache, "CPU1.PCACHE",
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sc->memmap[TC27XD_PCACHE1].base, sc->memmap[TC27XD_PCACHE1].size);
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make_ram(&s->cpu1mem.ptag, "CPU1.PTAG",
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sc->memmap[TC27XD_PTAG1].base, sc->memmap[TC27XD_PTAG1].size);
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make_ram(&s->cpu0mem.pcache, "CPU0.PCACHE",
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sc->memmap[TC27XD_PCACHE0].base, sc->memmap[TC27XD_PCACHE0].size);
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make_ram(&s->cpu0mem.ptag, "CPU0.PTAG",
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sc->memmap[TC27XD_PTAG0].base, sc->memmap[TC27XD_PTAG0].size);
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/*
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* TriCore QEMU executes CPU0 only, thus it is sufficient to map
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* LOCAL.PSPR/LOCAL.DSPR exclusively onto PSPR0/DSPR0.
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*/
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make_alias(&s->psprX, "LOCAL.PSPR", &s->cpu0mem.pspr,
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sc->memmap[TC27XD_PSPRX].base);
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make_alias(&s->dsprX, "LOCAL.DSPR", &s->cpu0mem.dspr,
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sc->memmap[TC27XD_DSPRX].base);
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make_ram(&s->flashmem.pflash0_c, "PF0",
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sc->memmap[TC27XD_PFLASH0_C].base, sc->memmap[TC27XD_PFLASH0_C].size);
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make_ram(&s->flashmem.pflash1_c, "PF1",
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sc->memmap[TC27XD_PFLASH1_C].base, sc->memmap[TC27XD_PFLASH1_C].size);
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make_ram(&s->flashmem.dflash0, "DF0",
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sc->memmap[TC27XD_DFLASH0].base, sc->memmap[TC27XD_DFLASH0].size);
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make_ram(&s->flashmem.dflash1, "DF1",
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sc->memmap[TC27XD_DFLASH1].base, sc->memmap[TC27XD_DFLASH1].size);
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make_ram(&s->flashmem.olda_c, "OLDA",
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sc->memmap[TC27XD_OLDA_C].base, sc->memmap[TC27XD_OLDA_C].size);
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make_rom(&s->flashmem.brom_c, "BROM",
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sc->memmap[TC27XD_BROM_C].base, sc->memmap[TC27XD_BROM_C].size);
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make_ram(&s->flashmem.lmuram_c, "LMURAM",
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sc->memmap[TC27XD_LMURAM_C].base, sc->memmap[TC27XD_LMURAM_C].size);
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make_ram(&s->flashmem.emem_c, "EMEM",
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sc->memmap[TC27XD_EMEM_C].base, sc->memmap[TC27XD_EMEM_C].size);
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make_alias(&s->flashmem.pflash0_u, "PF0.U", &s->flashmem.pflash0_c,
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sc->memmap[TC27XD_PFLASH0_U].base);
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make_alias(&s->flashmem.pflash1_u, "PF1.U", &s->flashmem.pflash1_c,
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sc->memmap[TC27XD_PFLASH1_U].base);
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make_alias(&s->flashmem.olda_u, "OLDA.U", &s->flashmem.olda_c,
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sc->memmap[TC27XD_OLDA_U].base);
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make_alias(&s->flashmem.brom_u, "BROM.U", &s->flashmem.brom_c,
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sc->memmap[TC27XD_BROM_U].base);
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make_alias(&s->flashmem.lmuram_u, "LMURAM.U", &s->flashmem.lmuram_c,
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sc->memmap[TC27XD_LMURAM_U].base);
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make_alias(&s->flashmem.emem_u, "EMEM.U", &s->flashmem.emem_c,
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sc->memmap[TC27XD_EMEM_U].base);
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}
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static void tc27x_soc_realize(DeviceState *dev_soc, Error **errp)
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{
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TC27XSoCState *s = TC27X_SOC(dev_soc);
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Error *err = NULL;
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qdev_realize(DEVICE(&s->cpu), NULL, &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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tc27x_soc_init_memory_mapping(dev_soc);
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}
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static void tc27x_soc_init(Object *obj)
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{
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TC27XSoCState *s = TC27X_SOC(obj);
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TC27XSoCClass *sc = TC27X_SOC_GET_CLASS(s);
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object_initialize_child(obj, "tc27x", &s->cpu, sc->cpu_type);
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}
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static Property tc27x_soc_properties[] = {
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DEFINE_PROP_END_OF_LIST(),
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};
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static void tc27x_soc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = tc27x_soc_realize;
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device_class_set_props(dc, tc27x_soc_properties);
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}
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static void tc277d_soc_class_init(ObjectClass *oc, void *data)
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{
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TC27XSoCClass *sc = TC27X_SOC_CLASS(oc);
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sc->name = "tc277d-soc";
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sc->cpu_type = TRICORE_CPU_TYPE_NAME("tc27x");
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sc->memmap = tc27x_soc_memmap;
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sc->num_cpus = 1;
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}
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static const TypeInfo tc27x_soc_types[] = {
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{
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.name = "tc277d-soc",
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.parent = TYPE_TC27X_SOC,
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.class_init = tc277d_soc_class_init,
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}, {
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.name = TYPE_TC27X_SOC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(TC27XSoCState),
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.instance_init = tc27x_soc_init,
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.class_size = sizeof(TC27XSoCClass),
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.class_init = tc27x_soc_class_init,
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.abstract = true,
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},
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};
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DEFINE_TYPES(tc27x_soc_types)
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