2021-09-23 23:34:56 +03:00
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/*
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* arm ELF definitions
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*
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* Copyright (c) 2013 Stacey D. Son
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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2022-05-06 16:49:09 +03:00
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#ifndef TARGET_ARCH_ELF_H
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#define TARGET_ARCH_ELF_H
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2021-09-23 23:34:56 +03:00
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#define ELF_START_MMAP 0x80000000
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#define ELF_ET_DYN_LOAD_ADDR 0x500000
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#define elf_check_arch(x) ((x) == EM_ARM)
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#define ELF_CLASS ELFCLASS32
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#define ELF_DATA ELFDATA2LSB
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#define ELF_ARCH EM_ARM
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#define USE_ELF_CORE_DUMP
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#define ELF_EXEC_PAGESIZE 4096
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2021-09-23 23:42:42 +03:00
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#define ELF_HWCAP get_elf_hwcap()
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2021-09-23 23:48:18 +03:00
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#define ELF_HWCAP2 get_elf_hwcap2()
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2021-09-23 23:42:42 +03:00
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#define GET_FEATURE(feat, hwcap) \
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do { if (arm_feature(&cpu->env, feat)) { hwcaps |= hwcap; } } while (0)
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#define GET_FEATURE_ID(feat, hwcap) \
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do { if (cpu_isar_feature(feat, cpu)) { hwcaps |= hwcap; } } while (0)
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enum {
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ARM_HWCAP_ARM_SWP = 1 << 0,
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ARM_HWCAP_ARM_HALF = 1 << 1,
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ARM_HWCAP_ARM_THUMB = 1 << 2,
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ARM_HWCAP_ARM_26BIT = 1 << 3,
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ARM_HWCAP_ARM_FAST_MULT = 1 << 4,
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ARM_HWCAP_ARM_FPA = 1 << 5,
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ARM_HWCAP_ARM_VFP = 1 << 6,
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ARM_HWCAP_ARM_EDSP = 1 << 7,
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ARM_HWCAP_ARM_JAVA = 1 << 8,
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ARM_HWCAP_ARM_IWMMXT = 1 << 9,
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ARM_HWCAP_ARM_CRUNCH = 1 << 10,
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ARM_HWCAP_ARM_THUMBEE = 1 << 11,
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ARM_HWCAP_ARM_NEON = 1 << 12,
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ARM_HWCAP_ARM_VFPv3 = 1 << 13,
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ARM_HWCAP_ARM_VFPv3D16 = 1 << 14,
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ARM_HWCAP_ARM_TLS = 1 << 15,
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ARM_HWCAP_ARM_VFPv4 = 1 << 16,
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ARM_HWCAP_ARM_IDIVA = 1 << 17,
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ARM_HWCAP_ARM_IDIVT = 1 << 18,
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ARM_HWCAP_ARM_VFPD32 = 1 << 19,
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ARM_HWCAP_ARM_LPAE = 1 << 20,
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ARM_HWCAP_ARM_EVTSTRM = 1 << 21,
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};
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2021-09-23 23:48:18 +03:00
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enum {
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ARM_HWCAP2_ARM_AES = 1 << 0,
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ARM_HWCAP2_ARM_PMULL = 1 << 1,
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ARM_HWCAP2_ARM_SHA1 = 1 << 2,
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ARM_HWCAP2_ARM_SHA2 = 1 << 3,
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ARM_HWCAP2_ARM_CRC32 = 1 << 4,
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};
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2021-09-23 23:42:42 +03:00
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static uint32_t get_elf_hwcap(void)
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{
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ARMCPU *cpu = ARM_CPU(thread_cpu);
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uint32_t hwcaps = 0;
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hwcaps |= ARM_HWCAP_ARM_SWP;
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hwcaps |= ARM_HWCAP_ARM_HALF;
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hwcaps |= ARM_HWCAP_ARM_THUMB;
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hwcaps |= ARM_HWCAP_ARM_FAST_MULT;
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/* probe for the extra features */
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/* EDSP is in v5TE and above */
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GET_FEATURE(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP);
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GET_FEATURE(ARM_FEATURE_IWMMXT, ARM_HWCAP_ARM_IWMMXT);
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GET_FEATURE(ARM_FEATURE_THUMB2EE, ARM_HWCAP_ARM_THUMBEE);
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GET_FEATURE(ARM_FEATURE_NEON, ARM_HWCAP_ARM_NEON);
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GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS);
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GET_FEATURE(ARM_FEATURE_LPAE, ARM_HWCAP_ARM_LPAE);
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GET_FEATURE_ID(aa32_arm_div, ARM_HWCAP_ARM_IDIVA);
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GET_FEATURE_ID(aa32_thumb_div, ARM_HWCAP_ARM_IDIVT);
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GET_FEATURE_ID(aa32_vfp, ARM_HWCAP_ARM_VFP);
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if (cpu_isar_feature(aa32_fpsp_v3, cpu) ||
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cpu_isar_feature(aa32_fpdp_v3, cpu)) {
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hwcaps |= ARM_HWCAP_ARM_VFPv3;
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if (cpu_isar_feature(aa32_simd_r32, cpu)) {
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hwcaps |= ARM_HWCAP_ARM_VFPD32;
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} else {
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hwcaps |= ARM_HWCAP_ARM_VFPv3D16;
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}
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}
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GET_FEATURE_ID(aa32_simdfmac, ARM_HWCAP_ARM_VFPv4);
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return hwcaps;
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}
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2021-09-23 23:48:18 +03:00
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static uint32_t get_elf_hwcap2(void)
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{
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ARMCPU *cpu = ARM_CPU(thread_cpu);
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uint32_t hwcaps = 0;
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GET_FEATURE_ID(aa32_aes, ARM_HWCAP2_ARM_AES);
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GET_FEATURE_ID(aa32_pmull, ARM_HWCAP2_ARM_PMULL);
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GET_FEATURE_ID(aa32_sha1, ARM_HWCAP2_ARM_SHA1);
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GET_FEATURE_ID(aa32_sha2, ARM_HWCAP2_ARM_SHA2);
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GET_FEATURE_ID(aa32_crc32, ARM_HWCAP2_ARM_CRC32);
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return hwcaps;
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}
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2021-09-23 23:42:42 +03:00
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#undef GET_FEATURE
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#undef GET_FEATURE_ID
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2021-09-23 23:34:56 +03:00
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2022-05-06 16:49:09 +03:00
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#endif /* TARGET_ARCH_ELF_H */
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