2018-04-11 21:56:33 +03:00
|
|
|
/*
|
|
|
|
* qemu user cpu loop
|
|
|
|
*
|
|
|
|
* Copyright (c) 2003-2008 Fabrice Bellard
|
|
|
|
*
|
|
|
|
* This program is free software; you can redistribute it and/or modify
|
|
|
|
* it under the terms of the GNU General Public License as published by
|
|
|
|
* the Free Software Foundation; either version 2 of the License, or
|
|
|
|
* (at your option) any later version.
|
|
|
|
*
|
|
|
|
* This program is distributed in the hope that it will be useful,
|
|
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
|
|
* GNU General Public License for more details.
|
|
|
|
*
|
|
|
|
* You should have received a copy of the GNU General Public License
|
|
|
|
* along with this program; if not, see <http://www.gnu.org/licenses/>.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include "qemu/osdep.h"
|
2019-05-23 17:35:08 +03:00
|
|
|
#include "qemu-common.h"
|
2019-03-16 04:20:46 +03:00
|
|
|
#include "qemu/error-report.h"
|
2018-04-11 21:56:33 +03:00
|
|
|
#include "qemu.h"
|
2021-09-08 18:44:03 +03:00
|
|
|
#include "user-internals.h"
|
2018-04-11 21:56:33 +03:00
|
|
|
#include "cpu_loop-common.h"
|
2021-09-08 18:43:59 +03:00
|
|
|
#include "signal-common.h"
|
2019-03-16 04:20:46 +03:00
|
|
|
#include "elf.h"
|
2021-03-05 16:54:49 +03:00
|
|
|
#include "semihosting/common-semi.h"
|
2018-04-11 21:56:33 +03:00
|
|
|
|
2018-04-11 21:56:49 +03:00
|
|
|
void cpu_loop(CPURISCVState *env)
|
|
|
|
{
|
2019-03-23 05:11:37 +03:00
|
|
|
CPUState *cs = env_cpu(env);
|
2018-04-11 21:56:49 +03:00
|
|
|
int trapnr, signum, sigcode;
|
|
|
|
target_ulong sigaddr;
|
|
|
|
target_ulong ret;
|
|
|
|
|
|
|
|
for (;;) {
|
|
|
|
cpu_exec_start(cs);
|
|
|
|
trapnr = cpu_exec(cs);
|
|
|
|
cpu_exec_end(cs);
|
|
|
|
process_queued_cpu_work(cs);
|
|
|
|
|
|
|
|
signum = 0;
|
|
|
|
sigcode = 0;
|
|
|
|
sigaddr = 0;
|
|
|
|
|
|
|
|
switch (trapnr) {
|
|
|
|
case EXCP_INTERRUPT:
|
|
|
|
/* just indicate that signals should be handled asap */
|
|
|
|
break;
|
|
|
|
case EXCP_ATOMIC:
|
|
|
|
cpu_exec_step_atomic(cs);
|
|
|
|
break;
|
|
|
|
case RISCV_EXCP_U_ECALL:
|
|
|
|
env->pc += 4;
|
|
|
|
if (env->gpr[xA7] == TARGET_NR_arch_specific_syscall + 15) {
|
|
|
|
/* riscv_flush_icache_syscall is a no-op in QEMU as
|
|
|
|
self-modifying code is automatically detected */
|
|
|
|
ret = 0;
|
|
|
|
} else {
|
|
|
|
ret = do_syscall(env,
|
2019-03-16 04:20:46 +03:00
|
|
|
env->gpr[(env->elf_flags & EF_RISCV_RVE)
|
|
|
|
? xT0 : xA7],
|
2018-04-11 21:56:49 +03:00
|
|
|
env->gpr[xA0],
|
|
|
|
env->gpr[xA1],
|
|
|
|
env->gpr[xA2],
|
|
|
|
env->gpr[xA3],
|
|
|
|
env->gpr[xA4],
|
|
|
|
env->gpr[xA5],
|
|
|
|
0, 0);
|
|
|
|
}
|
2021-11-22 21:47:33 +03:00
|
|
|
if (ret == -QEMU_ERESTARTSYS) {
|
2018-04-11 21:56:49 +03:00
|
|
|
env->pc -= 4;
|
2021-11-17 16:14:52 +03:00
|
|
|
} else if (ret != -QEMU_ESIGRETURN) {
|
2018-04-11 21:56:49 +03:00
|
|
|
env->gpr[xA0] = ret;
|
|
|
|
}
|
|
|
|
if (cs->singlestep_enabled) {
|
|
|
|
goto gdbstep;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case RISCV_EXCP_ILLEGAL_INST:
|
|
|
|
signum = TARGET_SIGILL;
|
|
|
|
sigcode = TARGET_ILL_ILLOPC;
|
|
|
|
break;
|
|
|
|
case RISCV_EXCP_BREAKPOINT:
|
|
|
|
signum = TARGET_SIGTRAP;
|
|
|
|
sigcode = TARGET_TRAP_BRKPT;
|
|
|
|
sigaddr = env->pc;
|
|
|
|
break;
|
2021-01-09 01:42:53 +03:00
|
|
|
case RISCV_EXCP_SEMIHOST:
|
|
|
|
env->gpr[xA0] = do_common_semihosting(cs);
|
|
|
|
env->pc += 4;
|
|
|
|
break;
|
2018-04-11 21:56:49 +03:00
|
|
|
case EXCP_DEBUG:
|
|
|
|
gdbstep:
|
2018-10-19 20:49:57 +03:00
|
|
|
signum = TARGET_SIGTRAP;
|
2018-04-11 21:56:49 +03:00
|
|
|
sigcode = TARGET_TRAP_BRKPT;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n",
|
|
|
|
trapnr);
|
|
|
|
exit(EXIT_FAILURE);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (signum) {
|
|
|
|
target_siginfo_t info = {
|
|
|
|
.si_signo = signum,
|
|
|
|
.si_errno = 0,
|
|
|
|
.si_code = sigcode,
|
|
|
|
._sifields._sigfault._addr = sigaddr
|
|
|
|
};
|
2019-10-01 19:39:52 +03:00
|
|
|
queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
|
2018-04-11 21:56:49 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
process_pending_signals(env);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-04-11 21:56:33 +03:00
|
|
|
void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
|
|
|
|
{
|
2019-03-23 02:07:18 +03:00
|
|
|
CPUState *cpu = env_cpu(env);
|
2019-03-16 04:20:46 +03:00
|
|
|
TaskState *ts = cpu->opaque;
|
|
|
|
struct image_info *info = ts->info;
|
|
|
|
|
2018-04-11 21:56:49 +03:00
|
|
|
env->pc = regs->sepc;
|
|
|
|
env->gpr[xSP] = regs->sp;
|
2019-03-16 04:20:46 +03:00
|
|
|
env->elf_flags = info->elf_flags;
|
|
|
|
|
2021-10-20 06:16:57 +03:00
|
|
|
if ((env->misa_ext & RVE) && !(env->elf_flags & EF_RISCV_RVE)) {
|
2019-03-16 04:20:46 +03:00
|
|
|
error_report("Incompatible ELF: RVE cpu requires RVE ABI binary");
|
|
|
|
exit(EXIT_FAILURE);
|
|
|
|
}
|
2021-03-23 19:52:54 +03:00
|
|
|
|
|
|
|
ts->stack_base = info->start_stack;
|
|
|
|
ts->heap_base = info->brk;
|
|
|
|
/* This will be filled in on the first SYS_HEAPINFO call. */
|
|
|
|
ts->heap_limit = 0;
|
2018-04-11 21:56:33 +03:00
|
|
|
}
|