qemu/hw/xtensa/Makefile.objs

obj-y += mx_pic.o
obj-y += pic_cpu.o
obj-y += xtensa_memory.o
obj-$(CONFIG_XTENSA_SIM) += sim.o
obj-$(CONFIG_XTENSA_VIRT) += virt.o
obj-$(CONFIG_XTENSA_XTFPGA) += xtfpga.o
target/xtensa: add MX interrupt controller MX interrupt controller is a collection of the following devices accessible through the external registers interface: - interrupt distributor can route each external IRQ line to the corresponding external IRQ pin of selected subset of connected xtensa cores. It has per-CPU and per-IRQ enable signals and per-IRQ software assert signals; - IPI controller has 16 per-CPU IPI signals that may be routed to a combination of 3 designated external IRQ pins of connected xtensa cores; - cache coherecy register controls core L1 cache participation in the SMP cluster cache coherency protocol; - runstall register lets BSP core stall and unstall AP cores. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> 2013-02-17 16:38:58 +04:00			`obj-y += mx_pic.o`
hw: move boards and other isolated files to hw/ARCH Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> 2013-02-05 15:03:15 +04:00			`obj-y += pic_cpu.o`
hw/xtensa: extract xtensa_create_memory_regions XTFPGA boards should populate core memory regions the same way sim machine does. Move xtensa_create_memory_regions implementation to a separate file and use it to create instruction and data memory regions on XTFPGA boards. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> 2017-12-23 00:53:36 +03:00			`obj-y += xtensa_memory.o`
hw/xtensa/Makefile.objs: Build xtensa_sim and xtensa_fpga conditionally Add the new CONFIG_* values to default-config/xtensa*-softmmu.mak. Signed-off-by: Ákos Kovács <akoskovacs@gmx.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Message-Id: <20190202072456.6468-17-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> 2019-02-02 10:24:45 +03:00			`obj-$(CONFIG_XTENSA_SIM) += sim.o`
hw/xtensa: add virt machine virt machine is a sim machine with generic PCI host controller. Make common parts of sim machine initialization reusable. Add PCI controller at 0xf0000000 with PIO space at its base address, ECAM space at base address + 1M and MMIO space at base address + 64M. Connect IRQ lines to consecutive CPU external IRQ pins starting from 0. Instantiate network interfaces on virt machine. Xtensa linux kernel configuration virt_defconfig can successfully boot on this machine. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> 2018-09-11 02:33:24 +03:00			`obj-$(CONFIG_XTENSA_VIRT) += virt.o`
xtensa: rename CONFIG_XTENSA_FPGA to CONFIG_XTENSA_XTFPGA Match the symbol name that is used e.g. in Linux (drivers/spi/Kconfig). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> 2019-02-20 20:45:35 +03:00			`obj-$(CONFIG_XTENSA_XTFPGA) += xtfpga.o`